KR100541691B1 - Method for fabricating capacitor - Google Patents

Abstract

According to an aspect of the present invention, there is provided a method of manufacturing a capacitor, the method comprising: forming a first storage node contact to expose a portion of the substrate by forming a first insulating layer on a semiconductor substrate and then etching the first insulating layer; Forming a first plug to fill the storage node contact; sequentially forming a second insulating film and a third insulating film having different etching selectivity from the second insulating film and the second insulating film on the substrate including the first plug; Selectively etching the insulating layer to form a second storage node contact exposing a portion of the first plug; forming a spacer on a sidewall of the second storage node contact; and a second storage node contact including a nitride film spacer. Forming a second plug to fill the second plug; and a fourth insulating film exposing the second plug on the substrate including the second plug. Forming a turn, forming a storage node electrode on the substrate including the fourth insulating layer pattern, and then etching back the metal layer until the fourth insulating layer pattern is exposed to form the storage node electrode of the capacitor; And removing the fourth insulating layer pattern by wet etching, and simultaneously preventing the second insulating layer from being etched by using the remaining third insulating layer and the spacer as an etch barrier, and forming a dielectric layer and a plate electrode on the storage node of the capacitor. It includes a step.

Description

Capacitor manufacturing method {METHOD FOR FABRICATING CAPACITOR}

1A to 1H are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.

Figure 2 is a plan view for explaining the problem according to the prior art.

3A to 3J are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

The present invention relates to a capacitor manufacturing method, and more particularly, to a capacitor manufacturing method capable of preventing a wet liquid from penetrating into a lower insulating film in a process of wet etching and removing a sacrificial oxide film for forming a storage node electrode. It is about.

Recently, due to the development of miniaturized semiconductor process technology, high integration of memory products has been accelerated, unit cell areas have been greatly reduced, and operation voltage has been reduced. However, despite the reduced cell area, the charging capacity required for the operation of the memory device requires a sufficient capacitance of 25 fF / cell or more to prevent the occurrence of soft errors and shortening of the reflash time. have.

The method of increasing the capacitance may be a method of applying a semi-spherical silicon (HemiSpheric Glass) structure to the NO (Nitride-0xide) dielectric film, or a method using an Al 2 O 3 film having a high dielectric constant as a dielectric film. However, for devices below 100nm, it is difficult to secure sufficient capacitance with Al2O3 films, so dielectric materials with higher permittivity have been developed, as well as a method of applying metal instead of polysilicon doped with storage node electrodes. It became.

1A to 1H are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.

In the capacitor manufacturing method according to the related art, as shown in FIG. 1A, a first insulating layer 3 is formed on a semiconductor substrate 1 having a predetermined substructure, and then the first insulating layer is selectively etched to form a substrate. A first storage node contact 4 is formed that exposes a predetermined portion of the substrate. Subsequently, after depositing a first polysilicon film (not shown) on the entire surface of the substrate including the first storage node contact 4, the first polysilicon film is etched back until the first insulating film is exposed. A first plug 5 filling the storage node contact 4 is formed. Then, a second insulating film 7 is formed on the entire surface of the first plug 5 and the first insulating film 3.

Thereafter, as illustrated in FIG. 1B, the second insulating layer is selectively etched to form a second storage node contact 8 exposing a part of the first plug 5. Next, a second polycrystalline silicon film (not shown) is deposited on the entire surface of the substrate including the second storage node contact 8, and then the second polycrystalline silicon film is etched back to fill the second storage node contact 8. Two plugs 9 are formed. In this case, the second plug 9 is electrically connected to the first plug through the second storage node contact 8.

Then, as illustrated in FIG. 1C, the nitride film 11 and the third insulating film 13 are sequentially formed on the entire surface of the substrate including the second plug 9. In this case, the nitride film 11 serves as an etch stop film in a subsequent etching process. In addition, an oxide film is used for the first, second and third insulating films.

Thereafter, as illustrated in FIG. 1D, a third insulating layer is selectively etched using the nitride layer as an etch stop to form a third insulating layer pattern 13a exposing the second plug 9. In this case, the third insulating layer pattern 13a becomes a sacrificial oxide layer for forming a storage node electrode.

Subsequently, as illustrated in FIG. 1E, the TiN layer 15 for the storage node electrode 15 is formed on the entire surface of the substrate including the third insulating layer pattern 13a.

1F, the upper surface of the third insulating film pattern 13a is exposed by etching back the TiN film 15 for the storage node electrode. In this case, reference numeral 16, which is not described in FIG. 1F, is a TiN film for the storage node electrode remaining after the etch back process, and shows a storage node electrode of a capacitor having a cylinder structure.

Thereafter, as shown in FIG. 1G, the third insulating layer pattern is removed by a wet etching method. In this case, the third insulating layer pattern uses BOE (Buffer Oxide Etchant).

Subsequently, as shown in FIG. 1H, the dielectric layer 17 and the plate electrode 19 are sequentially formed on the storage node electrode 16 of the capacitor to complete the capacitor manufacturing.

Figure 2 is a plan view for explaining the problem according to the prior art, showing that a bunker defect (bunker defect) has occurred.

However, in the related art, the second plug structure is applied to reduce the contact resistance between the first plug and the storage node electrode, but the second plug does not completely cover the bottom surface of the storage node electrode. Therefore, during the wet etching process of removing the oxide layer pattern, the wet liquid (BOE) penetrates through the bottom surface of the dense storage node electrode to penetrate the second plug or penetrates between the storage node electrode and the nitride layer to form the second insulating layer. Etching, and as a result, there is a problem that causes a bunker defect, as shown in FIG.

In order to solve the above problems, an object of the present invention is to cover each of the upper and sidewalls of the second insulating layer with a nitride film, thereby wet etching and removing the sacrificial oxide film for forming the storage node electrode. It is an object of the present invention to provide a method of manufacturing a capacitor that can prevent penetration into an insulating film.

In order to achieve the above object, the capacitor manufacturing method according to the present invention comprises the steps of forming a first storage layer on the semiconductor substrate and then etching the first insulating layer to form a first storage node contact to expose a portion of the substrate, Forming a first plug to fill the first storage node contact; sequentially forming a second insulating film having a different etching selectivity from the second insulation film and the second insulating film on the substrate including the first plug; Selectively etching the insulating film and the second insulating film to form a second storage node contact exposing a portion of the first plug, forming a spacer on a sidewall of the second storage node contact, and a second including a nitride film spacer. Forming a second plug to fill a storage node contact; and a fourth to expose the second plug on a substrate including the second plug. Forming an insulating layer pattern, forming a storage node electrode on the substrate including the fourth insulating layer pattern, and then etching back the metal layer until the fourth insulating layer pattern is exposed to form the storage node electrode of the capacitor; And wet etching the fourth insulating layer pattern to remove the second insulating layer and simultaneously using the remaining third insulating layer and the spacer as an etch barrier so that the second insulating layer is not etched, and then the dielectric layer and the plate electrode are sequentially formed on the storage node of the capacitor. It characterized by including the step of forming.

It is preferable that a nitride film is used for the third insulating film and the spacer.

The fourth insulating film pattern is preferably removed using a wet liquid of any one of HF and BOE.

Preferably, the storage node electrode and the plate electrode use any one metal of TiN, TaN, HfN, Ru, RuO 2, Pt, Ir and IrO 2.

As the dielectric film, any one metal of Al ₂ O _3, HfO ₂ , HfO ₂ / AlO ₃ , and BST is preferable.

(Example)

3A to 3J are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

In the method of manufacturing a capacitor according to the present invention, as shown in FIG. 3A, after forming a first insulating layer 102 on a semiconductor substrate 100 having a predetermined substructure, the first insulating layer is selectively etched to form a substrate. A first storage node contact 103 is formed to expose a predetermined portion of the substrate. A first polycrystalline silicon film (not shown) is deposited on the entire surface of the substrate including the first storage node contact 103, and then the first storage node contact 103 is formed. The first polycrystalline silicon film is etched back to the point at which the insulating film is exposed to form a plug 104 for filling the first storage node contact 103. Then, the first plug 104 and the first insulating film 102 are formed. The second insulating film 106 and the third insulating film 108 are sequentially formed on the entire surface of the second insulating film 106. The third insulating film 108 may be formed of a material having an etch selectivity different from that of the second insulating film 106, for example, a nitride film. I use it.

Thereafter, as illustrated in FIG. 3B, the third and second insulating layers are selectively etched to form second storage node contacts 109 exposing a portion of the first plug 104. Subsequently, a first nitride film 110 is formed on the entire surface of the substrate including the second storage node contact 109.

Next, as shown in FIG. 3C, the first nitride layer is etched back to form a spacer 110a on the sidewall of the second storage node contact 109.

3D, a second polysilicon layer (not shown) is formed on the resultant, and then the second polysilicon layer is etched back to form a second storage node contact 109 including a spacer 110a. To form a second plug 112 for embedding the same.

Subsequently, as shown in FIG. 3E, the second nitride film 114 and the fourth insulating film 116 are sequentially formed on the entire surface of the substrate including the second plug 112.

3F, the fourth insulating layer is selectively etched using the fourth nitride layer as an etch stop to form a fourth insulating layer pattern 116a exposing the second plug 112.

Thereafter, as illustrated in FIG. 3G, the TiN layer 118 for the storage node electrode is formed on the entire surface of the substrate including the fourth insulating layer pattern 116a.

Next, as shown in FIG. 3H, the TiN layer for storage node electrodes is etched back to a point where the upper surface of the fourth insulating layer pattern 116a is exposed to form a storage node electrode 119 of a capacitor having a cylinder structure. do.

Thereafter, as shown in FIG. 3I, the fourth insulating film pattern is removed by a wet etching method. In this case, the fourth insulating film pattern uses BOE or HF. Meanwhile, in the wet etching process of the fourth insulating film pattern, the remaining third insulating film and the spacer serve as an etching barrier to prevent the wet liquid from penetrating into the second insulating film.

Subsequently, as illustrated in FIG. 3J, the dielectric film 120 and the plate electrode 122 are sequentially formed on the storage node electrode 119 of the capacitor to complete the capacitor manufacturing. At this time, the storage node electrode 119 and the plate electrode 122 uses any one metal of TiN, TaN, HfN, Ru, RuO2, Pt, Ir and IrO2. In addition, the dielectric layer 120 uses any one metal of Al ₂ O _3, HfO ₂ , HfO ₂ / AlO ₃ , and BST.

According to the present invention, the upper and sidewalls of the second insulating layer may be respectively wrapped by using a nitride layer to prevent wet liquid from penetrating into the second insulating layer during the removal process by wet etching the sacrificial oxide layer for forming the storage node electrode. have. Therefore, the occurrence of the barrier defect is prevented and the reliability of the device is improved.

Claims (5)

Forming a first storage layer contact on the semiconductor substrate and then etching the first insulating layer to form a first storage node contact to expose a portion of the substrate; Forming a first plug to fill the first storage node contact; Sequentially forming a second insulating film and a third insulating film having different etching selectivities from the second insulating film on the substrate including the first plug; Selectively etching the third insulating layer and the second insulating layer to form a second storage node contact exposing a portion of the first plug; Forming a spacer on a sidewall of the second storage node contact; Forming a second plug to fill a second storage node contact including the nitride film spacer; Forming a fourth insulating film pattern exposing the second plug on the substrate including the second plug; Forming a storage node electrode metal film on the entire surface of the substrate including the fourth insulating film pattern, and then etching back the metal film to a time point at which the fourth insulating film pattern is exposed, thereby forming a storage node electrode of a capacitor; Wet etching and removing the fourth insulating layer pattern, and simultaneously using the remaining third insulating layer and the spacer as an etch barrier so that the second insulating layer is not etched; And sequentially forming a dielectric film and a plate electrode on the storage node electrode of the capacitor. The method of claim 1, wherein the third insulating film and the spacer are formed of a nitride film. The method of claim 1, wherein the fourth insulating film pattern is removed using a wet liquid of any one of HF and BOE. The method of claim 1, wherein the storage node electrode and the plate electrode use any one of TiN, TaN, HfN, Ru, RuO 2, Pt, Ir, and IrO 2 metals. The method of claim 1, wherein the dielectric layer uses any one metal of Al ₂ O _3, HfO ₂ , HfO ₂ / AlO ₃ , and BST.

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