KR100532976B1 - Memory test circuit and its fail position search method - Google Patents

Abstract

The present invention relates to a memory test circuit and a method of searching for a fail position thereof. In the related art, in the case of storing the failed information in the catch RAM, it is impossible to find out where the fail occurred by reading from the pattern three times and storing the failed information. In order to find out where it happened, you have to read the pattern only once. In this case, the program length becomes long and it takes a lot of test time. Accordingly, the present invention compares the data read from the pattern with the reference data to determine the pass (PASS) and fail state (COMP1), and the catch RAM for storing the information failed in the comparator (COMP1) ( 70) and a CPI 80 for calculating a point where a fail occurs in a pattern by calculating a point of occurrence when a fail occurs in the comparator COMP1 and outputting information of a point calculated by the CPI 80 to a display device. It is equipped with a RAM 90 to display and display the exact fail position in real time, so that not only fast analysis is possible, but also the position where the fail occurred in real time enables complex pattern realization and short program length. I would have to.

Description

Memory test circuit and its fail position search method

The present invention relates to a memory test circuit for searching for a precise fail position in real time, and a fail position searching method thereof. In particular, the present invention provides a fast test and analysis by finding a fail position as a pattern progress time. In addition, the present invention relates to a memory test circuit and a method of searching for a fail position thereof, which can implement a complex pattern.

1 is a diagram of a conventional memory test circuit, as shown in FIG. 1, an address generator 10 for creating an address to be entered into a RAM, and data generation for creating data to be written to an address generated by the address generator 10. The unit 20, an address scrambler 3 that scrambles and generates an address generated by the address generator 10, and data generated by the data generator 20 and scrambling generated by the address scrambler 30 Waveform generator 40 for converting into a program signal using the given address, and a device under tester for writing the signal generated by the waveform generator 40 in a test pattern, and reading data from the test pattern (50) compares the data read from the device under tester unit 50 with the reference data to catch the failed data (70) It consists of a comparison unit (60) for light.

Looking at the prior art configured as described above is as follows.

When the address generator 10 generates an address to be entered into the RAM, the data generator 20 generates and outputs data to be written to the address, and the address scrambler 30 generates the address generated by the address generator 10. The address is scrambled and output.

Then, the waveform generator 40 converts the data generated by the data generator 20 and the scrambled address generated by the address scrambler 30 into a program signal to be used to provide the device under tester 50.

Then, the device under tester 50 provides a signal to the test pattern, reads data from the test pattern, and outputs the data to the comparator 60.

Accordingly, the comparison unit 60 compares the data provided by the device under tester unit 50 with the reference data to determine whether the data is FAILed.

As a result of the determination, if the data is failed, it is stored in the catch RAM 70.

Referring to a process of writing and reading data in a pattern in the device under tester unit 50, the device under tester unit 50 writes '0' to all chips while increasing an address.

Then read one cell and write '1' to that cell. This is done on all chips.

It writes a '1' to the entire chip, reverses the address, reads a cell and then writes a '0' to that cell. This is done on all chips.

Read '0' from the previous chip.

This read '1' or '0' is provided to the comparator 60.

Accordingly, the comparator 60 stores the catch RAM 70 when a fail occurs in comparison with the reference data.

However, in the prior art as described above, in storing the failed information in the catch RAM, it is not possible to find out where the failure occurred by reading from the pattern three times and storing it, and finding out where the failed information occurred. In order to read the pattern only once, in this case, the length of the program is long, which causes a lot of test time.

Accordingly, an object of the present invention for solving the conventional problems as described above is to provide a memory test circuit and a fail position search method thereof to determine the exact fail position in real time.

Another object of the present invention is to provide a memory test circuit and a fail position search method thereof, which enables fast testing even in a complicated pattern.

The present invention for achieving the above object is a first step of determining whether a pass (PASS) state or a fail state by comparing the information read from the pattern and the reference data, and the fail information when judged as the fail state A second step of storing the data in the catch RAM, a third step of calculating a point of occurrence of a fail in the pattern by calculating an occurrence time using an internal clock when the first state is determined to be a fail state; The fourth step of reading the specific information of the point from the RAM to display on the display device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

According to a fail location search method of a memory test circuit of the present invention, a first step (S11) of comparing a state read from a pattern with reference data to determine whether a pass state or a fail state is performed, and the fail state. If it is determined that the fail information is stored in the catch RAM 2nd step (S12), and when the failure state in the first step (S11) using the internal clock to calculate the occurrence point of the point where the fail occurred in the pattern And a fourth step (S14) of reading the specific information of the calculated point from the RAM and displaying it on the display device.

As described above, the memory test circuit of the present invention for performing the method consisting of each step compares the data read from the pattern with the reference data, as shown in FIG. 2, in a PASS and FAIL state. Comparator (COMP1) to determine the, the catch RAM (70) for storing the information failed in the comparator (COMP1), and when the failure occurs in the comparator (COMP1) to calculate the occurrence point of the point where the fail occurs in the pattern It is composed of a CAPI oil 80 to be calculated, and a RAM 90 to display and display the information of the point calculated by the CPI 80 to a display device.

Referring to the operation and effect of the present invention configured as described in detail as follows.

The comparator COMP1 compares the information read from the test pattern with the reference data to determine whether it is in a PASS state or a FAIL state (S11).

As a result of the determination, if the information read from the test pattern and the reference data are the same and pass state (PASS), it is left as it is, and if the information read from the test pattern and the reference data are different and judged to be a fail state, the determined fail The information is stored in the catch RAM 70 and a notification is generated in the double C. 80 (S12).

The CPI 80 which receives the fail information from the comparator COMP1 calculates a time point (current time) at which the fail information is received using the internal clock, and calculates a point where the fail occurs in the test pattern. (90). (S13)

Then, the RAM 90 selects the information of the point generated by the CPI 80 and transmits it to the display device for display.

Therefore, by looking at the information displayed on the display device it is possible to know the point where the failure occurred.

The CPI 80 returns to the initial condition until another fail occurs.

As described above, it is possible to identify the cause of the fail in real time in the CAPI (80), it is possible to quickly analyze, it is possible to find out the exact location of the failure is possible to implement a complex pattern.

In addition, the program can be shortened by quickly determining where the fail occurred.

Therefore, the present invention finds the exact fail position in real time, so that not only a quick analysis is possible but also a position where the fail occurs in real time, so that a complicated pattern can be realized and the program length can be shortened.

1 is a conventional memory test circuit diagram.

2 is a memory test circuit diagram of the present invention.

*** Explanation of symbols for main parts of drawing ***

10: address generator 20: data generator

30: address scrambler 40: waveform generator

50: device under tester 60: comparison unit

70: catch ram 80: C

90: ram

Claims (2)

A comparator COMP1 that compares the data read from the pattern with the reference data to determine a pass and fail status, a catch RAM 70 that stores information failed by the comparator COMP1; When the fail occurs in the comparator COMP1, the occurrence time of the fail is calculated in real time using an internal clock to calculate the point where the fail occurs in the pattern, and the information of the point calculated by the seed oil 80 is displayed. And a RAM (90) for output to the device and display. A first step of determining whether a PASS state or a FAIL state is compared by comparing the information read from the pattern with the reference data; and a second step of storing the fail information in the catch RAM when determining the fail state. And a third step of calculating a point in which a fail occurred in the pattern by calculating an occurrence time in real time using an internal clock when determining the fail state in the first step, and specifying specific information of the calculated point as a RAM. 4. A method of searching for a fail position of a memory test circuit according to claim 4, wherein the step of reading from the display device is performed.