JP4678994B2 - Memory failure relief analysis method and memory test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory defect repair analysis method for determining whether or not a defective cell of a memory can be repaired by a spare line provided in a spare area, and a memory test apparatus that operates according to the defect repair analysis method.
[0002]
[Prior art]
FIG. 3 shows the configuration of a general memory test apparatus. In the figure, 11 is a timing generator 12 is a pattern generator, 13 is a waveform shaper, DUT is a memory under test, 14 is a logical comparator, 15 is a failure analysis memory, 16 is a failure relief analyzer, and 17 is an operation of each part. A tester controller for controlling The pattern generator 12 generates test pattern data according to various timing signals output from the timing generator 11. The test pattern data includes an address signal applied to the memory under test DUT, data to be written into the memory under test DUT, a control signal for controlling the operation of the memory under test DUT, and the like.
[0003]
The test pattern data generated by the pattern generator 12 is composed of a digital signal. The test pattern data composed of this digital signal is converted into a test pattern signal having an actual waveform (logic waveform of 1 and 0) by the waveform shaper 13, and the test pattern signal is applied to the memory under test DUT. The memory under test DUT stores the applied test pattern at the address according to the address signal included in the test pattern signal. At the same time, data is read from each address of the memory under test DUT, and the logical comparator 14 compares the read data with the expected value output from the pattern generator 12. If a mismatch occurs as a result of the comparison, fail data representing the mismatch is applied to the failure analysis memory 15. At this time, the address signal applied to the memory under test DUT is also supplied to the failure analysis memory 15, and the fail data is stored at the address where the mismatch occurs.
[0004]
FIG. 4 shows an internal configuration of the semiconductor memory MEMO capable of repairing a defective cell. The semiconductor memory MEMO capable of repairing a defective cell includes a spare memory cell group (hereinafter referred to as a spare area) 21 in addition to the original memory cell group 20, and a defective cell is detected in the original memory cell group 20. In this case, a defective memory can be made good by detecting an address line in which a defective cell exists and electrically replacing the address line with a spare line provided in the spare area 21. FIG. 5 shows an internal state of the failure analysis memory 15 for storing fail data. Here, in order to simplify the description, the inside of the failure analysis memory 15 will be described as being substantially equivalent to the internal structure of the semiconductor memory MEMO shown in FIG.
[0005]
That is, it is assumed that the defect analysis memory 15 also has a main memory area 15A corresponding to the original memory cell group 20 in the same manner as the memory MEMO capable of repairing a defective cell. In addition to the main memory area 15A, the spare area 21 and A description will be given assuming that the corresponding auxiliary storage area 15B exists. Also, here, the address lines arranged in the main storage area 15A, 15C is the row address line, address line 15D is the column address line, address line 15E arranged in the auxiliary storage area 15B is the spare row address line, and 15F is the spare. This will be referred to as a column address line.
[0006]
Next, a failure relief analysis method for determining whether failure repair is possible by analyzing the fail data fetched into the failure analysis memory 15 will be described with reference to FIGS. FIG. 6 shows a process of reading the inside of the defect analysis memory 15 in the row address direction and the column address direction and counting the number of failures on each address line. This counting process is generally called a scanning operation. Reference numerals 16A and 16B denote memories for storing the counted number of failures. FIG. 7 shows a process in which the number of failures on each address line obtained by the scan operation is searched, and an operation for searching for address lines whose number of failures on each address line is greater than the number of orthogonal spare lines is performed. . This operation is called a search operation. If the number of failures on the address line is greater than the number of orthogonal spare lines, the address line cannot be repaired unless it is replaced with a spare line parallel to the address line where the defective cell exists. This is called an address line MRAL (Must Repair Address LINE).
[0007]
FIG. 8 shows a state in which the D-scan operation is executed. This D-scan operation is an operation of subtracting the number of repaired defective cells from the memories 16A and 16B, assuming that the repair address line MRAL is repaired by the spare line 15D by the search operation shown in FIG. The search operation shown in FIG. 7 and the D-scan operation shown in FIG. 8 are repeatedly executed until no mass repair address is detected. FIG. 9 searches for a fail address (hereinafter referred to as a bit fail address) that is not a mass repair, based on the number of failures remaining when the mass repair address line is no longer detected. This operation is generally called a fail search operation.
[0008]
Failure recovery is performed by analyzing how a spare line is replaced for a defective cell from the mass repair address line MRAL and the bit fail address obtained as described above.
[0009]
[Problems to be solved by the invention]
In the arrangement of defective cells shown in FIG. 10, when the row address line 15D-1 determined to be the mass repair address line MRAL is repaired by the spare line 15D-2, when the D-scan operation is executed, Assuming that the number of defective cells is decremented by 1 and the number of defective cells in the spare area 15B is decremented by 1, and the defective cells are relieved as shown in FIG. There is a drawback that it becomes unclear whether there is a defective cell in 15B.
[0010]
In order to detect the fail pattern existing in the spare area on the mast repair address line in the state before the D-scan operation, for example, once the fail search operation shown in FIG. 9 is executed after the scan operation shown in FIG. Good. However, as shown in FIGS. 6 to 9, the defect remedy analysis is programmed in advance to perform the scan operation, the search operation, the D-scan operation, and the fail search operation in this order. If the fail search operation is performed after the operation, the time during which the fail search operation is performed is added to the conventional defect remedy analysis time, so that the time required for the defect remedy analysis becomes long.
[0011]
SUMMARY OF THE INVENTION An object of the present invention is to provide a memory defect repair analysis method and memory test capable of acquiring defective cell position information in a spare area on a mast repair address line before a D-scan operation within a time required for conventional defect analysis. The device is to be provided.
[0012]
[Means for Solving the Problems]
According to a first aspect of the present invention, a mast repair address line is detected in which the number of defective cells existing on each address line is larger than the number of spare lines in a direction orthogonal to the address line, and the mast repair address line is detected. A failure recovery analysis method for a memory that reads fail data in the upper spare area, obtains a fail pattern indicating the arrangement of defective cells in the spare area, and stores the fail pattern and an address indicating a mast repair address line in the fail pattern memory. suggest.
[0013]
According to a second aspect of the present invention, a failure analysis memory having an address area equivalent to that of the memory under test, and the same address as the address where the failure cell of the failure analysis memory is detected each time a failure cell is detected from the memory under test Fail data writing means for writing the fail data into the failure data reading means, fail data reading means for reading the presence of the fail data on the row address line or the column address line of the failure analysis memory, and the fail data read by the fail data reading means Detecting a fail-repair address line, detecting a fail pattern indicating a defective cell position in a spare area on the return address line; and detecting a fail pattern and a fail pattern memory for storing an address at which the fail pattern is generated. Equipped with memory test equipment To draft.
[0014]
Action
According to the defect repair analysis method and the memory test apparatus of the present invention, a fail pattern representing a defective cell position in the spare area on the mast repair address line is detected during execution of the D-scan operation in the normal defect repair process. since this failure pattern in the spare area on the must-repair address lines and stores the addresses of the must-repair address line failure pattern memory, in a state before executing the D- scanning operation within a conventional defect relief processing time It is possible to obtain defective cell position information on the spare area side on the mass repair address line. Therefore, there is an advantage that the failure pattern on the spare area side on the mast repair address line can be acquired together with the failure repair analysis result while the analysis processing time for failure repair is exactly the same as the conventional one.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a fail pattern storage unit added to the output side of the failure analysis memory 15 according to the present invention. In FIG. 1, 31 is a row address generator, and 32 is a column address generator. The row address generator 31 and the column address generator 32 are provided for reading the fail data stored in the failure analysis memory 15. The row address signal and the column address signal generated by the row address generator 31 and the column address generator 32 are formatted into an address signal for the failure analysis memory 15 by the formatter 33-3, and are sent to the address signal input terminal An of the failure analysis memory 15. Entered.
[0016]
Here, the row address is fixed to a certain address, and in this state, the column address is changed by +1 from the first address to the last address, and at the same time the column address reaches the last address and returns to the first address, the row address is changed to +1. In the following description, the failure data on each row address line in the failure analysis memory 15 is read. The row address signal generated by the row address generator 31 is input to the data input terminal _Di1 of the fail pattern memory 35 through the formatter 33-1. The column address signal generated by the column address generator 32 is also taken out as a bit signal representing each spare line in the spare area by the decoder 36 through the formatter 33-2, and this bit signal is taken as each spare line (here, the spare line on the column side). Are input to one input terminal of each of the gates G1 to Gn provided corresponding to.
[0017]
On the other hand, a gate 37 is provided on the output side of the failure analysis memory 15 to detect that a defective cell has been read from the failure analysis memory 15 in the spare area. That is, a spare area signal indicating that the spare area is accessed from the formatter 33-2 and fail data read from the defect analysis memory 15 are input to the gate 37. Therefore, when a fail is read out in the spare area, the gate 37 outputs “1” logic, and the fail data of “1” logic is applied to the other input terminal of each of the gates G1 to Gn.
[0018]
With this configuration, every time a column address is incremented by 1 in the spare area, when fail data of “1” logic is read from each column address (corresponding to a spare column address line), the gates G1 to Gn corresponding to the column address "1" logic is output from any of the above. Pattern registers 38-1 to 38-n are provided corresponding to the gates G1 to Gn, respectively. In this example, the pattern registers 38-1 to 38-n are configured by JK flip-flops. A “1” logic signal is applied to the K terminal of each JK flip-flop at the start of D-scan. The D-scan operation is started, and “0” logic is continuously applied to the K terminal during the D-scan operation.
[0019]
The outputs of the gates G1 to Gn are applied to the J input terminals of the corresponding fail pattern registers 38-1 to 38-n. By giving "1" logic to the K terminal at the start of D-scan, the outputs of the fail pattern registers 38-1 to 38-n are aligned with "0" logic. When “0” logic is applied to the J input terminal in a state where the input signal applied to the input terminal K is returned to “0” logic, the outputs of the fail pattern registers 38-1 to 38-n are “0”. Continue to maintain logic. When fail data is read from the defect analysis memory 15 in the spare area, “1” logic is input to the J input terminal of the fail pattern register corresponding to the read column address. When "1" logic is input to the J input terminal, the input fail pattern registers 38-1 to 38-n read "1" logic.
[0020]
Therefore, for example, in a state in which the mass repair address line MRAL shown in FIG. 2 is read, the fail pattern “1010001” is stored in the fail pattern registers 38-1 to 38-n. The fail pattern is input to the data input terminal D _i2 of the fail pattern memory 35, and the fail pattern is stored in the fail pattern memory 35. In accordance with the address generated by the address generator 39, the fail pattern memory 35 moves the storage address, for example, by +1 from the head address, and stores the fail pattern.
[0021]
As shown in FIG. 2, in addition to the column fail pattern 35A, the fail pattern memory 35 also stores a row address 35B representing a mass repair address line together with the fail pattern 35A. Although the case where the column fail pattern 35A is stored has been described above, the D-scan operation is executed in the row address direction in addition to the column address direction described above. When executing the D-scan operation in the row address direction, the column address is fixed, the row address pattern is read by +1 address in the row address direction to obtain a row fail pattern, and this row fail pattern is stored in the fail pattern memory 35. The storing can be easily understood from the above description.
[0022]
【The invention's effect】
As described above, in the present invention, in the process of performing the defect repair process using the fail data stored in the defect analysis memory 15, the column fail pattern or the row fail pattern of the spare area is obtained during the D-scan operation. Since this fail pattern is stored in the fail pattern memory 35, time is not spent other than the defect repair processing. Therefore, since the fail pattern of the spare area on the mast repair address line can be acquired within the time range for executing the defect repair processing as in the conventional case, time is not wasted. Therefore, the defect relief processing time does not become long, and there is an advantage that both the defect relief processing and the fail pattern acquisition in the spare area can be executed in a short time.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of a main part of the present invention.
FIG. 2 is a diagram for explaining the operation of FIG. 1;
FIG. 3 is a block diagram for explaining an outline of a general memory test apparatus;
FIG. 4 is a diagram for explaining an internal structure of a memory capable of repairing a defective cell.
FIG. 5 is a diagram for explaining an internal structure of a failure analysis memory that stores fail data of a semiconductor memory capable of repairing a defective cell;
FIG. 6 is a diagram for explaining a scan operation in a memory defect repair process;
FIG. 7 is a diagram for explaining a search operation in a memory defect repair process;
FIG. 8 is a diagram for explaining a D-scan operation in the process of memory defect repair processing;
FIG. 9 is a diagram for explaining a fail search operation in a memory defect repair process;
FIG. 10 is a diagram for explaining a conventional inconvenience.
FIG. 11 is a diagram for explaining a conventional inconvenience similar to FIG. 10;
[Explanation of symbols]
11 Timing generator 12 Pattern generator 13 Waveform shaper 14 Logic comparator 15 Failure analysis memory 16 Failure repair analyzer 17 Tester controller 20 Original memory cell group 21 Spare area MRAL Mast repair address line 31 Row address generator 32 Column Address generators 33 and 34 Formatter 35 Fail pattern memory 36 Decoder 37 Gates 38-1 to 38 -n fail pattern register 39 for detecting that fail data is read in the spare area Address generator

Claims (2)

Detects a mast repair address line in which the number of defective cells existing on each address line is larger than the number of spare lines in a direction perpendicular to the address line ,
Read the fail data of the spare area on this mast repair address line ,
Find a fail pattern that represents the placement of defective cells in the spare area,
The fail pattern and the address indicating the mast repair address line are stored in the fail pattern memory.
And a memory defect repair analysis method. A failure analysis memory having an address area equivalent to the memory under test;
Fail data writing means for writing fail data to the same address as the address where the defective cell is detected in the failure analysis memory each time a defective cell is detected from the memory under test;
Fail data reading means for reading the presence of fail data on the row address line or column address line of the failure analysis memory;
Means for detecting a mast repair address line from the fail data read by the fail data reading means ;
Means for detecting a fail pattern representing a defective cell position in a spare area on the mast repair address line;
A fail pattern memory for storing the fail pattern and an address where the fail pattern is generated;
A memory test apparatus comprising:

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