KR100525100B1 - Method for forming storge node electrodes of capacitor - Google Patents
Method for forming storge node electrodes of capacitor Download PDFInfo
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- KR100525100B1 KR100525100B1 KR10-2003-0076581A KR20030076581A KR100525100B1 KR 100525100 B1 KR100525100 B1 KR 100525100B1 KR 20030076581 A KR20030076581 A KR 20030076581A KR 100525100 B1 KR100525100 B1 KR 100525100B1
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000003990 capacitor Substances 0.000 title abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000012071 phase Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012808 vapor phase Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 101000965313 Legionella pneumophila subsp. pneumophila (strain Philadelphia 1 / ATCC 33152 / DSM 7513) Aconitate hydratase A Proteins 0.000 claims 1
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000006884 silylation reaction Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000006552 photochemical reaction Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
본 발명은 캐패시터의 스토리지노드 콘택 형성방법에 관해 개시한 것으로서, 반도체기판 위에 옥사이드막을 형성하는 단계와, 옥사이드막 위에 제 1감광막을 도포하고 베이킹 공정을 진행하여 버텀 감광막을 형성하는 단계와, 버텀 감광막 위에 제 2감광막을 도포하고 나서, 노광하고 습식 현상 공을 진행하여 스토리지노드 콘택 영역을 노출시키는 탑 감광막을 형성하는 단계와, 탑 감광막에 증기상 실릴레이션 처리를 실시하여 측면 프로파일을 버터킬하게 제조하는 단계와, 탑 감광막을 마스크로 하고 상기 버텀 감광막을 건식 현상하는 단계와, 상기 결과의 탑 감광막 및 버텀 감광막을 마스크로 이용하여 출력 위상 펄스조절을 통해 상기 옥사이드막을 식각하여 스토리지노드 콘택을 형성하는 단계를 포함한다.The present invention relates to a method of forming a storage node contact of a capacitor, comprising the steps of forming an oxide film on a semiconductor substrate, applying a first photoresist film on the oxide film and performing a baking process to form a bottom photoresist film; Applying a second photoresist film thereon, exposing and performing a wet developing hole to form a top photoresist film exposing the storage node contact region; and vapor phase silication treatment on the top photoresist film to produce buttery side profile. Dry-developing the bottom photoresist with a top photoresist as a mask, and etching the oxide film through output phase pulse control using the resulting top photoresist and bottom photoresist as a mask to form a storage node contact Steps.
Description
본 발명은 캐패시터 형성방법에 관한 것으로, 보다 구체적으로는 SIYAL(Silylation Treatment After Alkaline Wet Development)기술을 적용시켜 감광막 두께를 증가시키면서 스토리지노드 콘택 패턴의 해상도를 높이고, 건식 현상 및 출력 위상 펄스조절(out phase pulse modulation)을 적용시켜 이온의 직진성을 높여 종횡비에 따른 식각정지를 방지할 수 있는 캐패시터의 스토리지노드 콘택 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and more specifically, to increase the resolution of a storage node contact pattern while increasing the photoresist film thickness by applying SIYAL (Silylation Treatment After Alkaline Wet Development) technology, dry phenomenon and output phase pulse control (out) The present invention relates to a method of forming a storage node contact of a capacitor capable of preventing etch stop due to an aspect ratio by applying phase pulse modulation.
반도체 디바이스가 고집적화될수록 패턴 해상도는 감소된다. 따라서, 이러한 패턴 해상도 문제를 해결하기 위해 감광막 두께를 감소시키는 방법을 이용하여 캐패시터의 스토리지노드 콘택을 형성하고 있으나, 실제적으로 감광막 두께가 감소하게 되면 식각 선택비 부족으로 인해 식각 완료되기도 전에 감광막이 없어져 스토리지노드 콘택의 상부 부위 손실, 줄무늬(striation)현상, CD(Critical Dimension) 불안정 등을 유발시켜 디바이스에 악영향을 미친다.As semiconductor devices become more integrated, pattern resolution decreases. Therefore, in order to solve the pattern resolution problem, the storage node contact of the capacitor is formed using a method of reducing the thickness of the photoresist film. However, when the photoresist film thickness decreases, the photoresist film disappears before the etching is completed due to insufficient etching selectivity. This can adversely affect the device by causing loss of the top portion of the storage node contacts, streaks, and critical dimension (CD) instability.
또 다른 해결방안으로 다결정실리콘 하드마스크를 이용하여 식각선택비 부족의 문제를 극복하고 있으나, 이러한 방법은 공정이 복잡해질 뿐만 아니라 다결정 실리콘 하드마스크 위의 패턴 해상도도 떨어져 공정 상에 많은 부담을 주고 있다. 또한, 스토리지노드 콘택의 높은 종횡비로 인해 식각 정지 또는 포지티브 슬로프 (positive slope)가 발생되며, 이로써 이 후 캐패시터의 정전용량을 저하시키거나 페일(fail)을 유발시키는 문제점이 있다.Another solution is to overcome the problem of lack of etching selectivity by using polysilicon hard mask. However, this method not only complicates the process but also reduces the resolution of the pattern on the polycrystalline silicon hardmask. . In addition, an etch stop or a positive slope occurs due to the high aspect ratio of the storage node contact, thereby lowering the capacitance of the capacitor or causing a fail.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 다결정 실리콘 하드마스크 적용을 생략하여 스토리지노드 콘택 제조 공정을 단순화할 수 있는 캐패시터의 스토리지노드 콘택 형성방법을 제공하려는 것이다.Accordingly, an object of the present invention is to provide a method of forming a storage node contact of a capacitor that can simplify the storage node contact manufacturing process by omitting the application of a polycrystalline silicon hard mask.
본 발명의 다른 목적은 감광막 두께를 증가시키면서 패턴 해상도를 높일 수 있는 SILYAL 기술을 이용하고, 건식 현상 및 출력 위상 펄스조절을 통해 이온의 직진성을 높여 종횡비에 따른 식각정지를 방지하여 스토리지노드 콘택의 측면 프로파일을 버티컬하게 제조할 수 있는 캐패시터의 스토리지노드 콘택 형성방법을 제공하려는 것이다.Another object of the present invention is to use the SILYAL technology to increase the pattern resolution while increasing the thickness of the photoresist layer, and to prevent the etch stop due to the aspect ratio by increasing the linearity of the ions through the dry phenomenon and the output phase pulse control to the side of the storage node contact An object of the present invention is to provide a method of forming a storage node contact of a capacitor capable of vertically manufacturing a profile.
상기 목적들을 달성하기 위한 본 발명에 따른 캐패시터의 스토리지노드 콘택 형성방법은 반도체기판 위에 옥사이드막을 형성하는 단계와, 상기 옥사이드막 위에 제 1감광막을 도포하고 베이킹 공정을 진행하여 하부 감광막을 형성하는 단계와, 상기 하부 감광막 위에 화학 증폭형의 제 2감광막을 도포한 후 노광 및 습식 현상하여 스토리지노드 콘택 영역을 노출시키는 상부 감광막을 형성하는 단계와, 상기 상부 감광막에 증기상 실릴레이션 처리를 실시하여 측면 프로파일이 버티컬한 구조를 갖도록 하는 단계와, 상기 상부 감광막을 마스크로 하여 상기 하부 감광막의 노출된 부분을 건식 현상하는 단계와, 상기 상부 감광막 및 하부 감광막을 마스크로 이용하여 출력 위상 펄스조절을 통해 상기 옥사이드막의 노출된 부분을 식각하여 스토리지노드 콘택을 형성하는 단계를 포함한 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a storage node contact of a capacitor, the method comprising: forming an oxide film on a semiconductor substrate, applying a first photosensitive film on the oxide film, and performing a baking process to form a lower photosensitive film; And forming an upper photoresist film on which the second photoresist of chemical amplification type is applied on the lower photoresist film, followed by exposure and wet development to expose a storage node contact region, and performing vapor phase silication treatment on the upper photoresist film to obtain a side profile. The vertical structure, dry developing the exposed portion of the lower photoresist film using the upper photoresist film as a mask, and output oxide pulse control using the upper photoresist film and the lower photoresist film as a mask. Etch exposed portions of the membrane to And forming a tack.
상기 베이킹 공정은 200℃온도에서 1분동안 진행하는 것이 바람직하다.The baking process is preferably carried out for 1 minute at 200 ℃ temperature.
상기 제 2감광막은 0.07㎛ 두께로 도포하는 것이 바람직하다.It is preferable to apply the second photosensitive film to a thickness of 0.07 μm.
삭제delete
상기 건식 현상 공정은 MICP타입의 식각장치 내에서 진행하며, O2 또는 SO2 가스 공급에 의한 산소플라즈마를 이용하는 것이 바람직하다.The dry developing process is performed in an MICP type etching apparatus, and it is preferable to use an oxygen plasma by O 2 or SO 2 gas supply.
상기 출력위상 펄스조절 가스는 C4F8 또는 C5F8 가스를 이용하는 것이 바람직하다.The output phase pulse control gas is preferably C4F8 or C5F8 gas.
본 발명은 스토리지노드 콘택 형성에 있어서, 다결정 실리콘 하드마스크 적용을 생략하여 공정을 단순화시킨다. The present invention simplifies the process by omitting the application of polycrystalline silicon hardmask in forming storage node contacts.
또한, 본 발명은 감광막에 습식 현상 공정 이후에 진행되는 실릴레이션 처리 공정인 SILYAL기술을 적용시켜 감광막의 두께를 증가시키면서 패턴의 해상도를 높이며, 또한 MICP타입의 식각장치에서 건식현상 공정을 실시하고 출력 위상 펄스조절을 통해 옥사이드막 식각 시 이온의 직진성과 충돌성을 증가시켜 높은 종횡비에 따른 식각정지를 방지하고 버티컬한 측면 프로파일을 형성한다.In addition, the present invention increases the resolution of the pattern while increasing the thickness of the photosensitive film by applying SILYAL technology, which is a silylation process performed after the wet developing process, and also performs a dry developing process in an MICP type etching apparatus. Phase pulse control increases the linearity and collision of ions during oxide film etching, preventing etch stop due to high aspect ratio and forming vertical side profile.
(실시예)(Example)
도 1a 내지 도 1c는 본 발명에 따른 캐패시터의 스토리지노드 콘택 형성방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a storage node contact of a capacitor according to the present invention.
본 발명에 따른 캐패시터의 스토리지노드 콘택 형성방법은, 도 1a에 도시된 바와 같이, 소정의 하부패턴을 가진 반도체기판(1) 상에 옥사이드막(2)을 형성하고 나서, 상기 옥사이드막(2) 위에 제 1감광막(미도시)을 도포하고 200℃온도에서 1분동안 베이킹 공정을 진행함으로서, 상기 감광막을 경화시킨 하부 감광막(5)을 형성한다.In the method of forming a storage node contact of a capacitor according to the present invention, as shown in FIG. 1A, an oxide film 2 is formed on a semiconductor substrate 1 having a predetermined lower pattern, and then the oxide film 2 is formed. The first photoresist film (not shown) is applied thereon and a baking process is performed at 200 ° C. for 1 minute to form the lower photoresist film 5 on which the photoresist film is cured.
이어, 상기 하부 감광막(5) 위에 제 2감광막(미도시)을 도포하고 나서, 노광하고 습식 현상 공정을 진행하고, 다시 증기상 실릴레이션 처리(vapor phase silylation treatment)를 실시하여 스토리지노드 콘택영역을 노출시키는 상부 감광막(6)을 형성한다. 이때, 습식 현상 공정을 진행한 다음, 증기상 실릴레이션 처리하는 공정을 SILYAL(Silylation Treatment After Alkaline Wet Development)이라고 한다.Subsequently, after applying a second photoresist film (not shown) on the lower photoresist film 5, the photoresist film is exposed, a wet development process is performed, and a vapor phase silylation treatment is performed again to form a storage node contact region. An upper photosensitive film 6 to be exposed is formed. In this case, a process of performing a wet developing process followed by a vapor phase sillation treatment is referred to as SILYAL (Silylation Treatment After Alkaline Wet Development).
상기 상부 감광막(6)은 화학증폭(Chemical Amplified)형 감광막으로서, 빛을 흡수할 수 있는 염료(dye)가 다량 함유되어 있어 상부 감광막(6)의 광 투과율은 매우 낮다. 그리고 상기 상부 감광막(6)을 0.07㎛두께로 얇게 형성하는데, 그 이유로는 감광막 두께가 낮으면 패턴의 해상도가 좋으며, 하부의 하부 감광막이 경화된 상태이므로 난반사가 미소하기 때문에 두껍게 형성할 필요가 없다.The upper photosensitive film 6 is a chemically amplified photosensitive film, and contains a large amount of dye capable of absorbing light, so that the light transmittance of the upper photosensitive film 6 is very low. The upper photoresist film 6 is thinly formed to a thickness of 0.07 μm. For this reason, if the photoresist film thickness is low, the resolution of the pattern is good, and since the lower photoresist film is hardened, diffuse reflection does not need to be made thick. .
한편, 상기 감광막의 감광된 부분은 광화학 반응을 일으켜 고분자의 체인 구조들이 끊어지고 분자량이 작은 저분자 구조로 변화되며, 상기 변화된 구조의 감광막 부분에 증기상 실릴레이션 처리 공정을 실시하게 되면, 즉, 규소(Si)가 함유된 기체(4) 내에서 고온으로 가열하면, 저분자 구조로 변화된 감광막 부분에 규소가 치환되어 결합되며, 이 과정에서 상부 감광막(6)의 측면 프로파일이 버티컬하게 된다. On the other hand, the photosensitive part of the photoresist film causes a photochemical reaction to break the chain structure of the polymer and change to a low molecular weight structure having a small molecular weight, and when the vapor phase silylation treatment process is performed on the photoresist part of the changed structure, that is, silicon When heated to a high temperature in the substrate 4 containing (Si), silicon is substituted and bonded to a portion of the photosensitive film which has been changed to a low molecular structure, and in this process, the side profile of the upper photosensitive film 6 is vertical.
그런 다음, 도 1b에 도시된 바와 같이, 상기 결과의 기판을 MICP(Magnetized Inductively Coupled Plasma)타입의 식각장치(etcher) 내로 이송시킨 다음, SO2 또는 O2가스 공급에 의한 O2플라즈마를 이용하여 건식 현상 공정(7)을 실시함으로서 하부 감광막(5)을 식각한다. 이때, 상기 건식 현상 공정(7) 결과, 상부 감광막(6)은 산화되면서 하부 감광막(5)은 식각되며, 상기 하부 감광막은 과다 식각(undercut)을 일으키지 않고 하부 감광막(5)에 버티컬한 측면 프로파일 가공을 가능하게 한다. 또한, 상기 상부 감광막(6)이 산화됨에 따라, 상부 감광막(6) 및 하부 감광막(5)의 총 두께가 높아지고 패턴의 해상도가 매우 양호하여 이후의 옥사이드막 식각 마진을 증가시킨다.Then, as shown in FIG. 1B, the resultant substrate is transferred into an etching apparatus of a magnetized inductively coupled plasma (MICP) type, followed by a dry developing process using O 2 plasma by supplying SO 2 or O 2 gas. The lower photosensitive film 5 is etched by performing (7). At this time, as a result of the dry development process (7), the upper photoresist film (6) is oxidized while the lower photoresist film (5) is etched, and the lower photoresist film is vertical side profile to the lower photoresist film (5) without causing an overcut (undercut) Enable processing In addition, as the upper photoresist film 6 is oxidized, the total thickness of the upper photoresist film 6 and the lower photoresist film 5 is increased, and the resolution of the pattern is very good, thereby increasing the oxide film etching margin.
이 후, 도 1c에 도시된 바와 같이, C4F8 또는 C5F8 등의 가스를 이용하여 출력 위상 펄스조절(8)을 통해 옥사이드막을 식각함으로서 스토리지노드 콘택(C)을 형성한다. 이때, 상기 출력 위상 펄스조절(8)은 소오스 파워(source power) 온(on)시 바이어스 파워(bias power)는 오프(off)이고, 소오스 파워가 오프시 바이어스 파워는 온되는 방식으로 실시하되, 모듈레이션 주기(period)는 수μ∼수십μsec로 진행한다.Thereafter, as illustrated in FIG. 1C, the storage node contact C is formed by etching the oxide film through the output phase pulse control 8 using a gas such as C 4 F 8 or C 5 F 8. In this case, the output phase pulse control 8 is performed in such a manner that the bias power is turned off when the source power is turned on, and the bias power is turned on when the source power is turned off. The modulation period progresses from a few microns to several tens of microseconds.
한편, 상기 출력 위상 펄스조절(8) 결과, 옥사이드막 식각 시 이온(ion)의 직진성과 충돌성(bombardment)이 증가됨에 따라, 옥사이드막의 식각정지 또는 포지티브한 슬로프를 방지하여 스토리지노드 콘택(C)의 측면 프로파일을 버티컬하게 제조할 수 있다. On the other hand, as a result of the output phase pulse control 8, as the linearity and bombardment of ions are increased during the etching of the oxide film, the storage node contact (C) is prevented by preventing the etch stop or the positive slope of the oxide film. The side profile of can be prepared vertically.
이상에서와 같이, 본 발명은 스토리지노드 콘택 형성에 있어서, 다결정 실리콘 하드마스크 적용을 생략하여 공정을 단순화시킨다. As described above, the present invention simplifies the process by eliminating the application of a polycrystalline silicon hardmask in forming storage node contacts.
또한, 본 발명은 SILYAL기술을 적용시켜 감광막의 두께를 증가시키면서 패턴의 해상도를 높이며, MICP타입의 식각장치에서 건식현상 공정을 실시하고 출력 위상 펄스조절을 통해 스토리지노드 콘택의 측면 프로파일을 버티컬하게 제조할 수 있다. 따라서, 옥사이드막 식각 시 이온의 직진성과 충돌성을 증가시켜 높은 종횡비에 따른 식각정지 및 포지티브 슬로프를 방지할 수 있다.In addition, the present invention increases the resolution of the pattern while increasing the thickness of the photoresist film by applying the SILYAL technology, and performs the dry development process in the MICP type etching apparatus and vertically manufacture the side profile of the storage node contact through the output phase pulse control can do. Therefore, the etch stop and the positive slope due to the high aspect ratio can be prevented by increasing the linearity and collision of ions during the oxide film etching.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1c는 본 발명에 따른 캐패시터의 스토리지노드 콘택 형성방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming a storage node contact of a capacitor according to the present invention.
Claims (7)
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