KR100525084B1 - method for forming gate electrode in semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a gate electrode of a semiconductor device which prevents the generation of pores in the gate electrode and can maintain the flatness of the film interface constituting the gate electrode even when a high temperature thermal process is performed during the formation of the gate electrode. do. The present invention disclosed includes forming a gate oxide film on a semiconductor substrate; Depositing an amorphous silicon film on the gate oxide film; Depositing an amorphous transition metal silicide film on the amorphous silicon film; Crystallizing the amorphous transition metal silicide layer; Depositing a hard mask layer on the crystallized transition metal silicide layer; Patterning the films at least partially to form a gate electrode.

Description

Method for forming gate electrode in semiconductor device

The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, when forming a gate electrode including a titanium silicide layer, pores can be prevented from occurring and a semiconductor capable of realizing stable gate oxide film characteristics. A method for forming a gate electrode of an element.

In recent years, as the integration degree of a MOSFET device rapidly increases, corresponding line widths of gate electrodes are also rapidly reduced correspondingly. As a result, it is difficult to satisfy the conductivity of the highly integrated gate electrode with an electrode material such as conventional polysilicon or tungsten silicide / polysilicon. Accordingly, more and more alternative materials are being actively researched as next generation gate electrodes. Among them, representative materials include transition metal silicides such as titanium silicide, cobalt silicide and nickel silicide.

Here, a method for forming a gate electrode having a titanium silicide film will be described with reference to the accompanying drawings.

First, as shown in FIG. 1A, a gate oxide film 2 is grown on the semiconductor substrate 1, and a polysilicon film 3 doped with impurities is deposited on the gate oxide film 3. Then, a titanium silicide film 4 is formed on the doped polysilicon film 3 by physical vapor deposition. At this time, the titanium silicide film 4 is formed in an amorphous state.

Then, as shown in Figure 1b, the resultant is subjected to a rapid heat treatment process for a few seconds at a predetermined temperature, so that the titanium silicide film 4 in the amorphous state (C54) in the crystalline state (C54) having a low specific resistance ( Phase change to 5).

Thereafter, as shown in FIG. 1C, the hard mask film 6 is deposited on the titanium silicide film 5, the hard mask film 6, the crystallized titanium silicide film 5, the polysilicon film 3, and the like. The gate oxide film 2 is patterned to form a gate electrode. Then, in order to recover damage to the substrate caused by the etching of the gate electrode and subsequently minimize the damage of the substrate during ion implantation for the source drain, the resultant surface is reoxidized to form the reoxidation film 7.

However, the method of forming the gate electrode with the titanium silicide film has the following problems.

The titanium silicide film 4 formed in the amorphous state has a relatively coarse structure. When the titanium silicide film 4 is rapidly heat-treated and crystallized into the crystalline titanium silicide film 5, during the crystallization process, titanium and silicon, which are constituent elements, undergo rapid mass transfer (thermal diffusion) to form a relatively large atomic density phase. It progresses and the whole film shrinks. At this time, since the polysilicon film 3 under the titanium silicide film 4 is already crystallized, there is no change of state. Accordingly, while the titanium silicide shrinks in volume during the thermal process, while the polysilicon film is intact, the tensile stress generated in the titanium silicide film cannot be alleviated, and the concentration is concentrated inside the gate electrode, particularly at the interface between the polysilicon film and the titanium silicide film. , Pores are generated.

2 is a SEM photograph showing pores generated in the titanium silicide film. At this time, the photo is taken after the crystallization of the titanium silicide film, the predetermined thickness, it can be seen that a large number of pores in the titanium silicide film after crystallization.

3A and 3B are TEM and SEM photographs showing the cross section after the gate electrode is formed. According to the two photographs, pores 10 are generated at the interface between the polysilicon film 3 and the titanium silicide film 5. As a result, the side surface of the gate electrode is partially recessed by the pores 10. As such, when pores are generated and the side surface of the gate electrode is recessed, the effective line width of the gate electrode is reduced. As a result, the sheet resistance of the gate electrode is increased.

In addition, after completing the gate electrode as described above, a predetermined thermal process is performed to form a source, a drain region, and the like. At this time, if the thermal process is performed at 800 ° C. (FIG. 4A) and 850 ° C. (FIG. 4B) for about 60 minutes, when the breakdown voltage is applied to a certain degree, the gate oxide film is destroyed. On the other hand, if the thermal process is performed at 900 ° C. for 60 minutes (see FIG. 4C), the gate oxide film is immediately destroyed while the breakdown voltage is applied. As such, when the thermal process is performed at a high temperature (900 ° C.), the movement between materials becomes active, and the yield of the gate oxide film occurs quickly, and at the same time, the interface that was flat during the initial deposition becomes very rough. That is, when the thermal process is performed, the silicon of the polysilicon film and the titanium of the titanium silicide film mutually react with each other, and the reaction proceeds preferentially along the grain boundaries of the polysilicon film, resulting in uneven interfaces.

Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device which can prevent the generation of pores in the gate electrode when the gate electrode is formed.

Further, another object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of maintaining the flatness of the film interface constituting the gate electrode even when a high temperature thermal process is performed during the formation of the gate electrode.

In order to achieve the above object of the present invention, the present invention comprises the steps of forming a gate oxide film on a semiconductor substrate; Sequentially depositing a polysilicon film and an amorphous silicon film on the gate oxide film; Depositing an amorphous transition metal silicide film on the amorphous silicon film; Crystallizing the amorphous transition metal silicide layer; Depositing a hard mask layer on the crystallized transition metal silicide layer; Patterning the films at least partially to form a gate electrode.

According to the present invention, in forming a gate electrode including a transition metal silicide film, an amorphous silicon film is used as a conductor constituting the gate electrode. Accordingly, in the step of crystallizing the transition metal silicide film, the amorphous silicon film is simultaneously crystallized, so that the volume shrinkage occurs at a substantially similar ratio between the transition metal silicide film and the amorphous silicon film, and no porosity or the like occurs.

In addition, by using an amorphous silicon film having a random structure as the gate electrode conductor, when the titanium silicide film is crystallized with respect to the entire interfacial region, atoms are uniformly moved and reacted with each other to achieve interfacial planarization.

Further, an amorphous silicon film doped with impurities as a conductor of the gate electrode is deposited, and the amorphous silicon film is densified before the titanium silicide film is deposited. Accordingly, the amorphous silicon film is maintained in a stable amorphous state so that the subsequent reaction of the amorphous silicon film with the titanium silicide film is minimized during the crystallization process of the titanium silicide film. Accordingly, the stress difference does not occur, so that the generation of pores can be reduced, the mutual movement and reaction of atoms are prevented, and the interface planarization can be achieved.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6A through 6C are cross-sectional views of respective processes for describing a method of forming a gate electrode of a semiconductor device according to a first exemplary embodiment of the present invention.

First, as shown in FIG. 6A, a gate oxide film 12 is formed on the semiconductor substrate 11. Next, an amorphous silicon film 13 doped with impurities is formed on the gate oxide film 12. Then, a titanium silicide film 14 is deposited on the doped amorphous silicon film 13 by a physical vapor deposition method. At this time, the titanium silicide layer 14 is in an amorphous state during deposition, and instead of the titanium silicide layer 14, a transition metal silicide layer such as cobalt silicide or nickel silicide may be used.

Then, as shown in FIG. 6B, the resultant is heat-treated at a predetermined temperature to change the amorphous titanium silicide film 14 into a crystalline (C54) titanium silicide film 15 having a low specific resistance. At this time, the heat treatment process is a rapid heat treatment process for 10 to 30 seconds in an inert atmosphere and 750 to 850 ℃. In addition, it can be carried out by dividing into two steps, first, the first heat treatment for 10 to 30 seconds in an inert atmosphere and 650 to 750 ℃ to form a titanium silicide film of the C49 state having a high specific resistance of 60 to 70μΩ · cm Next, a second heat treatment is performed at 800 to 850 ° C. for 10 to 30 seconds to form a titanium silicide film 15 having a C54 state having a low resistivity of about 13 to 25 μΩ · cm. As another method, the first heat treatment in a furnace (funace) for 30 to 60 minutes at an inert atmosphere and 650 to 650 ℃, and the second heat treatment for 10 to 30 seconds at 800 to 850 ℃ to form a titanium silicide film It may be formed. Here, in the step of crystallizing the titanium silicide film 14, the amorphous silicon film 13 is also crystallized to become the polysilicon film 13a. In this case, since the amorphous silicon film 13 is crystallized in correspondence with the upper titanium silicide film 14, the volumetric shrinkage of the titanium silicide film 14 and the amorphous silicon film 13 similarly occurs. Accordingly, the generation of stress in the titanium silicide film 15 is reduced, so that no pores are generated. In addition, during the crystallization process, the amorphous silicon film 13 has a random structure and isotropy, so that the titanium and silicon react with each other uniformly during the thermal process, thereby making the interface planarized. That is, the polysilicon film mutually reacts only at the grain boundaries, but in the case of the amorphous silicon film, the grain boundaries do not exist, so that the mutual reaction occurs uniformly.

Then, a hard mask film 16 is formed on the titanium silicide film 15 by a known method.

Next, as shown in FIG. 6C, the hard mask film 16, the crystallized titanium silicide film 15, the polysilicon film 13, and the gate oxide film 12 are patterned to form a gate electrode. Then, in order to recover the damage of the substrate 11 caused by the etching of the gate electrode, and then to minimize the damage of the substrate 11 during ion implantation for the source drain, the resulting surface is recrystallized, reoxidized film (7) ).

7A and 7B are cross-sectional views of respective processes for describing the second embodiment of the present invention.

Referring to FIG. 7A, a gate oxide film 22 is formed on the semiconductor substrate 21. Next, a polysilicon film 23 is formed on the gate oxide film 22. Then, an amorphous silicon film 24 is formed on the polysilicon film 23 by a predetermined thickness.

Thereafter, as shown in FIG. 7B, a titanium silicide film is deposited on the amorphous silicon film 24, and then a heat treatment process is performed to crystallize the titanium silicide film. At this time, the titanium silicide film crystallized by the heat treatment process becomes a titanium silicide film 24 in a crystalline state, and the amorphous silicon film 24 is converted into a polysilicon film 23b. Here, although the polysilicon film 23b amorphous by the heat treatment process is crystallized similarly to the polysilicon film 23a below, the grain boundary is formed discontinuously, so that the movement between titanium and silicon can be effectively prevented. Therefore, the film interface is prevented from being rough. Subsequent processes are the same as in the first embodiment.

8A, 8B and 9 are diagrams for explaining a third embodiment according to the present invention.

First, as shown in FIG. 8A, a gate oxide film 32 is formed on the semiconductor substrate 31. Next, an amorphous silicon film 33 doped with impurities is deposited on the gate oxide film 32.

Then, in order to densify the amorphous silicon film 33, a rapid heat treatment process is performed at 600 to 700 ° C. in a nitrogen atmosphere for 10 to 30 seconds.

Then, as shown in FIG. 8B, the amorphous silicon film 33a is densified while maintaining the amorphous state, thereby becoming a relatively stable state. Accordingly, in the subsequent crystallization process of the titanium silicide film, the amorphous silicon film 33a does not react and suppresses stress and pores due to volume shrinkage. In addition, in the densification process, the nitrogen gas and the surface of the amorphous silicon film are reacted to form a nitride film 34 on the densified amorphous silicon film 33a. In this case, since the nitride film 34 is very thin, it does not affect the conductivity of the gate electrode and serves as a barrier film that prevents mutual atomic movement between the titanium silicide film and the amorphous silicon film.

In this case, as shown in FIG. 9, the same effect may be achieved even through the polysilicon film 330 between the gate oxide film 32 and the amorphous silicon film 33.

As described in detail above, according to the present invention, in forming a gate electrode including a transition metal silicide film, an amorphous silicon film is used as a conductor constituting the gate electrode. Accordingly, in the step of crystallizing the transition metal silicide film, the amorphous silicon film is simultaneously crystallized, so that the volume shrinkage occurs at a substantially similar ratio between the transition metal silicide film and the amorphous silicon film, and no porosity or the like occurs.

In addition, by using an amorphous silicon film having a random structure as a conductor of the gate electrode, when the titanium silicide film is crystallized, atoms are uniformly moved with each other to achieve interfacial planarization.

Further, an amorphous silicon film doped with impurities as a conductor of the gate electrode is deposited, and the amorphous silicon film is densified before the titanium silicide film is deposited. Accordingly, the amorphous silicon film is maintained in a stable amorphous state so that the amorphous silicon film does not react with the titanium silicide film during the subsequent crystallization process of the titanium silicide film. Accordingly, the stress difference does not occur, it is possible to reduce the occurrence of pores, to prevent the mutual movement and reaction, to achieve the interface planarization.

1A to 1C are cross-sectional views illustrating a gate electrode forming method according to the prior art.

2 is a SEM photograph showing a titanium silicide film after crystallization of the titanium silicide film according to the related art.

3A is a TEM photograph showing a cross section of a gate electrode formed according to the prior art.

Figure 3b is a SEM photograph showing a gate electrode formed according to the prior art.

4A to 4C are graphs illustrating a count at which yield occurs with temperature when a conventional gate electrode is formed.

5 is a graph showing a cumulative probability according to a breakdown time when forming a conventional gate electrode.

6A through 6C are cross-sectional views illustrating a method of forming a gate electrode in a semiconductor device according to a first embodiment of the present invention.

7A and 7B are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device in accordance with a second embodiment of the present invention.

8A, 8B, and 9 are cross-sectional views for forming a gate electrode of a semiconductor device according to the third embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

11,21,31- semiconductor substrate 12,22,32- gate oxide

13,24,33-Amorphous Silicon Film 13a, 23a, 23b, 330-Polysilicon Film

14- Titanium Silicide Film in Amorphous State

15,25- Crystallized Titanium Silicide Film

16- Hard Mask Film 17- Property Paint

23,330- Polysilicon Film 34- Nitride Film

Claims (10)

Forming a gate oxide film on the semiconductor substrate; Sequentially depositing a polysilicon film and an amorphous silicon film on the gate oxide film; Depositing an amorphous transition metal silicide film on the amorphous silicon film; Crystallizing the amorphous transition metal silicide layer; Depositing a hard mask layer on the crystallized transition metal silicide layer; Forming a gate electrode by partially patterning the films. The method of claim 1, wherein the crystallization step is a rapid heat treatment for 10 to 30 seconds in an inert gas atmosphere and 750 to 850 ℃. The method of claim 1, wherein the crystallization step, the first heat treatment for 10 to 30 seconds at 650 to 750 ℃, and the second heat treatment for 10 to 30 seconds at 800 to 850 ℃ A gate electrode forming method of a semiconductor device comprising a. The method of claim 1, wherein the crystallization step, the first heat treatment in the furnace (funace) for 30 to 60 minutes at 650 to 650 ℃, and the second heat treatment for 10 to 30 seconds at 800 to 850 ℃ Method of forming a gate electrode of a semiconductor device comprising the step of proceeding. The method of forming a gate electrode of a semiconductor device according to any one of claims 1 to 4, wherein the transition metal silicide film is any one of a titanium silicide film, a cobalt silicide film, and a nickel silicide film. The method of claim 5, wherein the transition metal silicide layer is formed by physical vapor deposition. delete Forming a gate oxide film on the semiconductor substrate; Depositing an amorphous silicon film on the gate oxide film; Densifying the amorphous silicon film; Depositing an amorphous transition metal silicide film on the amorphous silicon film; Crystallizing the amorphous transition metal silicide layer; Depositing a hard mask layer on the crystallized transition metal silicide layer; Forming a gate electrode by partially patterning the films. The method of claim 8, wherein the densifying the amorphous silicon film comprises performing a heat treatment process for 10 seconds to 30 seconds at a nitrogen atmosphere and 600 to 700 ° C. 10. The method of claim 8, wherein the densifying the amorphous silicon film comprises performing a heat treatment for 10 seconds to 30 minutes at a nitrogen atmosphere and at 500 to 550 ° C. 10.