KR100345063B1 - Method of manufacturing mosfet device - Google Patents

Abstract

The present invention relates to a method for manufacturing a MOSFET device capable of preventing the removal of a sacrificial gate due to a step caused by a field oxide film. The method of the present invention is, first, on a silicon substrate on which field oxide films are formed. A thermal oxide film is grown, and a polysilicon film is deposited on the thermal oxide film and the field oxide film. Thereafter, after the planarization of the polysilicon film, the polysilicon film and the thermal oxide film are etched to form a sacrificial gate. Then, reoxidation is performed to form a screen oxide film on the sidewall of the sacrificial gate and the surface of the exposed silicon substrate, and then a low concentration impurity region is formed in the exposed silicon substrate portion through primary ion implantation, and then After forming spacers on both sidewalls of the sacrificial gate including the mask pattern, successively, source / drain regions of a low doping drain structure are formed by forming a high concentration impurity region in a portion of the silicon substrate exposed through secondary ion implantation. Form. Next, after depositing the interlayer insulating film on the resultant, the interlayer insulating film and the mask pattern is etched to expose the sacrificial gate, and then the exposed sacrificial gate is removed to define a groove to form a gate. To form. Next, after forming a gate insulating film on the resultant, a metal film is deposited on the gate insulating film so that the groove is completely filled, and then the metal film is etched to form a metal gate in the groove.

Description

Manufacturing method of MOSFET device {METHOD OF MANUFACTURING MOSFET DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOSFET, and in particular, to planarizing a polysilicon film for a sacrificial gate, a method of manufacturing a MOSFET capable of preventing the removal of a sacrificial gate due to a step by a field oxide film. It is about.

As is well known, gates of MOSFET devices have typically been formed of polysilicon. This is because the polysilicon satisfies physical properties required as a gate such as high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and formation of a flat surface. In addition, in the practical application of the MOSFET, the polysilicon gate contains a dopant such as phosphorus (P), arsenic (As), and boron (B), thereby achieving low resistance.

However, as the degree of integration of the MOSFET increases, variable values such as the line width of the gate, the thickness of the gate insulating film, the junction depth, and the like are reduced, so that polysilicon has a limitation in implementing the low resistance required on the fine line width. Therefore, there is a need for the development of a gate of a new material that can replace the polysilicon.

For this purpose, the research and development of the polyside gate using the transition metal-silicide-based material has been actively conducted in the early stage, but even in the case of such polyside gates, there is a limit in implementing low resistance due to the presence of polysilicon. It became. That is, in the polyside gate, the effective thickness of the gate insulating layer due to the gate depletion effect, the boron penetration in the p ⁺ polysilicon gate, and the threshold voltage due to the dopant distribution fluctuation are increased. Problems such as change have occurred.

Therefore, in recent years, research and development on metal gates have been actively promoted. Since the metal gate does not use a dopant, it is possible to solve the problem occurring in the polyside gate, and also use a metal having a work function value located in the mid band-gap of silicon. Thus, it can be applied as a single gate that can be used simultaneously in the NMOS and PMOS regions. Here, as the metal whose work function value corresponds to the mid band-gap of silicon, tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), tantalum (Ta) and nitride And a tantalum (TaN) film.

On the other hand, when the metal gate is applied to the MOSFET device, problems such as patterning of the metal gate, that is, difficulty in etching, damage due to plasma during etching and ion implantation, and thermal damage due to subsequent processes, are encountered. There is a problem in that the device characteristics are deteriorated.

Therefore, in order to solve the above problems, an integration technique using a damascene process has been proposed. The damascene process is a technology of changing the sacrificial gate into a metal gate by forming a sacrificial gate made of polysilicon and then forming an interlayer insulating film, removing the sacrificial gate, depositing a metal film, and polishing the metal film. Since the gate can be formed without the etching process, it is possible to prevent the deterioration of characteristics due to the etching process, and in particular, there is an advantage that the existing MOSFET process can be used as it is.

Hereinafter, a method for preparing a mospat using a damascene process according to the prior art will be described with reference to FIGS. 1A to 1H.

First, as shown in FIG. 1A, a thermal oxide film 3 and a polysilicon film 4 are sequentially formed on the entire surface of the silicon substrate 1 on which the field oxide films 2 defining the element formation region are formed on a surface thereof. do.

Then, as shown in FIG. 1B, an oxide film or a nitride film for a hard mask is deposited on the polysilicon film 4, and then patterned, and then the lower portion thereof is patterned using the patterned mask pattern 5. The sacrificial gate 10 is formed by etching the polysilicon film 4 and the thermal oxide film 3.

Next, as shown in FIG. 1C, the silicon at the time of ion implantation for recovering the etch damage of the silicon substrate 1 generated at the time of the etching, and for the formation of subsequent source / drain regions. In order to protect the substrate 1 from damage, a gate re-oxidation is performed on the resultant, and as a result, a screen oxide film is formed on the sidewall of the sacrificial gate 10 and the surface of the silicon substrate 1. (11) is formed. Then, a low dose and energy ion implantation process is performed on the resultant to form the LDD region 12 in portions of the silicon substrate on both sides of the sacrificial gate 10.

Subsequently, as shown in FIG. 1D, in the state where the screen oxide film is removed, a nitride nitride film for the spacer is deposited on the entire surface of the resultant product, and the nitride nitride film for the spacer is etched on the entire surface of the sacrificial gate 10. Spacers 13 are formed on both side walls. The resultant is then implanted with high dose and energy ions to form source / drain regions 14 of LDD structure.

Next, as shown in FIG. 1E, an interlayer insulating film 15 is deposited on the resultant to a thickness sufficient to cover the sacrificial gate 10 including the mask pattern 5, and then the sacrificial gate ( The interlayer insulating film 15 is polished by a chemical mechanical polishing (CMP) process using 10) as a polishing inhibiting layer to expose the sacrificial gate 10 and to planarize its surface.

Subsequently, as shown in FIG. 1F, the sacrificial gate exposed as a result of the CMP process is removed to form a groove 16 defining a region where a metal gate is to be formed, and then as shown in FIG. 1G. After the gate insulating film 17 is formed along the surface of the resultant product, the gate metal film 18 is deposited to a sufficient thickness such that the groove is completely filled thereon.

Then, as shown in FIG. 1H, the gate metal film is polished by using the interlayer insulating film 15 as the polishing inhibiting layer, thereby finally completing the MOSFET having the metal gate 20.

However, the conventional MOSFET manufacturing method as described above has the following problems. First, FIGS. 2A and 2B are cross-sectional views illustrating a conventional problem, and FIG. 2A is a cross-sectional view of FIG. 1B viewed from the side, and FIG. 2B is a cross-sectional view of FIG. 1E viewed from the side.

In FIG. 2A, the polysilicon film 4 itself has a step due to the step caused by the field oxide film 2. However, when the subsequent process proceeds in this state, as shown in FIG. 2B, in the process of exposing the sacrificial gate 10, a portion where the interlayer insulating film 15 is not removed by the step may occur. Therefore, when the sacrificial gate is removed, a portion that remains without being removed may not be able to manufacture a normal MOSFET device.

In addition, in FIGS. 1C and 1D, an ion implantation process is performed to form a source / drain region of an LDD structure. In this process, a sacrificial gate, ie, polysilicon, is doped. The different types of dopants are ion implanted in the NMOS and the PMOS, and as a result, when the sacrificial gate is removed in FIG. 1F, different etching characteristics are exhibited in the NMOS and the PMOS. The setting of the condition is difficult.

Accordingly, the present invention has been made to solve the above problems, and by forming the sacrificial gate polysilicon film, the MOSFET element capable of preventing the removal of the polysilicon film caused by the step by the field oxide film can be prevented. To provide a method for the preparation, the purpose is.

1A to 1H are cross-sectional views for each process for explaining a method of manufacturing a MOSFET device using a damascene process according to the prior art.

Figure 2a and Figure 2b is a cross-sectional view for explaining the problem in the manufacturing method of the MOSFET using the damascene process according to the prior art.

3A to 3G are cross-sectional views of respective processes for explaining a method of manufacturing a MOSFET according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

1 silicon substrate 2 field oxide film

3: thermal oxide film 4: polysilicon film

5: mask pattern 10: sacrificial gate

11: screen oxide film 12: LDD region

13: spacer 14; Source / Drain Area

15: interlayer insulating film 16: groove

17 gate insulating film 18 metal film

20: metal gate

Method of manufacturing a MOSFET device of the present invention for achieving the above object comprises the steps of providing a silicon substrate formed with field oxide films; Growing a thermal oxide film on the silicon substrate and depositing a polysilicon film on the thermal oxide film and the field oxide film; Planarizing the surface of the polysilicon film; Forming a mask pattern on the polysilicon layer, and etching the polysilicon layer and the thermal oxide layer by an etching process using the mask pattern to form a sacrificial gate in an element formation region of the silicon substrate; Performing a reoxidation of the result to form a screen oxide on the sidewalls of the sacrificial gate and the surface of the exposed silicon substrate; Forming a low concentration impurity region in the portion of the silicon substrate exposed through the primary ion implantation; Forming spacers on both sidewalls of the sacrificial gate including the mask pattern; Forming a high concentration impurity region in the portion of the silicon substrate exposed through the secondary ion implantation, thereby forming a source / drain region of low doping drain structure; Depositing an interlayer dielectric layer on the resultant, and etching the interlayer dielectric layer and mask pattern to expose the sacrificial gate; Removing the exposed sacrificial gate to form a groove defining a region in which the gate is to be formed; Forming a gate insulating film on the resultant, and depositing a predetermined metal film on the gate insulating film to completely fill the grooves; And etching the metal film to form a metal gate in the groove.

According to the present invention, the planarization is performed after the deposition of the sacrificial gate polysilicon film, whereby the phenomenon in which the polysilicon film is not removed afterwards can be prevented, so that a MOSFET having a desired structure can be formed. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views of respective processes for explaining a method of manufacturing a MOSFET using a damascene process according to an exemplary embodiment of the present invention. 1A to 1H are denoted by the same reference numerals.

First, as shown in FIG. 3A, field oxide films 2 defining element formation regions are formed on the surface of the silicon substrate 1, and the thermal oxide film 3 is formed on the entire upper portion of the silicon substrate 1. After the growth, the polysilicon film 4 is deposited on the thermal oxide film 3 and the field oxide film 2 to a thickness of 2,000 to 4,000 kPa through an LPCVD process.

In this case, the polysilicon film 4 may be deposited in a doped state by introducing a gas containing a dopant into the chamber in an in-situ manner during the deposition thereof, and deposited in an undoped state. In this case, the dopant is doped through the ion implantation process after the deposition. As described above, the doping of the polysilicon film 4 is intended to suppress further doping at the sacrificial gate made of polysilicon during the ion implantation process for forming subsequent source / drain regions. This is to facilitate setting of the etching condition when the gate is removed.

On the other hand, the polysilicon film 4 itself has a step at the top of the field oxide film 2 due to the step by the field oxide film 2 at the time of vapor deposition thereof, and in this polysilicon film 4 As described above, the step of, causes a structurally fatal defect.

Therefore, in order to remove the step in the polysilicon film 4, as shown in Figure 3b, the polysilicon film 4 is planarized as a whole by performing a CMP process. In this case, etching for planarizing the polysilicon layer 4 may be performed by an etch back process instead of the CMP process.

Next, as illustrated in FIG. 3C, an oxide or nitride film for hard mask is deposited to a thickness of 800 to 1,000 Å on the planarized polysilicon film 4, and then patterned to form a mask pattern 5. By using the mask pattern 5 to etch the polysilicon film 4 and the thermal oxide film 3, a sacrificial gate may be formed in the element formation region of the silicon substrate 1 defined by the field oxide film 2. 10) form.

Then, in order to recover the etching damage of the silicon substrate 1 generated at the time of the etching and to protect the damage of the silicon substrate 1 at the time of ion implantation for the formation of subsequent source / drain regions, The gate reoxidation is performed on the resultant at a temperature of 650 to 850 ° C. to form a screen oxide film 11 to a thickness of 30 to 100 μm on the sidewall of the sacrificial gate 10 and the surface of the silicon substrate 1. In this case, in the reoxidation, a bird's beak is induced in the thermal oxide film 3 at the edge of the sacrificial gate 10, thereby minimizing the occurrence of gate overlap capacitance. Thereafter, relatively low dose and energy ion implantation is performed on the resultant to form a low concentration impurity region, that is, an LDD region 12, in portions of the silicon substrate on both sides of the sacrificial gate 10.

Subsequently, as shown in FIG. 3D, in a state in which the screen oxide film is removed, a spacer oxide film is deposited to a thickness of 900 to 1,200 상 에 on the entire surface of the resultant product, and then the entire surface is etched, followed by blanket etching. Spacers 13 are formed on both sidewalls of the sacrificial gate 10 having (5), and then ion implantation of relatively high dose and energy is formed to form high concentration impurity regions of the LDD structure. Source / drain regions 14 are formed.

Next, as shown in FIG. 3E, an interlayer insulating film 15 is deposited on the resultant to a thickness of 4,000 to 6,000 Å, and the sacrificial gate 10 is used as a polishing blocking layer. The pattern is polished by a CMP process to expose the sacrificial gate 10 and to planarize the surface of the interlayer insulating film 15. In this case, etching for planarizing the interlayer insulating layer 15 may be performed by an etch back process instead of the CMP process.

Next, as shown in FIG. 3F, the exposed sacrificial gate is removed through a wet or dry etching process to form a groove 16 defining a region where a metal gate is to be formed, and then the surface of the resultant product is removed. Therefore, after the gate insulating film 17 is formed, the gate metal film 18 is deposited to a sufficient thickness such that the groove 16 is completely buried thereon. Here, the gate insulating film 17 is an oxide film, a nitride oxide film, or a high dielectric constant film by a growth method or a vapor deposition method, and the gate metal film 18 is a tungsten (W) film by a PVD or CVD process. Tungsten nitride (WN) film, titanium (Ti) film, titanium nitride (TiN) film, molybdenum (Mo) film, tantalum (Ta) film, or tantalum nitride (TaN) film.

Then, as shown in FIG. 1G, the gate metal film is polished by using the interlayer insulating film 15 as a polishing inhibiting layer, thereby finally completing the MOSFET device having the metal gate 20. In this case, the etching for forming the metal gate 20 may be performed by an etch back process instead of the CMP process.

In the manufacturing method of the present invention as described above, since the step in the polysilicon film 4 caused by the field oxide film 2 is eliminated in advance, at the subsequent CMP process with respect to the interlayer insulating film 15, the poly The phenomenon in which the silicon film is not exposed can be eliminated, so that the problem caused by the partial residual of the polysilicon film can be solved, so that a MOSFET having a metal gate of a desired structure can be formed.

As described above, according to the present invention, the planarization of the polysilicon film for the sacrificial gate can be performed, whereby the CMP process and the sacrificial gate removing process for the interlayer insulating film can be normally performed in a subsequent process, and thus, the MOSFET having the desired structure. Can be formed, and in particular, the process reliability can be ensured, and thus it can be very advantageously applied to the production of highly integrated devices.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (13)

Providing a silicon substrate having field oxide films formed thereon; Growing a thermal oxide film on the silicon substrate and depositing a polysilicon film on the thermal oxide film and the field oxide film; Planarizing the surface of the polysilicon film; Forming a mask pattern on the polysilicon layer, and etching the polysilicon layer and the thermal oxide layer by an etching process using the mask pattern to form a sacrificial gate in an element formation region of the silicon substrate; Performing a reoxidation of the result to form a screen oxide on the sidewalls of the sacrificial gate and the surface of the exposed silicon substrate; Forming a low concentration impurity region in the portion of the silicon substrate exposed through the primary ion implantation; Forming spacers on both sidewalls of the sacrificial gate including the mask pattern; Forming a high concentration impurity region in the portion of the silicon substrate exposed through the secondary ion implantation, thereby forming a source / drain region of low doping drain structure; Depositing an interlayer dielectric layer on the resultant, and etching the interlayer dielectric layer and mask pattern to expose the sacrificial gate; Removing the exposed sacrificial gate to form a groove defining a region in which the gate is to be formed; Forming a gate insulating film on the resultant, and depositing a predetermined metal film on the gate insulating film to completely fill the grooves; And And etching the metal film to form a metal gate in the groove. 2. The method of claim 1, wherein the polysilicon film is deposited to a thickness of 2,000 to 4,000 kPa through an LPCVD process. The method of manufacturing a MOSFET device according to claim 1, wherein the polysilicon film is deposited in a doped state by introducing a gas containing a dopant during deposition. The method of claim 1, wherein the polysilicon film After the deposition in the undoped state, the manufacturing method of the MOSFET device characterized in that the doping a predetermined dopant by an ion implantation process. The method of claim 1, wherein the planarization of the polysilicon film A method for manufacturing a MOSFET device, characterized in that it is carried out by chemical mechanical polishing or etchback process. The method for manufacturing the MOSFET device according to claim 1, wherein the reoxidation is performed so that a screen oxide film having a thickness of 30 to 100 kPa is formed at 650 to 850 ° C. The method of claim 1, wherein forming a low concentration impurity region and forming a spacer, The method of claim 1, further comprising the step of removing the screen oxide film. The method of claim 1, wherein the forming of the spacers comprises: And a second step of depositing an oxide film to a thickness of 900 to 1,200 Å, and a second step of blanket etching the oxide film. The method of claim 1, wherein the interlayer insulating layer is deposited to a thickness of 4,000 to 6,000 GHz. The method of claim 1 or 9, wherein the etching of the interlayer insulating film A method for manufacturing a MOSFET device, which is performed by chemical mechanical polishing or etch back process. The method of claim 1, wherein the gate insulating film, A method for manufacturing a MOSFET device, characterized in that it is one selected from an oxide film, a nitride oxide film, or a high dielectric constant film by a growth method or a deposition method. The method of claim 1, wherein the metal film Tungsten (W) film, tungsten nitride (WN) film, titanium (Ti) film, titanium nitride (TiN) film, molybdenum (Mo) film, tantalum (Ta) film, or tantalum nitride (PVD) by CVD process TaN) film manufacturing method of the MOSFET device characterized in that the one selected from. The method of claim 1, wherein the etching of the metal layer is performed. A method for manufacturing a MOSFET device, which is performed by chemical mechanical polishing or etch back process.