KR100521446B1 - A semiconductor device with a pre-metal dielectric layer and method for manufacturing the layer - Google Patents
A semiconductor device with a pre-metal dielectric layer and method for manufacturing the layer Download PDFInfo
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- KR100521446B1 KR100521446B1 KR10-2003-0087187A KR20030087187A KR100521446B1 KR 100521446 B1 KR100521446 B1 KR 100521446B1 KR 20030087187 A KR20030087187 A KR 20030087187A KR 100521446 B1 KR100521446 B1 KR 100521446B1
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Abstract
본 발명은 반도체 소자의 금속전 유전체막(Pre-Metal Dielectric: PMD) 형성 공정에 있어서 다중 증착 속도로 PMD 산화막을 형성하는 방법에 관한 것이다. 본 발명에 따른 반도체 소자의 금속전 유전체막 형성 방법은, 게이트 패턴이 형성된 반도체 기판 상에 장벽용 절연막을 형성하는 단계; 및 상기 질화막 상에 다중 증착 속도로 금속전 유전체막(PMD)을 형성하는 단계를 포함하며, 여기서, 상기 다중 증착 속도로 증착되는 PMD는 적어도 3단계의 증착 속도로 형성되며, 상기 3단계의 증착 속도로 형성되는 PMD는 낮은 증착 속도로 형성되는 제1 PMD, 중간 증착 속도로 형성되는 제2 PMD, 및 높은 증착 속도로 형성되는 제3 PMD를 포함할 수 있다. 본 발명에 따르면, 다중 단계 방식의 증착 속도로 PMD를 증착함으로써 완전하게 갭을 충진(Gap fill)하고, 보이드로 인하여 발생되는 이웃한 콘택홀과의 단락 발생을 제거하여 전류의 누설을 최소화함으로써 소자의 수율 및 신뢰성을 향상시킬 수 있다.The present invention relates to a method of forming a PMD oxide film at multiple deposition rates in a pre-metal dielectric (PMD) forming process of a semiconductor device. A method of forming a dielectric metal film of a semiconductor device according to the present invention includes forming a barrier insulating film on a semiconductor substrate on which a gate pattern is formed; And forming a pre-metal dielectric film (PMD) on the nitride film at multiple deposition rates, wherein the PMD deposited at the multiple deposition rates is formed at at least three deposition rates, and the deposition of the three steps is performed. The PMD formed at a rate may include a first PMD formed at a low deposition rate, a second PMD formed at an intermediate deposition rate, and a third PMD formed at a high deposition rate. According to the present invention, the gap is completely filled by depositing PMD at a multi-step deposition rate, and a short circuit with neighboring contact holes caused by voids is minimized to minimize current leakage. Can improve the yield and reliability.
Description
본 발명은 반도체 소자의 금속전 유전체막에 관한 것으로, 보다 구체적으로, 반도체 소자의 금속전 유전체막(Pre-Metal Dielectric: PMD) 형성 공정에 있어서 다중 증착 속도로 PMD를 형성하는 방법 및 이 방법에 의해 형성된 PMD를 갖는 반도체 소자에 관한 것이다.The present invention relates to a metal dielectric film of a semiconductor device, and more particularly, to a method of forming a PMD at multiple deposition rates in a process of forming a pre-metal dielectric (PMD) of a semiconductor device. It relates to a semiconductor device having a PMD formed by.
반도체 소자의 제조 공정 중에서 금속전 유전체막(PMD)은 폴리실리콘과 상부 금속 배선의 층간 절연막으로 사용되고 있다. 이러한 PMD는 주로 PSG(Phosphors Silicate Glass) 또는 BPSG(Boron-Phosphors Silicate Glass)가 사용되고 있으며, PMD 증착 공정 진행에 의해 발생된 불순물인 나트륨(Na+) 원자의 포획 및 이동을 저지하기 위해서, 상기 PMD 증착 시에 인(Phosphors)을 불순물 형태로 첨가하며, 붕소(Boron)는 재흐름(Reflow) 특성을 향상시키기 위하여 불순물 형태로 첨가된다.In the process of manufacturing a semiconductor device, a metal dielectric film (PMD) is used as an interlayer insulating film of polysilicon and an upper metal wiring. The PMD is mainly composed of PSG (Phosphors Silicate Glass) or BPSG (Boron-Phosphors Silicate Glass), and in order to prevent the trapping and movement of sodium (Na +) atoms, which are impurities generated by the PMD deposition process, the PMD deposition Phosphors are added in the form of impurities, and boron is added in the form of impurities to improve reflow properties.
도 1은 종래의 기술에 따른 금속전 유전체막 형성 방법으로 제조되는 반도체 소자의 단면도로서, 기존의 공정을 진행하여 금속전 유전체막이 형성된 반도체 소자를 도시하고 있다.1 is a cross-sectional view of a semiconductor device manufactured by a method of forming a dielectric metal film according to the related art, and illustrates a semiconductor device in which a metal dielectric film is formed by a conventional process.
도 1을 참조하면, N-MOS(11a) 또는 P-MOS(11b) 상에 드레인/소스(17, 19) 및 게이트(15)가 형성된 기판 상에 질화막(27)을 형성하며, 이후, 상부 금속 배선의 층간 절연막인 PMD(29)를 일정 비율의 증착 속도로 증착하게 된다. 이후, 후속 공정으로서, 콘택 패턴(Contact pattern) 실시한 후, 콘택 식각(Contact etch) 실시하고, 이러한 콘택 식각 부위에 대해 클리닝을 실시하고, 최종적으로 콘택 장벽 금속 및 텅스텐-플러그 증착을 실시함으로써, 반도체 소자의 PMD 제조를 완료하게 된다.Referring to FIG. 1, the nitride film 27 is formed on a substrate on which the drain / source 17 and 19 and the gate 15 are formed on the N-MOS 11a or the P-MOS 11b. PMD 29, which is an interlayer insulating film of a metal wiring, is deposited at a rate of deposition. Subsequently, as a subsequent step, after performing a contact pattern, a contact etch, a contact etched site, a cleaning, and finally a contact barrier metal and tungsten-plug deposition are performed. The PMD manufacturing of the device is completed.
그러나 반도체 소자의 고집적화로 인한 게이트 전극의 간격이 점점 좁아짐에 따라서 갭 충진(Gap fill)에서의 보이드(void) 문제를 완전히 제거할 수 없었다. 이러한 보이드가 형성된 상태에서 후속적인 PMD 식각이 이루어질 경우, 이웃한 콘택홀(Contact Hole)과 콘택홀 사이에 식각에 의한 빈 공간이 생기고, 후속 공정인 장벽 금속(Barrier metal) 및 텅스텐-플러그 증착(W-plug deposition) 시에 상기 식각된 빈 공간에 금속 성분이 침투되어 이웃한 콘택홀과 콘택홀 사이에 단락(Short)이 발생되어 전류의 누설(Leakage)을 유발함으로써 반도체 소자의 신뢰성에 악영향을 끼치게 된다는 문제점이 있다.However, as the gap between the gate electrodes due to the higher integration of semiconductor devices becomes narrower, the void problem in gap fill cannot be completely eliminated. When subsequent PMD etching is performed while the voids are formed, an empty space is formed between the adjacent contact hole and the contact hole, and a subsequent process of barrier metal and tungsten-plug deposition is performed. During W-plug deposition, a metal component penetrates into the etched empty space, causing a short circuit between adjacent contact holes and the contact holes, causing leakage of current, thereby adversely affecting the reliability of the semiconductor device. There is a problem that causes.
도 2는 종래의 기술에 따라 PMD를 형성할 경우에 단락을 유발하여 불량 셀을 도시하기 위한 사진으로서, BPSG막의 빈 공간에 금속 성분이 확산(diffusion)되어 도면부호 A와 같이 콘택홀 사이의 단락이 발생되어 불량(fail) 셀이 발생되는 것을 도시하고 있다.FIG. 2 is a photograph showing a defective cell by causing a short circuit when forming a PMD according to the related art, and a metal component is diffused into an empty space of a BPSG film to short-circuit between contact holes as indicated by reference numeral A. FIG. Is generated and a fail cell is generated.
상기 문제점을 해결하기 위한 본 발명의 목적은 기존의 일괄적 증착 속도로 증착하는 방식이 아닌 다중 단계 방식의 증착 속도를 도입함으로써 완전한 갭 충진을 이룰 수 있는 반도체 소자의 PMD 제조 방법을 제공하기 위한 것이다.An object of the present invention for solving the above problems is to provide a method of manufacturing a PMD of a semiconductor device that can achieve a full gap filling by introducing a multi-step deposition rate rather than a conventional deposition rate at a batch deposition rate. .
또한, 본 발명의 목적은 보이드로 인하여 발생되는 이웃한 콘택홀과의 단락 발생을 제거하여 전류의 누설을 최소화할 수 있는 반도체 소자의 PMD 제조 방법을 제공하기 위한 것이다.It is also an object of the present invention to provide a method of manufacturing a PMD of a semiconductor device capable of minimizing leakage of current by eliminating short circuits with neighboring contact holes caused by voids.
상기 목적을 달성하기 위한 수단으로서, 본 발명에 따른 반도체 소자의 PMD 제조 방법은,As a means for achieving the above object, the PMD manufacturing method of a semiconductor device according to the present invention,
게이트 패턴이 형성된 반도체 기판 상에 장벽용 절연막을 형성하는 단계; 및Forming a barrier insulating film on the semiconductor substrate on which the gate pattern is formed; And
상기 장벽용 절연막 상에 다중 증착 속도로 금속전 유전체막(Pre-Metal Dielectric: PMD)을 형성하는 단계Forming a pre-metal dielectric film (PMD) at multiple deposition rates on the barrier insulating film;
를 포함한다.It includes.
여기서, 상기 PMD 전면을 화학적 기계 연마(CMP) 방식으로 평탄화하는 단계를 추가로 포함할 수 있다.Here, the method may further include planarizing the entire surface of the PMD by chemical mechanical polishing (CMP).
여기서, 상기 장벽용 절연막은 SiO2, Si3N4 또는 SiON일 수 있다.Here, the barrier insulating film may be SiO 2 , Si 3 N 4 or SiON.
여기서, 상기 PMD는 BPSG(Boro-Phospho Silicate Glass), USG(Undoped Silicate Glass), PSG(Phospho-Silicate Glass), BSG(Boro-Silicate Glass) 및 FSG(Fluorine-doped Silicon Oxide)로 이루어지는 일군으로부터 선택되는 것이 바람직하다.The PMD is selected from the group consisting of BPSG (Boro-Phospho Silicate Glass), USG (Undoped Silicate Glass), PSG (Phospho-Silicate Glass), BSG (Boro-Silicate Glass), and Fluorine-doped Silicon Oxide (FSG). It is desirable to be.
여기서, 상기 다중 증착 속도로 증착되는 PMD는 적어도 3단계의 증착 속도로 형성되는 것을 특징으로 하며, 상기 3단계의 증착 속도로 형성되는 PMD는, 낮은 증착 속도로 형성되는 제1 PMD, 중간 증착 속도로 형성되는 제2 PMD, 및 높은 증착 속도로 형성되는 제3 PMD를 포함할 수 있다.Here, the PMD deposited at the multiple deposition rate is formed at at least three deposition rates, wherein the PMD formed at the deposition rate of the three steps, the first PMD formed at a lower deposition rate, the intermediate deposition rate And a third PMD formed at a high deposition rate.
여기서, 상기 낮은 증착 속도에서는 붕소(Boron) 농도를 크게 하고, 상기 중간 증착 속도에서는 중간 농도로 하며, 상기 높은 증착 속도에서는 인(P) 농도를 크게 하는 것이 바람직하다.Here, it is preferable to increase the boron concentration at the low deposition rate, to the intermediate concentration at the intermediate deposition rate, and to increase the phosphorus (P) concentration at the high deposition rate.
한편, 상기 목적을 달성하기 위한 수단으로서, 본 발명에 따른 다중 증착 속도로 형성된 PMD를 구비한 반도체 소자는,On the other hand, as a means for achieving the above object, a semiconductor device having a PMD formed at multiple deposition rates according to the present invention,
반도체 기판 상에 형성된 게이트 패턴;A gate pattern formed on the semiconductor substrate;
상기 게이트 패턴 상에 형성되는 장벽용 절연막;A barrier insulating film formed on the gate pattern;
상기 장벽용 절연막 상에 다중 증착 속도로 형성되어 금속 배선의 층간 절연막으로 사용되는 복수의 금속전 유전체막(PMD); 및A plurality of metal dielectric films (PMDs) formed on the barrier insulating film at multiple deposition rates and used as interlayer insulating films of metal lines; And
상기 복수의 PMD를 식각하여 형성된 콘택과 연결되는 소스 및 드레인Source and drain connected to the contact formed by etching the plurality of PMDs
을 포함한다.It includes.
본 발명에 따르면, 기존의 한 단계로 일정 비율의 증착 속도로 산화막을 형성하지 않고, 적어도 한 번 이상의 여러 비율의 증착 속도로 산화막을 형성함으로써, 즉, 다중 증착 속도로 PMD 산화막을 형성함으로써, 완전하게 갭을 충진하고, 보이드로 인하여 발생되는 이웃한 콘택홀과의 단락 발생을 제거하여 전류의 누설을 최소화함으로써 소자의 수율 및 신뢰성을 향상시킬 수 있다.According to the present invention, by forming an oxide film at a deposition rate of at least one or more times, i.e., forming a PMD oxide film at a multiple deposition rate, without forming an oxide film at a certain rate of deposition rate in one conventional step, By filling the gaps and eliminating short circuits with neighboring contact holes caused by voids, leakage of current can be minimized to improve device yield and reliability.
이하, 첨부된 도면을 참조하여, 본 발명의 실시예에 따른 반도체 소자의 금속전 유전체막 형성 방법을 상세히 설명한다.Hereinafter, a method of forming a dielectric metal film of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 다중 증착 속도로 PMD를 제조하는 반도체 소자의 단면도이다.3 is a cross-sectional view of a semiconductor device fabricating a PMD at multiple deposition rates in accordance with the present invention.
전술한 바와 같이, 기존의 단일 단계의 일정 비율의 증착 속도로 산화막을 형성할 경우, 게이트 전극의 간격이 점점 좁아짐에 따라서 갭 충진에서의 보이드 문제를 완전히 제거할 수 없었으나, 본 발명은 기존의 단일 단계의 일정 비율의 증착 속도로 PMD를 형성하지 아니하고, 3단계, 즉, 낮은 증착 속도로 제1 PMD(51)를 형성하고, 중간 증착 속도로 제2 PMD(53)를 형성하며, 높은 증착 속도로 제3 PMD(55)를 증착하는 방법을 이용함으로써, 기존의 보이드 문제를 해결하여 이웃한 콘택홀과 콘택홀 사이에 터널이 형성되는 것을 방지하게 된다. 물론, 3단계 이상의 증착 속도로 PMD를 형성할 수도 있다.As described above, when the oxide film is formed at a predetermined rate of deposition in a single step, the void problem in gap filling cannot be completely eliminated as the gap between the gate electrodes becomes narrower. Rather than forming a PMD at a certain rate of deposition rate in a single step, forming a first PMD 51 at three steps, ie, a low deposition rate, forming a second PMD 53 at an intermediate deposition rate, and high deposition By using the method of depositing the third PMD 55 at a speed, the existing void problem is solved to prevent the formation of a tunnel between the adjacent contact hole and the contact hole. Of course, it is also possible to form the PMD at three or more deposition rates.
보다 구체적으로, 도 3을 참조하면, 본 발명에 따른 반도체 소자의 PMD 제조 방법은, 게이트 패턴(35)이 형성된 반도체 기판 상에 장벽용 절연막(47)을 형성한 후, 상기 장벽용 절연막(47) 상에 다중 증착 속도로 제1, 제2 및 제3 PMD(51, 53, 55)를 형성하게 된다. 이후, 상기 제3 PMD(55) 전면을 화학적 기계 연마(CMP) 방식으로 평탄화하게 된다.More specifically, referring to FIG. 3, in the method of manufacturing a PMD of the semiconductor device according to the present invention, after the barrier insulating film 47 is formed on the semiconductor substrate on which the gate pattern 35 is formed, the barrier insulating film 47 ) To form first, second and third PMDs 51, 53, 55 at multiple deposition rates. Thereafter, the entire surface of the third PMD 55 is planarized by chemical mechanical polishing (CMP).
여기서, 상기 장벽용 절연막(47)은 SiO2, Si3N4 또는 SiON일 수 있다.The barrier insulating layer 47 may be SiO 2 , Si 3 N 4, or SiON.
또한, 상기 제1, 제2 및 제3 PMD(51, 53, 55)는 붕소(Boron), 인(Phosphorus) 등이 포함된 모든 PMD 증착 시에 모두 적용할 수 있으며, 예를 들어, BPSG(Boro-Phospho Silicate Glass), USG(Undoped Silicate Glass), PSG(Phospho-Silicate Glass), BSG(Boro-Silicate Glass) 및 FSG(Fluorine-doped Silicon Oxide)로 이루어지는 일군으로부터 선택될 수 있다.In addition, the first, second and third PMDs 51, 53, and 55 may be applied to all PMD depositions including boron, phosphorus, and the like. For example, BPSG ( It may be selected from the group consisting of Boro-Phospho Silicate Glass (USG), Undoped Silicate Glass (USG), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), and Fluorine-doped Silicon Oxide (FSG).
상기 다중 증착 속도로 증착되는 PMD는 적어도 3단계의 증착 속도로 형성되며, 상기 3단계의 증착 속도로 형성되는 PMD는, 낮은 증착 속도로 형성되는 제1 PMD(51), 중간 증착 속도로 형성되는 제2 PMD(53), 및 높은 증착 속도로 형성되는 제3 PMD(55)를 포함할 수 있다. 예를 들어, 상기 낮은 증착 속도에서는 붕소(Boron) 농도를 크게 하고, 상기 중간 증착 속도에서는 중간 농도로 하며, 상기 높은 증착 속도에서는 인(P) 농도를 크게 함으로써, gathering 효과를 증가시킬 수 있다. 여기서, 미설명 도면부호 31a 및 31b는 N-MOS 또는 P-MOS 트랜지스터 영역을 나타내며, 도면부호 33은 절연층을 나타낸다. 또한, 도면부호 37은 LDD 영역을 나타내고, 도면부호 39는 소스 또는 드레인이 형성되는 영역을 나타내며, 도면부호 41은 소자 분리용 트렌치 상에 충진되는 절연재를 나타내고, 도면부호 43은 트렌치 내부의 라이너 산화막을 나타낸다. 또한, 미설명 도면부호 45는 게이트(35) 측면에 형성되는 스페이서용 질화막을 나타낸다. 상기 미설명 도면부호들은 본 발명에 따른 PMD 제조와 직접적인 관련이 없으므로 상세한 설명은 생략하기로 한다.The PMD deposited at the multiple deposition rate is formed at the deposition rate of at least three stages, and the PMD formed at the deposition rate of the three stages is formed of the first PMD 51 formed at a low deposition rate and the intermediate deposition rate. A second PMD 53 and a third PMD 55 formed at a high deposition rate may be included. For example, by increasing the boron concentration at the low deposition rate, the medium concentration at the intermediate deposition rate, and the phosphorus (P) concentration at the high deposition rate, the gathering effect may be increased. Here, reference numerals 31a and 31b denote regions of N-MOS or P-MOS transistors, and reference numeral 33 denotes an insulating layer. Further, reference numeral 37 denotes an LDD region, reference numeral 39 denotes a region where a source or a drain is formed, reference numeral 41 denotes an insulating material filled on the isolation trench, and reference numeral 43 denotes a liner oxide film inside the trench. Indicates. Further, reference numeral 45 denotes a nitride film for a spacer formed on the side of the gate 35. Since the non-described reference numerals are not directly related to the production of PMD according to the present invention, the detailed description will be omitted.
한편, 본 발명에 따른 다중 증착 속도로 형성된 금속전 유전체막을 구비한 반도체 소자는, 반도체 기판 상에 형성된 게이트 패턴(35), 상기 게이트 패턴(35) 상에 형성되는 장벽용 절연막(47), 상기 장벽용 절연막(47) 상에 다중 증착 속도로 형성되어 금속 배선의 층간 절연막으로 사용되는 복수의 금속전 유전체막(51, 53, 55), 및 상기 복수의 PMD를 식각하여 형성된 콘택과 연결되는 소스 및 드레인을 포함할 수 있다.On the other hand, the semiconductor device having a metal dielectric film formed at a multiple deposition rate according to the present invention, the gate pattern 35 formed on the semiconductor substrate, the barrier insulating film 47 formed on the gate pattern 35, the A source formed on the barrier insulating film 47 at a multiple deposition rate and connected to a plurality of metal dielectric films 51, 53, 55 used as an interlayer insulating film of a metal wiring, and a contact formed by etching the plurality of PMDs. And a drain.
도 4는 본 발명에 따른 금속전 유전체막 제조 이후 후속 콘택홀 형성 공정을 실시한 반도체 소자의 단면도로서, 전술한 3단계의 PMD 증착 공정의 후속 공정으로서, 콘택 패턴을 형성하고, 이후, 콘택을 식각하고, 이후 콘택 장벽 금속(59)과 텅스텐-플러그(57)를 증착한 것을 나타내고 있다. 이와 같이 콘택홀에 전기 배선을 형성하기 위한 콘택 장벽 금속(59) 증착 및 텅스텐-플러그(57) 증착 실시에 따른 SRAM 영역과 같은 이웃한 콘택홀과 콘택홀 사이에 터널이 발생하지 않게 된다.FIG. 4 is a cross-sectional view of a semiconductor device in which a subsequent contact hole forming process is performed after fabrication of a dielectric metal film according to the present invention. As a subsequent step of the above-described three-step PMD deposition process, a contact pattern is formed and then a contact is etched. Next, the contact barrier metal 59 and the tungsten plug 57 are deposited. As such, a tunnel does not occur between the contact hole and the neighboring contact hole such as the SRAM region according to the deposition of the contact barrier metal 59 and the tungsten-plug 57 deposition for forming the electrical wiring in the contact hole.
위에서 발명을 설명하였지만, 이러한 실시예는 이 발명을 제한하려는 것이 아니라 예시하려는 것이다. 이 발명이 속하는 분야의 숙련자에게는 이 발명의 기술 사항을 벗어남이 없어 위 실시예에 대한 다양한 변화나 변경 또는 조절이 가능함이 자명할 것이다. 그러므로 본 발명의 보호 범위는 첨부된 청구 범위에 의해서만 한정될 것이며, 위와 같은 변화예나 변경예 또는 조절예를 모두 포함하는 것으로 해석되어야 할 것이다.While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments are possible without departing from the technical details of the present invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.
본 발명에 따르면, 다중 단계 방식의 증착 속도로 PMD를 증착함으로써 완전하게 갭을 충진하고, 보이드로 인하여 발생되는 이웃한 콘택홀과의 단락 발생을 제거하여 전류의 누설을 최소화함으로써 소자의 수율 및 신뢰성을 향상시킬 수 있다.According to the present invention, the gap is completely filled by depositing PMD at a multi-step deposition rate, and the short circuit of neighboring contact holes caused by voids is minimized to minimize leakage of current, thereby yielding and reliability of the device. Can improve.
도 1은 종래의 기술에 따른 금속전 유전체 산화막 형성 방법으로 제조되는 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device manufactured by a method of forming a dielectric metal oxide film according to the related art.
도 2는 종래의 기술에 따라 금속전 유전체 산화막을 형성할 경우에 단락을 유발하여 불량 셀을 도시하기 위한 사진이다.FIG. 2 is a photograph for illustrating a defective cell by causing a short circuit when forming a dielectric metal oxide film according to the related art.
도 3은 본 발명에 따른 다중 증착 속도로 금속전 유전체막을 제조하는 반도체 소자의 단면도이다.3 is a cross-sectional view of a semiconductor device for fabricating a pre-metal dielectric film at multiple deposition rates in accordance with the present invention.
도 4는 본 발명에 따른 금속전 유전체막 제조 이후 후속 콘택홀 형성 공정을 실시한 반도체 소자의 단면도이다.4 is a cross-sectional view of a semiconductor device in which a subsequent contact hole forming process is performed after fabrication of a dielectric metal film according to the present invention.
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