KR100515054B1 - CMOS semiconductor device and method of the same - Google Patents

Abstract

A CMOS semiconductor device and a method of forming the same are provided. This device comprises a semiconductor substrate having an N-MOS region and a P-MOS region. An NMOS gate pattern is disposed on the semiconductor substrate in the NMOS region, and an NMOS gate insulating film is interposed between the NMOS gate pattern and the semiconductor substrate. A PMOS gate pattern is disposed on the semiconductor substrate in the PMOS region, and a PMOS gate insulating film is interposed between the PMOS gate pattern and the semiconductor substrate. At this time, the lower surface of the NMOS gate insulating film is made of a silicon oxynitride film, the lower surface of the PMOS gate insulating film is made of a silicon oxide film, and the upper surface of the PMOS gate insulating film is made of a silicon oxynitride film.

Description

CMOS semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a CMOS semiconductor device and a method for forming the same.

Among the semiconductor devices, the transistor includes a gate electrode formed on the semiconductor substrate, a gate oxide interposed between the gate electrode and the semiconductor substrate, and a source / drain region formed on the semiconductor substrate on both sides of the gate electrode. The transistors may be classified into an NMOS transistor and a PMOS transistor according to the type of the main carrier. The NMOS transistor uses electrons as the main carrier, and the PMOS transistor uses holes as the main carrier. CMOS semiconductor devices have both NMOS and PMOS transistors.

In accordance with the trend toward higher integration of semiconductor devices, the size of the transistors is gradually reduced to decrease the operation speed of the transistors. For this reason, researches on transistors capable of operating at high speed are being actively conducted. In particular, in the case of the PMOS transistor, research on a surface channel that can improve the operating speed compared to the buried channel is being conducted, and in the case of the NMOS transistor, between the semiconductor substrate and the gate oxide film Research is underway to reduce the traps. Traps are causing the electrons mobility to degrade. Accordingly, researches are being conducted to improve the operation speed of the NMOS and PMOS transistors at the same time.

An object of the present invention is to provide a CMOS semiconductor device that can improve the operating speed characteristics of the NMOS transistor and the operating speed characteristics of the PMOS transistor.

Another object of the present invention is to provide a method of forming a CMOS semiconductor device capable of improving an operating speed characteristic of an NMOS transistor and an operating speed characteristic of a PMOS transistor.

To provide a CMOS semiconductor device for solving the above technical problem. This device includes a semiconductor substrate having an NMOS region and a PMOS region. An NMOS gate pattern is disposed on the semiconductor substrate in the NMOS region, and an NMOS gate insulating layer is interposed between the NMOS gate pattern and the semiconductor substrate. A PMOS gate pattern is disposed on the semiconductor substrate in the PMOS region, and a PMOS gate insulating layer is interposed between the PMOS gate pattern and the semiconductor substrate. In this case, a lower surface of the NMOS gate insulating film is formed of a silicon oxynitride film, a lower surface of the PMOS gate insulating film is made of a silicon oxide film, and an upper surface of the PMOS gate insulating film is made of a silicon oxynitride film.

Specifically, the NMOS gate pattern includes a stacked n-type doped polysilicon layer and an NMOS metal silicide layer, and the PMOS gate pattern includes a stacked p-type doped polysilicon layer and PMOS. It is preferable to consist of a metal silicide film. The NMOS gate insulating film may be composed of stacked first and second silicon oxynitride films, and the PMOS gate insulating film may be formed of stacked silicon oxide films and a second silicon oxynitride film. The silicon oxide film is preferably a thermal oxide film.

Provided are a method for forming a CMOS semiconductor device for solving the above-mentioned other technical problem. The method includes forming a first silicon oxynitride film on the entire surface of the semiconductor substrate having the NMOS region and the PMOS region. The first silicon oxynitride film of the PMOS region is selectively removed to expose the semiconductor substrate of the PMOS region. A silicon oxide film having a smaller thickness in the NMOS region than the thickness on the exposed semiconductor substrate is formed on the entire surface of the semiconductor substrate. The silicon oxide film is nitrided to form a second silicon oxynitride film, and the silicon oxide film remains in the PMOS region.

Specifically, the silicon oxide film is preferably formed of a thermal oxide film. Preferably, the first and second silicon oxynitride layers stacked in the NMOS region are NMOS gate insulating layers, and the remaining silicon oxide and second silicon oxynitride layers stacked in the PMOS region are PMOS gate insulating layers. Do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

1 is a cross-sectional view illustrating a CMOS semiconductor device according to a preferred embodiment of the present invention. In the drawings, reference numerals "a" and "b" denote NMOS regions and PMOS regions, respectively.

Referring to FIG. 1, an isolation layer 10 is disposed in a predetermined region of a semiconductor substrate 9 having an NMOS region a and a PMOS region b. The device isolation layer 10 defines an NMOS active region within the NMOS region a, and defines an PMOS active region within the PMOS region b. The NMOS active region is doped with p-type impurities and the PMOS active region is doped with n-type impurities.

An NMOS gate pattern 25 is disposed on the NMOS active region, and an NMOS gate insulating layer 14 is interposed between the NMOS gate pattern 25 and the NMOS active region. The NMOS gate pattern 25 may be formed of a stacked NMOS gate electrode 21a and an NMOS metal silicide layer 23a. The NMOS gate electrode 21a is preferably made of an n-type doped polysilicon film. The n-type doped polysilicon layer may be doped with phosphorus (P) or ashenic (As) impurities. The NMOS gate insulating film 14 is preferably made of a silicon oxynitride film. More specifically, the NMOS gate insulating layer 14 may be formed of stacked first and second silicon oxynitride layers 11 and 13a. That is, the lower surface of the NMOS gate insulating layer 14 in contact with the NMOS active region is formed of the first silicon oxynitride layer 11. The first silicon oxynitride layer 11 may be formed of a thermal oxynitride layer. Alternatively, it may be made of a plasma oxynitride film. The second silicon oxynitride layer 13a may be formed of a plasma oxynitride layer. An n-type impurity diffusion layer 28 is disposed in the NMOS active region on both sides of the NMOS gate pattern 25. The n-type impurity diffusion layer 28 corresponds to a source / drain region of the NMOS transistor. The NMOS gate pattern 25, the NMOS gate insulating layer 14, and the n-type impurity diffusion layer 28 are included in the NMOS transistor.

The PMOS gate pattern 26 is disposed on the PMOS active region. A PMOS gate insulating layer 15 is interposed between the PMOS gate pattern 26 and the PMOS active region. The PMOS gate pattern 26 may be formed of a stacked PMOS gate electrode 22a and a PMOS metal silicide layer 23b. The PMOS gate electrode 22a is preferably made of a p-type doped polysilicon film. The p-type doped polysilicon layer may be doped with impurities such as boron (B). The PMOS gate insulating film 15 may be formed of a silicon oxide film 13 ′ and a second silicon oxynitride film 13a that are sequentially stacked. That is, a lower surface of the PMOS gate insulating film 15 in contact with the PMOS active region is formed of the silicon oxide film 13 ′, and an upper surface of the PMOS gate insulating film 15 is the second silicon oxide. It is preferable that it consists of the nitride film 13a. The silicon oxide film 13 'is preferably made of a thermal oxide film. A p-type impurity diffusion layer 29 is disposed in the PMOS active region on both sides of the PMOS gate pattern 26. The p-type impurity diffusion layer 29 corresponds to a source / drain region of the PMOS transistor. The PMOS gate pattern 26, the PMOS gate insulating layer 15, and the p-type impurity diffusion layer 29 are included in the PMOS transistor.

The NMOS and PMOS metal silicide layers 23a and 23b may be formed of a tungsten silicide layer, a cobalt silicide layer, a titanium silicide layer, or a nickel silicide layer.

In the above-described NMOS transistor, since the NMOS gate insulating layer 14 is formed of the silicon oxynitride layers 11 and 13a, the flow of electrons between the NMOS active region and the NMOS gate insulating layer 14 is reduced. Interrupting traps are reduced. As a result, it is possible to minimize the phenomenon that electrons, which are main carriers of the NMOS transistor, are degraded by the traps. That is, the operating speed of the NMOS transistor can be improved.

In contrast, the PMOS transistor includes the silicon oxide layer 13 ′ and the second silicon oxynitride layer 13a in which the PMOS gate insulating layer 14 is stacked. The second silicon oxynitride layer 13a prevents the borons in the p-type doped polysilicon layer from diffusing into the PMOS active region. Accordingly, the p-type doped polysilicon film may be used as the PMOS gate electrode 22a. As a result, the PMOS transistor may have a surface channel to improve operating speed characteristics. In addition, the silicon oxide film 13 ′ contacts the PMOS active region so that the silicon oxide film 13 ′ does not disturb the flow of holes, which are main carriers of the PMOS transistor. If the silicon oxynitride film is in contact with the PMOS active region, the traps that hinder the flow of electrons are reduced, while the traps that hinder the flow of holes are increased, thereby decreasing the mobility of the holes. As a result, due to the PMOS gate insulating film 15, the PMOS transistor has a surface channel without a decrease in the flow of holes, thereby improving the operation speed characteristic.

An improved operating speed of the CMOS semiconductor device according to the present invention will be described with reference to FIGS. 2A and 2B.

Figure 2a is a schematic graph showing the mobility of the electrons of the NMOS transistor of the CMOS device according to the present invention, Figure 2b is a schematic graph showing the mobility of holes of the PMOS transistor of the CMOS device according to the present invention to be. In FIG. 2A, the x axis represents the gate voltage applied to the NMOS gate pattern, and the y axis represents the mobility of electrons. In FIG. 2B, the x axis represents the absolute value of the gate voltage applied to the PMOS gate pattern, and the y axis represents the mobility of holes.

1, 2A and 2B, the curve 51 of FIG. 2A shows the mobility of electrons of the NMOS transistor according to the present invention. Curve 52 shows the mobility of electrons of a general NMOS transistor, that is, an NMOS transistor having a gate insulating film made of a silicon oxide film. As shown, when the operating voltage 53 is applied to the gate electrode, it can be seen that the mobility of the curve 51 is high. It can be seen that traps which prevent the flow of electrons at the interface between the first silicon oxynitride layer 11 and the NMOS active region are reduced.

Curve 55 in FIG. 2B shows the mobility of holes in the PMOS transistor according to the present invention. Curve 56 shows the mobility of holes in the PMOS transistor in which the PMOS gate insulating film is made of only the silicon oxynitride film. As shown in FIG. 2B, it can be seen that the mobility of the curve 55 is high when the operating voltage 57 is applied to the gate electrode. This indicates that when the silicon oxynitride film is in contact with the PMOS active region, the traps that hinder the flow of electrons decrease while the traps that hinder the flow of holes increase. In other words, the PMOS transistor according to the present invention may have the surface channel without the increase of the traps, which are sequentially stacked by the silicon oxide film 13 ′ and the second silicon oxynitride film 13 a. Although not shown, it is well known that the surface channel is improved in speed compared to the buried channel.

As a result, the operation speed of the NMOS transistor may be improved due to the NMOS gate insulating layer 14, and the mobility of holes of the PMOS transistor may not decrease due to the PMOS gate insulating layer 15. It may have the surface channel without.

3 to 9 are cross-sectional views illustrating a method of forming a CMOS semiconductor device according to a preferred embodiment of the present invention. In the drawings, reference numerals "a" and "b" denote NMOS regions and PMOS regions, respectively.

1, 2, and 3, an isolation layer 10 is formed in a predetermined region of a semiconductor substrate 9 having an NMOS region a and a PMOS region b, thereby forming the NMOS region a. The NMOS active region in the X) and the PMOS active region in the PMOS region (b) are defined. The NMOS region a is a region for forming an NMOS transistor, and the PMOS region b is a region for forming a PMOS transistor. The device isolation layer 10 may be formed as a trench device isolation layer.

A first silicon oxynitride film 11 (1st SiON layer) is formed on the entire surface of the semiconductor substrate 9 having the device isolation film 10. The first silicon oxynitride film 11 proceeds to an oxynitride process. For example, it is preferable to form by a thermal oxynitride process. The thermal oxynitride process may be a rapid thermal oxy-nitridation process or a furnace thermal oxy-nitridation process using gases such as NO, N ₂ O, NH _3, and the like. . Alternatively, the oxynitride process may be a plasma oxynitride process using gases such as NO, N ₂ O, NH _3, and the like.

The first photoresist layer pattern 12 is formed on the semiconductor substrate 9 having the first silicon oxynitride layer 11. The photoresist layer pattern 12 exposes the first silicon oxynitride layer 11 in the PMOS region b. The exposed first silicon oxynitride layer 11 is removed by an etching process to expose the PMOS active region.

The first photoresist layer pattern 12 is removed from the semiconductor substrate 9 having the exposed PMOS active region to expose the first silicon oxynitride layer 11 in the NMOS region a. A silicon oxide film 13 is formed on the entire surface of the semiconductor substrate 9 from which the photoresist pattern 12 is removed. The silicon oxide film 13 is preferably formed of a thermal oxide film. In this case, the thickness of the silicon oxide film 13 formed in the NMOS region a is thinner than the thickness of the silicon oxide film formed on the PMOS active region. This is due to the first silicon oxynitride film 11 in the NMOS region a. That is, the growth rate of the thermal oxide film formed on the first silicon oxynitride film 11 is slower than the growth rate of the thermal oxide film formed on the PMOS active region.

A nitriding process is performed on the surface of the silicon oxide film 13 to form a second silicon oxynitride film 13a. At this time, a part of the silicon oxide film 13 on the PMOS active region is left. That is, the PMOS gate insulating film 15 having the structure in which the remaining silicon oxide film 13 ′ and the second silicon oxynitride film 13 a are sequentially stacked is formed on the PMOS active region. Alternatively, the thin silicon oxide film 13 on the NMOS active region may be all formed of the second silicon oxynitride film 13a. That is, it is preferable to form the NMOS gate insulating film 14 having the structure in which the first and second silicon oxynitride films 11 and 13a are sequentially stacked on the NMOS active region. The nitriding process includes a remote plasma nitridation process, a decoupled plasma nitridation process, a slot plane antenna plasma nitridation process and an electron ion accelerator plasma nitridation process. It is preferred to proceed to one of the electron cyclotron resonance plasma niridation process.

As a result, the lower surface of the NMOS gate insulating layer 14 is formed of the first silicon oxynitride layer 11, thereby reducing traps that reduce mobility of electrons at the interface with the NMOS active region. . As a result, the operating speed characteristics of the NMOS transistor can be improved. In addition, the lower surface of the PMOS gate insulating film 15 is formed of the remaining silicon oxide film 13 ′, and the upper surface of the PMOS gate insulating film 15 is formed of the second silicon oxynitride film 13a, so that mobility of holes does not decrease. The PMOS transistor having the surface channel can be formed without. As a result, the operating speed characteristic of the PMOS transistor can be improved.

5, 6, 7, and 8, the gate electrode layer 16 is formed on the entire surface of the semiconductor substrate 9 having the NMOS and PMOS gate insulating layers 14 and 15. The gate electrode film 16 preferably forms an undoped polysilicon film. A second photoresist layer pattern 17 is formed on the gate electrode layer 16 to expose the gate electrode layer 16 in the NMOS region a. The n-type impurity ions are implanted into the gate electrode layer 16 using the second photoresist layer pattern 17 as a mask. For example, phosphorus (P) or ethnic (As) ions may be implanted. As a result, the NMOS gate electrode film 21 is formed in the NMOS region a.

The second photoresist layer pattern 17 is removed from the semiconductor substrate 9, and a third photoresist layer pattern 19 covering the NMOS gate electrode layer 21 is formed. The third photoresist layer pattern 19 exposes the gate electrode layer 16 in the PMOS region b. P-type impurity ions are implanted into the exposed gate electrode layer 16 to form a PMOS gate electrode layer 22. For example, boron (B) ions may be implanted. The third photoresist pattern 19 is removed. Thereafter, it is preferable to proceed with a thermal process for activating the implanted n-type and p-type impurities.

The metal silicide layer 23 and the hard mask layer 24 are sequentially formed on the entire surface of the semiconductor substrate 9 having the NMOS and PMOS gate electrode layers 21 and 22. The metal silicide layer 23 may be formed of a tungsten silicide layer, a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer. The hard mask layer 24 may be formed of a silicon nitride layer. The hard mask layer 24 may be omitted.

Referring to FIG. 9, the hard mask layer 24, the metal silicide layer 23, the NMOS gate electrode layer 21, and the NMOS gate insulating layer 14 in the NMOS region a may be continuously formed. The NMOS gate pattern 25 and the NMOS hard mask layer 24a are sequentially formed on the NMOS active region by patterning. The NMOS gate pattern 25 includes an NMOS gate electrode 21a and an NMOS metal silicide layer 23a that are sequentially stacked. The hard mask layer 24, the metal silicide layer 23, the PMOS gate electrode layer 22, and the PMOS gate insulating layer 15 in the PMOS region b are successively patterned. The PMOS gate pattern 26 and the PMOS hard mask layer 24b that are sequentially stacked on the active region are formed. The PMOS gate pattern 26 includes a PMOS gate electrode 22a and a PMOS metal silicide layer 23b that are sequentially stacked. The NMOS and PMOS gate patterns 25 and 26 may be simultaneously formed.

An n-type impurity diffusion layer 28 is formed in the NMOS active region on both sides of the NMOS gate pattern 25. The n-type impurity diffusion layer 28 corresponds to a source / drain region of the NMOS transistor. A p-type impurity diffusion layer 29 is formed in the PMOS active region on both sides of the PMOS gate pattern 26. The p-type impurity diffusion layer 29 corresponds to a source / drain region of the PMOS transistor. Spacers 27 may be formed on both sidewalls of the NMOS and PMOS gate patterns 25 and 26. The spacer 27 may be formed of a silicon nitride film. In this case, the n-type and p-type impurity diffusion layers 27 and 28 may be formed to have an LDD structure.

As described above, according to the present invention, the NMOS gate insulating film is formed of a silicon oxynitride film, and the PMOS gate insulating film is formed of a stacked silicon oxide film and a silicon oxynitride film. Therefore, in the case of the NMOS transistor, by reducing the traps between the NMOS gate insulating layer and the NMOS active region, it is possible to improve the operating speed characteristics of the NMOS transistor. In the case of a PMOS transistor, the PMOS transistor may have a surface channel without decreasing mobility of holes due to the PMOS gate insulating layer. Accordingly, the operating speed characteristic of the PMOS transistor can be improved.

1 is a cross-sectional view illustrating a CMOS semiconductor device according to a preferred embodiment of the present invention.

Figure 2a is a schematic graph showing the mobility of the electrons of the NMOS transistor of the CMOS device according to the present invention.

Figure 2b is a schematic graph showing the mobility of the holes of the PMOS transistor of the CMOS device according to the present invention.

3 to 9 are cross-sectional views illustrating a method of forming a CMOS semiconductor device according to a preferred embodiment of the present invention.

Claims (13)

A semiconductor substrate having an NMOS region and a PMOS region; An NMOS gate pattern on the semiconductor substrate in the NMOS region; An NMOS gate insulating layer interposed between the NMOS gate pattern and the semiconductor substrate; A PMOS gate pattern disposed on the semiconductor substrate in the PMOS region; And And a PMOS gate insulating layer interposed between the PMOS gate pattern and the semiconductor substrate, wherein a bottom surface of the NMOS gate insulating film is formed of a silicon oxynitride film, and a bottom surface of the PMOS gate insulating film is made of a silicon oxide film. The upper surface of the PMOS gate insulating film is formed of a silicon oxynitride film. The method of claim 1, The NMOS gate pattern includes a stacked n-type doped polysilicon layer and an NMOS metal silicide layer, and the PMOS gate pattern includes a stacked p-type doped polysilicon layer and a PMOS metal silicide layer. CMOS semiconductor device, characterized in that consisting of. The method of claim 1, The NMOS gate insulating layer is composed of stacked first and second silicon oxynitride layers, and the PMOS gate insulating layer is composed of stacked silicon oxide layers and silicon oxynitride layers, and the second silicon oxynitride layer of the NMOS gate insulating layer is And the same material as that of the silicon oxynitride film of the PMOS gate insulating film. The method of claim 3, wherein And the first silicon oxynitride film is at least one of a thermal oxynitride film and a plasma oxynitride film. The method of claim 3, wherein And the second silicon oxynitride layer is a plasma oxynitride layer. The method according to any one of claims 1 to 3, And the silicon oxide film is a thermal oxide film. The method according to any one of claims 1 to 3, An n-type impurity diffusion layer formed in the semiconductor substrate on both sides of the NMOS gate electrode in the NMOS region; And And a p-type impurity diffusion layer formed in the semiconductor substrate on both sides of the PMOS gate pattern in the PMOS region. Forming a first silicon oxynitride film on an entire surface of the semiconductor substrate having an NMOS region and a PMOS region; Selectively removing the first silicon oxynitride film of the PMOS region to expose the semiconductor substrate of the PMOS region; Forming a silicon oxide film on the entire surface of the semiconductor substrate, wherein the silicon oxide film is thinner than the thickness on the exposed semiconductor substrate; And Forming a second silicon oxynitride film by nitriding the silicon oxide film, and leaving the silicon oxide film in the PMOS region. The method of claim 8, The first silicon oxynitride layer is formed of one of a rapid thermal oxy-nitridation process, a furnace thermal oxy-nitridation process, and a plasma oxy-nitridation process. A method of forming a CMOS semiconductor device, characterized in that. The method of claim 8, And the silicon oxide film is formed of a thermal oxide film. The method of claim 8, Nitriding the silicon oxide film may include remote plasma nitridation process, decoupled plasma nitridation process, slot plane antenna plasma nitridation process, and electron ion accelerator. The method of forming a CMOS semiconductor device, characterized in that the selected one of the plasma (nitride process). The method of claim 8, The first and second silicon oxynitride layers stacked in the NMOS region are NMOS gate insulating layers, and the remaining silicon oxide and second silicon oxynitride layers stacked in the PMOS region are PMOS gate insulating layers. A method of forming a CMOS transistor. The method of claim 12, Forming a gate electrode film on the NMOS and PMOS gate insulating film; Selectively implanting n-type and p-type impurity ions into the gate electrode film to form an NMOS gate electrode film in the NMOS region and a PMOS gate electrode film in the PMOS region; Performing a thermal process on the semiconductor substrate having the NMOS and PMOS gate electrode films; Forming a metal silicide layer on the NMOS and PMOS gate electrode layers; The metal silicide layer and the NMOS gate electrode layer in the NMOS region are successively patterned to form an NMOS gate pattern, and the metal silicide layer and PMOS gate electrode layer in the PMOS region are successively patterned to form PMOS. Forming a gate pattern; Forming an n-type impurity diffusion layer on the semiconductor substrate on both sides of the NMOS gate pattern in the NMOS region; And And forming a p-type impurity diffusion layer in the semiconductor substrates on both sides of the PMOS gate pattern in the PMOS region.