KR100507369B1 - Method for Forming Polysilicon Plug of Semiconductor Device - Google Patents

Abstract

The present invention relates to a slurry composition for a composite film CMP consisting of a polysilicon film and an oxide film, and to a method for forming a polysilicon plug of a semiconductor device using the same, comprising a chemical mechanical polishing process using a slurry containing an additive having a high affinity for a nitride film. By removing the polysilicon film and the oxide film, the polysilicon plug of the semiconductor device can be formed so that the Pinocchio defect does not occur and the loss of the hard mask film, which is a nitride film, does not occur, so that the word line electrode is not exposed.

Description

Method for forming poly plug of semiconductor device {Method for Forming Polysilicon Plug of Semiconductor Device}

The present invention relates to a slurry composition for a composite film CMP consisting of a polysilicon film and an oxide film and a method for forming a polysilicon plug of a semiconductor device using the same, and more particularly, to a chemical composition using a slurry containing an additive having a high affinity for a nitride film. The present invention relates to a method of forming a polysilicon plug of a semiconductor device by removing a polysilicon film and an oxide film by a chemical mechanical polishing (hereinafter, referred to as "CMP") process.

In general, polysilicon plugs are widely used as contact plugs to manufacture highly integrated semiconductor devices. The polysilicon plug is formed by depositing a polysilicon film on a semiconductor substrate on which a contact hole is formed, followed by CMP treatment of the polysilicon film deposited on the entire surface of the semiconductor substrate.

1A is a plan view after forming a word line pattern, FIG. 1B is a plan view after forming a polysilicon plug contact, and FIGS. 2A to 2E are process cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to the prior art.

In this case, I represents a cell region and II represents a peripheral circuit region.

FIG. 2A is a cross-sectional view illustrating a state in which an interlayer insulating film is deposited on the AA ′ cross-section of FIG. 1A. First, a stacked pattern of a word line 12 and a hard mask film 14 is formed on an upper surface of a semiconductor substrate 10. The hard mask film 14 is formed of a nitride film and its thickness is t1.

Next, a nitride film is formed on the entire surface of the structure, and the nitride film is etched entirely to form spacers 16 on sidewalls of the stacked patterns of the word line 12 and the hard mask film 14.

Next, an interlayer insulating film 18 planarized by a CMP process is formed over the entire surface of the structure, wherein the interlayer insulating film 18 is formed of an oxide film, the thickness of which is t2 from the hard mask film 14 (Fig. 2a).

2B is a cross-sectional view taken along line BB ′ of FIG. 1B, and the polysilicon plug contact hole 20 is formed by etching the interlayer insulating layer 18 using a landing plug contact mask as an etch mask. Here, the region "C" illustrated in FIG. 1B represents a region in which the polysilicon plug contact hole 20 is formed by etching the interlayer insulating layer 18, and the region "D" does not form the polysilicon plug contact hole 20. Indicates an area that does not.

At this time, since the stacked pattern of the word line 12 and the hard mask layer 14 in the “C” region is exposed when the polysilicon plug contact 20 is formed, the upper portion of the hard mask layer 14 may be partially removed to increase the thickness. The interlayer insulating film 18 in the " D " region is reduced to t3 smaller than t1, and part of the interlayer insulating film 18 is removed by the CMP process to reduce the thickness to t4 after the polysilicon plug contact hole 20 is formed (Fig. 2b).

Next, a polysilicon film 22 is deposited on the entire surface of the structure. At this time, the "C" region and the "D" region has a step by t5 thickness due to the previous process difference. That is, the polysilicon film 22 has a step of t5 in the polysilicon plug contact hole 20, and has a step of t6 from the hard mask film 14 (see Fig. 2C).

Next, the polysilicon plug 22, the interlayer insulating film 18, and the hard mask film 14 having a predetermined thickness are removed to form the polysilicon plug 24. At this time, in order to separate the polysilicon plug 24 into the P1 region and the P2 region, a removal process of at least t6 thickness should be performed.

To this end, first, the polysilicon film 22 of the cell region I is removed so that a part of the upper part thereof is removed, and the polysilicon film 22 is removed so that all of the polysilicon film 22 of the peripheral circuit region II is removed. Full etch (see Figure 2d).

Next, using the hard mask film 14 of the cell region I as the anti-polishing film, a slurry having a similar polishing rate to the oxide film and the nitride film was used until the hard mask film 14 of the cell region I was exposed. By performing the CMP process on the polysilicon film 22 in the cell region I and the interlayer insulating film 18 in the peripheral circuit region II, a polysilicon plug 24 in which the P1 region and the P2 region are completely separated is formed. .

At this time, pinocchio defects do not occur because a slurry having a similar polishing rate to the oxide film and the nitride film is used. However, in the peripheral circuit region (II), the interlayer insulating film 18 is easily removed, and the hard mask film made of the nitride film. 14 is also easily removed to expose wordline 12 (see FIG. 2E).

FIG. 3 is an SEM image showing a word line exposed after forming a polysilicon plug of a semiconductor device according to the prior art, and as shown in the portion indicated by "E", a hard mask on the word line in the peripheral circuit region (II). It can be seen that the word line is exposed due to the film loss.

As described above, when the word line is exposed, misalignment is induced in a subsequent process, and a bridge between the word line wiring and the storage node contact is formed or a leakage current increases to fail the device. There is a problem inducing).

SUMMARY OF THE INVENTION An object of the present invention is a slurry composition for a composite film CMP comprising a polysilicon film and an oxide film containing an additive having a high affinity for a nitride film, in order to prevent a fail due to word line exposure and to increase the yield of the semiconductor device. The present invention provides a method for forming a polysilicon plug of a semiconductor device.

The slurry composition for a composite film CMP composed of a polysilicon film and an oxide film of the present invention for achieving the above object includes an anionic compound, an abrasive, and water.

In the slurry composition for CMP according to the present invention, the anionic compound is at least one compound selected from the group consisting of RCO ₂ M, ROSO ₃ M, RSO ₃ M, RPO ₄ M ₂ and R ₃ N ( Wherein R is a straight or branched substituted or unsubstituted C ₁₀ -C ₅₀ aliphatic hydrocarbon group, or a straight or branched substituted or unsubstituted C ₁₀ -C ₅₀ aromatic hydrocarbon group, M is hydrogen ion; Na Alkali metal ions such as ⁺ or K ⁺ , alkaline earth metal ions such as Mg ²⁺ or Ca ²⁺ , or NH ₄ ⁺ , where R ₃ is the same or different from each other), the linear or branched substituted Aliphatic and aromatic hydrocarbon groups include at least one of ethylene oxide, carbon-to-carbon double bonds, or carbon-to-carbon triple bonds, more specifically lauric acid, oleic acid, stearic acid. , Cow Sodium stearate, sodium lauryl sulfate, sodium lauryl ether sulfate, ammonium lauryl sulfate, triethanol ammonium lauryl sulfate ), Sodium octyl sulfate, dodecyl benzene sulfonic acid, sodium dodecyl benzene sulfonate, mono lauryl phosphate, lauryl ether phosphate lauryl ether phosphate) and dimethyl laurylamine.

The anionic compound is used in an amount of 0.01 to 10% by weight, more preferably 0.1 to 5% by weight based on the total weight of the slurry, and the abrasive is colloidal silica (SiO ₂ ), fumed silica (SiO ₂ ), alumina (Al ₂ O ₃ ), ceria (CeO ₂ ) and mixtures thereof, the size of which is 20 to 300 nm, and is used at a ratio of 0.5 to 40 wt% based on the total weight of the slurry, the slurry The pH of 2 to 7, characterized in that more preferably 3 to 6.

In addition, the polysilicon plug forming method of a semiconductor device for achieving the above object comprises the steps of (a) forming a stacked pattern of a word line and a hard mask film on the semiconductor substrate; (b) forming spacers on sidewalls of the stacked pattern; (c) forming an interlayer insulating film over the entire surface of the structure; (d) selectively etching the interlayer insulating film to form a polysilicon plug contact hole defining a polysilicon plug contact hole region, wherein the stacked pattern is present in the contact hole region; (e) depositing a polysilicon film over the entire surface of the structure; And (f) using the slurry for CMP of the present invention as described above, performing a CMP process on the entire surface of the resultant until the hard mask film is exposed.

In the method for forming a polysilicon plug of a semiconductor device according to the present invention, the word line is a polysilicon film, a doped polysilicon film, a WSi _x film, a WN film, a W film, a TiSi _x film, or a combination thereof;

The word line pattern is formed by a plasma etch process using a gas of Cl ₂ or CCl ₄ ,

The hard mask film is a nitride film,

The interlayer dielectric layer may include a borophospho silicate glass (BPSG) oxide, a phospho silicate glass (PSG) oxide film, a fluoro silicate glass (FSG) oxide film, a plasma enhanced-tetraethyl ortho silicate (PE-TEOS) oxide film, a PE-SiH ₄ oxide film, and an HDP USG high density plasma undoped silicon glass oxide film, advanced planarization layer (APL) oxide film, or a combination thereof,

The polysilicon plug contact hole is formed by a self-aligned contact process using a C ₄ F ₈ as a source,

The polysilicon film is formed by an in-situ doping method,

The step (f) is carried out using a hard pad under the conditions that the polishing pressure is 2 to 6 psi, the table rotation speed is 10 to 700 rpm (revolutions per minute), or the table moving speed is 100 to 700 fpm (feet per minute). To do that,

In the step (f), the polishing selectivity of the hard mask film: the polysilicon film: the interlayer insulating film is 1: 2 to 10: 2 to 10.

On the other hand, the principle of the present invention is as follows.

The slurry for CMP according to the present invention uses an anionic compound having a high affinity for a nitride film as an additive, and the anionic compound is a negatively charged material composed of a substituent of an alkyl group and mutually interacts with the surface of the nitride film having a positive charge. It works.

That is, when the polysilicon film and the interlayer insulating film are removed by performing a CMP process on the polysilicon film in the cell region and the interlayer insulating film in the peripheral circuit region by using the slurry for CMP according to the present invention to form a polysilicon plug, When the hard mask film is exposed, the surface of the anionic compound and the hard mask film has a cation-anion interaction.

As a result, the surface of the hard mask film has a low contact area with the abrasive, and thus the polishing rate is low. On the contrary, the surface of the polysilicon film and the interlayer insulating film has a negative charge and does not interact with the additive, thus the contact area with the abrasive is large. Polishing speed is high.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4A to 4F are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to the present invention.

In this case, I represents a cell region and II represents a peripheral circuit region.

FIG. 4A is a cross-sectional view illustrating a state in which an interlayer insulating film is deposited on the AA ′ cross-section of FIG. 1A. First, a stacked pattern of a word line 102 and a hard mask film 104 is formed on the semiconductor substrate 100. The hard mask film 104 is formed of a nitride film and its thickness is t1.

Further, the word line 102 is a polysilicon film, a doped polysilicon film, a WSi _x film, a WN film, a W film, a TiSi _x film or a combination thereof, and the word line 102 pattern is a gas of Cl ₂ or CCl ₄ . It is formed by a plasma etch process using as a source, in order to have a high selectivity with respect to the gate oxide film to be formed in a subsequent process.

Next, a nitride film is formed over the entire surface of the structure, and the nitride film is etched entirely to form spacers 106 on the sidewalls of the stacked patterns of the word line 102 and the hard mask film 104.

Next, an interlayer insulating film 108 planarized by a CMP process is formed on the entire surface of the structure, wherein the interlayer insulating film 108 is a borophospho silicate glass (BPSG) oxide film, a phospho silicate glass oxide film (PSG), a fluorocarbon FSG formed of silicate glass oxide, plasma enhanced-tetraethyl ortho silicate (PE-TEOS) oxide, PE-SiH ₄ oxide, HDP high density plasma undoped silicon glass (HDP) oxide, advanced planarization layer (APL) oxide, or a combination thereof The thickness is t2 from the hard mask film 104 (see Fig. 4A).

4B is a cross-sectional view taken along the line BB ′ of FIG. 1B, wherein the interlayer insulating layer 108 is selectively etched to form a polysilicon plug contact hole 110 defining a polysilicon plug contact hole region, wherein the polysilicon plug contact hole 110 is formed in the contact hole region. The stacked pattern is present. That is, the polysilicon plug contact hole 110 uses the landing plug contact mask as an etch mask and a self-aligned contact process using C ₄ F ₈ as a source to increase the selectivity for the oxide layer. It is formed by removing the insulating film 108.

Here, the region “C” illustrated in FIG. 1B represents a region in which the polysilicon plug contact hole 110 is formed by etching the interlayer insulating layer 108, and the region “D” does not form the polysilicon plug contact hole 110. Indicates an area that does not.

At this time, since the stacked pattern of the word line 102 and the hard mask film 104 in the "C" region is exposed when the polysilicon plug contact 110 is formed, the upper portion of the hard mask film 104 is partially removed and the thickness thereof is increased. The interlayer insulating film 108 in the " D " region is reduced to t3 smaller than t1, and part of the interlayer insulating film 108 in the " D " region is removed by the CMP process to reduce the thickness to t4 after the polysilicon plug contact hole 110 is formed (Fig. 4b).

Next, a polysilicon film 112 is deposited on the entire surface of the structure. At this time, the "C" region and the "D" region has a step by t5 thickness due to the previous process difference. That is, the polysilicon film 112 has a step of t5 in the polysilicon plug contact hole 110, and has a step of t6 from the hard mask film 104.

At this time, the polysilicon film 112 is formed using SiH ₄ or Si ₂ H ₆ as a source, preferably a doped polysilicon film formed by an in-situ doping method (FIG. 4C). Reference).

Next, the polysilicon plug 112, the interlayer insulating film 108, and the hard mask film 104 having a predetermined thickness are removed to form the polysilicon plug 114. At this time, in order to separate the polysilicon plug 114 into the P1 region and the P2 region, a removal process of at least t6 thickness should be performed.

To this end, first, the polysilicon film 112 of the cell region I is removed so that a part of the upper part thereof is removed, and the polysilicon film 112 is removed so that all of the polysilicon film 112 of the peripheral circuit region II is removed. Full etch (see Figure 4d).

Next, using the hard mask film 104 of the cell region (I) as the anti-polishing film until the hard mask film 104 of the cell region (I) is exposed, the cell region (using the CMP slurry according to the present invention) is used. The CMP process is performed on the polysilicon film 112 in I) and the interlayer insulating film 108 in the peripheral circuit region II.

At this time, the CMP process has a polishing pressure of 2 to 6 psi, and when the rotary type rotary type device is used, the table rotation speed is 10 to 200 rpm, and when the rotary type orbital type equipment is used, the table rotation speed is 100 to At 700 rpm, it is preferable to use a hard pad under the condition that the table moving speed is 100 to 700 fpm when using linear equipment.

As a result of the CMP process, the polishing selectivity of the hard mask film 104: polysilicon film 112: interlayer insulating film 108 is 1: 2 to 10: 2 to 10, and the surface of the hard mask film 104 has an abrasive ( 130, the polishing area is low due to the small contact area. On the contrary, the surfaces of the polysilicon film 112 and the interlayer insulating film 108 have a negative charge and do not interact with the additive 120, so the contact area with the abrasive 130 is reduced. Because of this size, the polishing rate is high (see FIG. 4E).

In the slurry composition for CMP according to the present invention, the anionic compound is RCO ₂ M, ROSO ₃ M, RSO ₃ M, RPO ₄ M ₂ , R ₃ N or a mixture thereof.

Wherein R is a straight or branched substituted or unsubstituted C ₁₀ -C ₅₀ aliphatic hydrocarbon group; Or a straight or branched substituted or unsubstituted C ₁₀ -C ₅₀ aromatic hydrocarbon group, M is hydrogen ion; Alkali metal ions such as Na ⁺ or K ⁺ ; Alkaline earth metal ions such as Mg ²⁺ or Ca ²⁺ ; Or NH ₄ ⁺ , and for R ₃ N R are the same or different.

The linear or branched substituted aliphatic and aromatic hydrocarbon groups preferably include at least one of ethylene oxide, an intercarbon double bond or an intercarbon triple bond.

Specific examples of the anionic compound include lauric acid, oleic acid, stearic acid, sodium stearate, sodium lauryl sulfate, sodium lauryl Sodium lauryl ether sulfate, ammonium lauryl sulfate, triethanolammonium lauryl sulfate, sodium octyl sulfate, dodecyl benzene sulfonic acid, Sodium dodecyl benzene sulfonate, mono lauryl phosphate, lauryl ether phosphate or dimethyl laurylamine.

Among them, sodium stearate, sodium lauryl sulfate, sodium dodecyl benzene sulfonate or lauryl ether phosphate is preferably used.

In addition, the anionic compound is used in a ratio of 0.01 to 10% by weight relative to the total weight of the slurry, preferably in a ratio of 0.1 to 5% by weight. When more than 10% by weight of the anionic compound is used, the polysilicon film, the oxide film, and the nitride film are densely packed in the cell region having a high pattern density, so that many anionic compounds interact with the nitride film and the polysilicon film adjacent to the nitride film. And the polishing rate for the oxide film is rather lowered. In addition, when less than 0.01% by weight of the slurry according to the present invention can not be secured.

The abrasive is colloidal silica, fumed silica, alumina, ceria or mixtures thereof, the size of which is preferably 20 to 300 nm, and is preferably used at a ratio of 0.5 to 40 wt% based on the total weight of the slurry. More specifically, in the case of silica is used in the ratio of 5 to 20% by weight relative to the total weight of the slurry, in the case of alumina is used in the ratio of 5 to 15% by weight, in the case of ceria is used in the ratio of 0.5 to 5% by weight It is preferable.

It is preferable that pHs of the said slurry are 2-7, More preferably, it is 3-6. To maintain the pH range, a buffer solution consisting of phosphoric acid (H ₃ PO ₄ ), carbonic acid (H ₂ CO ₃ ) or acetic acid (CH ₃ COOH) and salts thereof is added.

Figure 2f shows the result of performing the CMP process using the slurry for CMP according to the present invention, it shows that the polysilicon plug 114 is completely separated from the P1 region and P2 region. At this time, the thickness of the final hard mask film 104 is t7, so that the loss of the hard mask film 104 in the peripheral circuit region II does not occur, so that the word line 102 is not exposed.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail based on an Example. However, the present invention is not limited to the following examples.

A. Slurry Preparation of the Invention

Example 1 .

To 40% by weight of a typical oxide film slurry (Cabot SS-25) containing 20 to 300 nm sized fumed silica, 55% by weight of deionized water was added, and 5% by weight of sodium stearate was added with stirring to prevent aggregation. The slurry of the present invention was prepared at pH 6 by further stirring for about 30 minutes until the mixture was thoroughly mixed and stabilized. Wherein the fumed silica content is 10% by weight relative to the total weight of the final slurry.

Example 2.

To 60% by weight of a common oxide film slurry (Bayer's LEVASIL 50CK / 30% V1) containing 20 to 300 nm of colloidal silica, 1% by weight of sodium lauryl sulfate was added with stirring to avoid aggregation, and 39% of deionized water. After further addition of%, the slurry of the present invention was prepared at pH 3 by further stirring for about 30 minutes until the mixture was thoroughly mixed and stabilized. Wherein the content of the colloidal silica is 18% by weight relative to the total weight of the final slurry.

Example 3.

To 80% by weight of a common oxide film slurry containing alumina having a size of 20 to 300 nm, 10% by weight of dodecyl benzene sulfonate was added without stirring, and further 10% by weight of deionized water was added, and then the mixture was mixed thoroughly. The mixture was stirred for about 30 minutes until it stabilized to prepare the slurry of the present invention at pH 5. Wherein the content of alumina is 10% by weight relative to the total weight of the final slurry.

Example 4.

To 20% by weight of a typical oxide film slurry containing 20 to 300 nm of ceria (Showa-Denko Co., Ltd. GPL-C S2125), 70% by weight of deionized water was added, and 5% by weight of lauryl ether phosphate was stirred to prevent aggregation. After addition, 5% by weight of deionized water was further added, and then stirred for about 30 minutes until the mixture was completely mixed and stabilized to prepare the slurry of the present invention at pH 6. Wherein the content of ceria is 1% by weight relative to the total weight of the final slurry.

B. Fabrication of Semiconductor Devices Using Slurry of the Present Invention

Example 5.

Using the slurry prepared in Example 1, a CMP process was performed on the resultant of FIG. 4D with a hard pad under the conditions of a polishing pressure of 3 psi and a table rotation speed of 80 rpm (Rotary Type CMP equipment), so that steps and defects did not occur. A semiconductor device having a polysilicon plug was manufactured.

Example 6.

Using the slurry prepared in Example 2, the resultant of FIG. 4D was subjected to the CMP process with a hard pad under a polishing pressure of 3 psi and a table rotation speed of 600 rpm (Orbital Type CMP equipment), thereby separating and removing poly A semiconductor device having a silicon plug was manufactured.

Example 7.

Using the slurry prepared in Example 3, the CMP process was performed on the resultant of FIG. 4D with a hard pad under conditions of a polishing pressure of 4 psi and a table moving speed of 600 fpm (Linear Type CMP equipment), so that steps and defects were not produced. A semiconductor device having a silicon plug was manufactured.

Example 8.

Except for using the slurry prepared in Example 4 instead of the slurry prepared in Example 1 by performing the CMP process in the same manner as in Example 5 a semiconductor device having a separated polysilicon plug does not occur step and defect Was prepared.

As described above, in the present invention, when the polysilicon plug of the semiconductor device is formed using a slurry having a high polishing selectivity for the polysilicon film and the oxide film by including an anionic compound having a high affinity for the nitride film, The Pinocchio defect does not occur, and since the word mask electrode is not exposed due to no loss of the hard mask layer, which is a nitride film, the alignment error is not induced in a subsequent process. In addition, since the bridge does not form a bridge between the word line wiring and the storage node contact, and no leakage current is generated, the device may be prevented from failing to increase the final yield.

1A is a plan view after word line pattern formation.

1B is a plan view after polysilicon plug contact formation.

2A to 2E are cross-sectional views illustrating a method for forming a polysilicon plug of a semiconductor device according to the prior art;

Figure 3 is a SEM photograph showing a state in which the word line is exposed after the polysilicon plug formed of the semiconductor device according to the prior art.

4A to 4F are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10, 100: semiconductor substrate 12, 102: word line

14, 104: hard mask film 16, 106: spacer

18, 108: interlayer insulating film 20, 110: polysilicon plug contact hole

22, 112: polysilicon film 24, 114: polysilicon plug

120: additive 130: abrasive

Ⅰ: Cell area Ⅱ: Peripheral circuit area

Claims (20)

(Iii) at least one anionic compound selected from the group consisting of RCO ₂ M, ROSO ₃ M, RSO ₃ M, RPO ₄ M ₂ and R ₃ N, provided that R is linear or branched or unsubstituted C ₁₀ An aliphatic hydrocarbon group of -C ₅₀ , or a straight or branched substituted or unsubstituted aromatic hydrocarbon group of C ₁₀ -C ₅₀ , M is a hydrogen ion, an alkali metal ion such as Na ⁺ or K ⁺ , Mg ²⁺ or Ca Alkaline earth metal ions such as ²⁺ , or NH ₄ ⁺ , hydrogen ions are excluded from M for RCO ₂ M, NH ₄ ⁺ is excluded from M for ROSO ₃ M, and R is the same as for R ₃ N Or else); (Ii) an abrasive selected from the group consisting of colloidal silica (SiO ₂ ), fumed silica (SiO ₂ ), alumina (Al ₂ O ₃ ), and mixtures thereof; And (Iii) A slurry composition for composite film CMP, comprising a polysilicon film and an oxide film, comprising water. delete The method of claim 1, The linear or branched-substituted aliphatic and aromatic hydrocarbon groups are each CMP slurry composition comprising at least one or more of ethylene oxide, inter-carbon double bond and inter-carbon triple bond. The method of claim 1, The anionic compound is sodium stearate, sodium lauryl sulfate, sodium lauryl ether sulfate, sodium octyl sulfate, dodecyl benzene sulfonic acid benzene sulfonic acid, sodium dodecyl benzene sulfonate, mono lauryl phosphate, lauryl ether phosphate and dimethyl laurylamine Slurry composition for CMP, characterized in that selected. The method of claim 1, The anionic compound is a slurry composition for CMP, characterized in that used in a ratio of 0.01 to 10% by weight relative to the total weight of the slurry. The method of claim 5, The anionic compound is a slurry composition for CMP, characterized in that used in a ratio of 0.1 to 5% by weight relative to the total weight of the slurry. delete The method of claim 1, Slurry composition for CMP, characterized in that the size of the abrasive is 20 to 300nm. The method of claim 1, Slurry composition for CMP, characterized in that the abrasive is used in a proportion of 0.5 to 40% by weight relative to the total weight of the slurry. The method of claim 1, PH of the slurry is 2 to 7, characterized in that the slurry composition for CMP. The method of claim 10, PH of the slurry is a slurry composition for CMP, characterized in that 3 to 6. (a) forming a stacked pattern of a word line and a hard mask film on the semiconductor substrate; (b) forming spacers on sidewalls of the stacked pattern; (c) forming an interlayer insulating film over the entire surface of the structure; (d) selectively etching the interlayer insulating film to form a polysilicon plug contact hole defining a polysilicon plug contact hole region, wherein the stacked pattern is present in the contact hole region; (e) depositing a polysilicon film over the entire surface of the structure; And (f) using the slurry for CMP according to claim 1, performing a CMP process on the entire surface of the resultant until the hard mask film is exposed. The method of claim 12, And the word line is a polysilicon film, a doped polysilicon film, a WSi _x film, a WN film, a W film, a TiSi _x film, or a combination thereof. The method of claim 12, The word line pattern is a polysilicon plug forming method of a semiconductor device, characterized in that formed by a plasma etch process using a gas of Cl ₂ or CCl ₄ source. The method of claim 12, And said hard mask film is a nitride film. The method of claim 12, The interlayer dielectric layer may include a borophospho silicate glass (BPSG) oxide, a phospho silicate glass (PSG) oxide film, a fluoro silicate glass (FSG) oxide film, a plasma enhanced-tetraethyl ortho silicate (PE-TEOS) oxide film, a PE-SiH ₄ oxide film, and an HDP USG A method for forming a polysilicon plug of a semiconductor device, the method comprising: an oxide film, an advanced planarization layer (APL) oxide film, or a combination thereof. The method of claim 12, The polysilicon plug contact hole is a polysilicon plug forming method of a semiconductor device, characterized in that formed by a self-aligned contact process using C ₄ F ₈ as a source. The method of claim 12, The polysilicon film is a polysilicon plug forming method of a semiconductor device, characterized in that formed by the in-situ doping (in-Situ Doping) method. The method of claim 12, The step (f) is carried out using a hard pad under the conditions that the polishing pressure is 2 to 6 psi, the table rotation speed is 10 to 700 rpm (revolutions per minute), or the table moving speed is 100 to 700 fpm (feet per minute). Polysilicon plug forming method of a semiconductor device, characterized in that. The method of claim 12, The method for forming a polysilicon plug of a semiconductor device according to step (f), wherein the polishing selectivity of the hard mask film: the polysilicon film: the interlayer insulating film is 1: 2 to 10: 2 to 10.