KR20000045411A - Method for forming dual damascene of semiconductor device - Google Patents
Method for forming dual damascene of semiconductor device Download PDFInfo
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- KR20000045411A KR20000045411A KR1019980061969A KR19980061969A KR20000045411A KR 20000045411 A KR20000045411 A KR 20000045411A KR 1019980061969 A KR1019980061969 A KR 1019980061969A KR 19980061969 A KR19980061969 A KR 19980061969A KR 20000045411 A KR20000045411 A KR 20000045411A
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- bit line
- contact
- forming
- damascene
- line
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000009977 dual effect Effects 0.000 title claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 238000003860 storage Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 62
- 150000004767 nitrides Chemical class 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000001052 transient effect Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체소자를 제조함에 있어, 콘택식각 공정과 라인/스페이스 식각 공정을 동시에 사용하는 메모리 또는 비메모리 반도체 소자의 배선패턴 형성공정에 적합하도록한 반도체소자의 이중 다마신 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to manufacturing a semiconductor device, to be suitable for a wiring pattern forming process of a memory or non-memory semiconductor device using a contact etching process and a line / space etching process simultaneously. A method for forming a double damascene of a semiconductor device.
종래의 이중 다마신 공정(Dual Damascene Process)에는 여러 가지 공정 방법이 사용되고 있다.Various process methods are used in the conventional dual damascene process.
그런데, 식각 방지막 증착 → 산화막 증착 → 콘택 식각 → 라인/스페이스 식각의 순서로 진행되는 공정 방법은 콘택 식각시 산화막 및 식각 방지막까지 식각되어 플러그가 드러나게 된다.However, in the process of etching prevention layer deposition → oxide layer deposition → contact etching → line / space etching, the plug is etched by the oxide layer and the etching prevention layer during contact etching.
이후, 라인/스페이스 패턴 식각시 종전에 형성되었던 콘택 패턴에서 플러그와 오정렬(Misalign)된 주위의 산화막이 식각되어 심한 손실(Loss)이 발생하면 필드산화막까지 손실되는 문제가 발생하게 된다.Subsequently, when the line / space pattern is etched, the oxide layer around the plug misaligned with the plug pattern is etched in the contact pattern that was previously formed, thereby causing a loss to the field oxide layer.
이에, 본 발명은 상기 종래의 문제점을 해결하기 위하여 안출한 것으로서, 비트라인용 콘택플러그와 이중다마신에서의 콘택과의 오정렬에 의해 발생하는 산화막의 손실을 방지하고자한 반도체소자의 이중 다마신 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and the formation of double damascene of a semiconductor device intended to prevent the loss of the oxide film caused by misalignment between the contact of the bit line contact plug and the contact in the double damascene. In providing a method.
또한, 본 발명의 다른 목적은 하부패턴과 오정렬 발생시에 하부패턴의 손실 문제를 해결할 수 있어, 비트라인 공정 뿐 아니라 배선화 공정을 사용하는 메모리 또는 비메모리 소자의 제조 공정에 적합한 반도체소자의 이중다마신 형성방법을 제공함에 있다.In addition, another object of the present invention is to solve the problem of the loss of the lower pattern when the lower pattern and misalignment occurs, the dual damascene of the semiconductor device suitable for the manufacturing process of memory or non-memory device using the wiring process as well as the bit line process It is to provide a formation method.
그리고, 본 발명의 또다른 목적은 구리와 같이 식각 공정이 어려운 물질의 패터닝 공정에 적용할 수 있는 반도체소자의 이중다마신 형성방법을 제공함에 있다.상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 형성된 게이트의 상부와 측면에 각각 게이트마스크와 절연막스페이서를 형성하는 공정과;In addition, another object of the present invention is to provide a method for forming a double damascene of a semiconductor device that can be applied to the patterning process of a material difficult to etch such as copper. The present invention for achieving the above object is a semiconductor substrate Forming a gate mask and an insulating film spacer on upper and side surfaces of the gate formed thereon, respectively;
상기 게이트마스크상에 산화막을 증착한후 CMP 공정을 진행하여 평탄화를 실시하는 공정과;Depositing an oxide film on the gate mask and performing a CMP process to planarize the oxide film;
상기 평탄화 공정후 상기 산화막을 선택적으로 제거하여 비트라인 콘택과 스토리지노드 콘택을 형성하는 공정과;Selectively removing the oxide layer after the planarization process to form a bit line contact and a storage node contact;
상기 콘택을 포함한 전체구조의 상부에 플러그 물질을 증착하고 이를 CMP 또는 에백 공정에 의해 선택적으로 제거하여 비트라인용 콘택플러그 및 스토리지노드 콘택플러그를 형성하는 공정과;Depositing a plug material on top of the entire structure including the contact and selectively removing the plug material by a CMP or EB back process to form a bit line contact plug and a storage node contact plug;
상기 전체 구조의 상부에 콘택플러그상부에 제1산화막과 식각 방지막인 실리콘 옥시나이트라이드막을 형성하고 그 위에 제2산화막을 형성하는 공정과;Forming a first oxide film and a silicon oxynitride film as an anti-etching film on the contact plug and forming a second oxide film over the contact plug;
상기 제2산화막상에 비트라인용 다마신 라인/스페이스 마스크를 형성하는 공정과;Forming a damascene line / space mask for a bit line on the second oxide film;
상기 비트라인 다마신 라인/스페이스 마스크로 상기 제2산화막을 선택적으로 식각하여 라인/스페이스패턴을 형성하는 공정과;Selectively etching the second oxide layer using the bit line damascene line / space mask to form a line / space pattern;
상기 비트라인 다마신 라인/스페이스마스크를 제거하고, 상기 라인/스페이스패턴상에 비트라인 다마신 라인/스페이스콘택마스크를 형성하는 공정과;Removing the bit line damascene line / space mask and forming a bit line damascene line / space contact mask on the line / space pattern;
상기 비트라인 다마신 라인/스페이스콘택마스크로 상기 제1산화막 및 실리콘 옥시나이트라이드막을 선택적으로 제거하여 상기 비트라인용 플러그위에 콘택패턴을 형성하고 상기 라인/스페이스패턴의 측벽에 콘택프로파일을 형성하는 공정과;Selectively removing the first oxide layer and the silicon oxynitride layer with the bit line damascene line / space contact mask to form a contact pattern on the bit line plug and to form a contact profile on sidewalls of the line / space pattern and;
상기 비트라인용 다마신 라인/스페이스 콘택마스크를 제거하고, 상기 비트라인용 다마신 라인/스페이스패턴의 콘택프로파일과 콘택패턴의 측벽에 질화막스페이서를 형성하는 공정과;Removing the bit line damascene line / space contact mask and forming a nitride film spacer on the sidewall of the contact pattern and the contact pattern of the bit line damascene line / space pattern;
상기 전체구조의 상부에 비트라인물질을 증착하고 이를 선택적으로 제거하여 비트라인을 형성하는 공정을 포함하여 구성되는 것을 특징으로한다.And forming a bit line by depositing and selectively removing the bit line material on top of the entire structure.
본 발명의 기술적 요지는, 비교적 얇은 제1완충산화막(Buffer Oxide)을 증착한 후, 산화막에 대한 식각 선택비가 높은 실리콘 옥시나이트라이드막를 식각 방지막으로 증착하고 라인/스페이스가 형성될 제2산화막을 증착후, 라인/스페이스 패턴을 식각한다.The technical gist of the present invention is that after depositing a relatively thin buffer oxide, a silicon oxynitride film having a high etching selectivity with respect to the oxide film is deposited as an etch stop layer, and a second oxide film is formed to form a line / space. After that, the line / space pattern is etched.
이때, 라인/스페이스 패턴은 식각 방지막에서 식각이 멈추는데 이는 산화막과 실리콘 옥시나이트라이드와의 식각 선택비를 이용하기 때문에 가능하다.In this case, the etching of the line / space pattern is stopped in the etch stop layer because the etching selectivity between the oxide layer and the silicon oxynitride is used.
라인/스페이스 패턴 형성후, 비트라인용 콘택플러그 상부에 선택적으로 콘택 패턴을 형성하면, 하부의 플러그와 연결된 비트라인용 이중다마신공정 (Dual Damascene Process)이 완료된다.After forming the line / space pattern, if a contact pattern is selectively formed on the contact plug for the bit line, the dual damascene process for the bit line connected to the lower plug is completed.
콘택 형성시, 라인/스페이스에 비해 얇은 옥시나이트라이드와 완충산화막(Buffer Oxide)가 식각되는데 오정렬(Misalign)이 발생하여도 과도식각에 대한 타겟트(Target) 자체가 작기 때문에 오정렬(Misalign)된 플러그주위의 산화막 손실은 매우 작게 되어 상기와 같은 문제를 해결할 수 있다.When forming contacts, thin oxynitride and buffer oxides are etched compared to lines / spaces, and misaligned plugs because the target itself for transient etching is small even when misalignment occurs. The oxide film loss around is very small, which can solve the above problem.
도 1 은 본 발명에 따른 소자분리 공정 후 질화막 하드마스크 및 질화막 스페이서를 형성한 게이트의 도면,1 is a view of a gate on which a nitride film hard mask and a nitride film spacer are formed after a device isolation process according to the present invention;
도 2 는 본 발명에 따른 평탄화산화막(IPO ; Inter Poly Oxide) 증착후 산화막 CMP를 이용하여 평탄화 공정을 진행하여 형성된 플러그를 설명하기 위한 도면,2 is a view for explaining a plug formed by performing a planarization process using an oxide film CMP after deposition of a planarization oxide film (IPO) according to the present invention;
도 3 은 본 발명에 따른 제1산화막, 실리콘 옥시나이트라이드막(SiON) 및 제2산화막 증착후의 도면,3 is a view after deposition of the first oxide film, silicon oxynitride film (SiON) and the second oxide film according to the present invention,
도 4 는 본 발명에 따른 제2산화막 상부에 비트라인다마신(Bit Line Damascence) 용 라인/스페이스마스크를 형성한 후의 도면,4 is a view after forming a line / space mask for bit line damascence on the second oxide film according to the present invention;
도 5 는 본 발명에 따른 제2산화막에 비트라인다마신용 라인/스페이스패턴 형성후의 도면,5 is a view after the formation of the line / space pattern for bit line damascene in the second oxide film according to the present invention,
도 6 은 본 발명에 따른 비트라인 다마신용 콘택마스크를 이용하여 하부의 실리콘 옥시나이트라이드막(SiON) 및 제1산화막의 식각에의한 비트라인콘택플러그를 개구시킨 후의 도면이다.6 is a view after opening the bit line contact plug by etching the lower silicon oxynitride layer (SiON) and the first oxide layer using the bit line damascene contact mask according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
1 : 게이트패턴 2 : 질화막 하드마스크(Nitride Hard Mask)1: gate pattern 2: nitride hard mask
3 : 질화막 스페이서(Nitride Spacer) 4 : 산화막(Inter Ply Oxide)3: Nitride Spacer 4: Inter Ply Oxide
5 : 비트라인용 플러그 6 : 스토리지노드용 플러그5: plug for bit line 6: plug for storage node
7 : 제1산화막(SiO2) 8 : 실리콘 옥시나이트라이드(SiON)7: first oxide film (SiO 2) 8: silicon oxynitride (SiON)
9 : 제2산화막 10 : 비트라인다마신 라인/스페이스마스크9: second oxide film 10: bit line damascene line / space mask
11 : 비트라인마스크를 이용하여 라인/스페이스식각후의 프로파일11: Profile after line / space etching using bit line mask
12 : 비트라인/스페이스패턴에 콘택패턴 형성후의 프로파일12: Profile after contact pattern formation on bit line / space pattern
이하, 본 발명에 따른 반도체소자의 이중 다마신 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming double damascene of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 은 본 발명에 따른 소자분리 공정후 질화막 하드마스크 및 질화막 스페이서를 형성한 게이트의 도면이다.1 is a view illustrating a gate in which a nitride film hard mask and a nitride film spacer are formed after a device isolation process according to the present invention.
도 2 는 본 발명에 따른 평탄화산화막(IPO) 증착후 산화막 CMP를 이용하여 평탄화 공정을 진행하여 형성된 플러그를 설명하기 위한 도면이다.2 is a view for explaining a plug formed by performing a planarization process using an oxide film CMP after deposition of a planarization oxide film (IPO) according to the present invention.
도 3 은 본 발명에 따른 제1산화막, 실리콘 옥시나이트라이드막(SiON) 및 제2산화막 증착후의 도면이다.3 is a view after deposition of a first oxide film, a silicon oxynitride film (SiON) and a second oxide film according to the present invention.
도 4 는 본 발명에 따른 제2산화막 상부에 비트라인다마신 (Bit Line Damascence) 용 라인/스페이스마스크를 형성한 후의 도면이다.FIG. 4 is a view after forming a line / space mask for bit line damascence on the second oxide layer according to the present invention.
도 5 는 본 발명에 따른 제2산화막에 비트라인다마신 라인/스페이스패턴 형성후의 도면이다.5 is a view after the formation of the bit line damascene line / space pattern in the second oxide film according to the present invention.
도 6 은 본 발명에 따른 비트라인 다마신용 콘택마스크를 이용하여 하부의 실리콘 옥시나이트라이드(SiON) 및 제1산화막의 식각에의한 비트라인콘택플러그를 개구시킨 후의 도면이다.6 is a view after opening the bit line contact plug by etching the silicon oxynitride (SiON) and the first oxide film of the lower portion using the bit line damascene contact mask according to the present invention.
본 발명은, 도 1 에 도시된 바와같이, 소자분리공정후 활성영역상에 상부와 측면에 각각 질화막 하드마스크(3)와 질화막 스페이서(2)가 존재하는 게이트(1)를 형성한다.In the present invention, as shown in FIG. 1, after the device isolation process, a gate 1 having a nitride hard mask 3 and a nitride spacer 2 is formed on the top and side surfaces of the active region, respectively.
그다음, 도 2 에 도시된 바와같이, 평탄화산화막 (IPO ; Inter Poly Oxide)(4)를 증착하고, 게이트(1) 상부의 질화막하드마스크(3)를 스톱층(Stopping Layer)로하여 CMP(Chemical Mechanical Polish) 공정을 진행하므로써 산화막 평탄화 공정을 진행한다.Next, as illustrated in FIG. 2, a planarization oxide (IPO) 4 is deposited, and the CMP (Chemical) is formed by using the nitride hard mask 3 over the gate 1 as a stop layer. Mechanical Polishing) to proceed the oxide film planarization process.
이어서, 평탄화 공정후 비트라인(Bit Line)용 및 스토리지노드(Storage Node)용 플러그콘택(Plug Contact)(미도시)을 형성하고, 플러그물질(Plug Material)을 증착 하고, 이를 연마(Chemical Mechanical Polishing, CMP)하여 비트라인용 플러그(5) 및 스토리지노드용 플러그(6)를 형성한다.Subsequently, after the planarization process, a plug contact (not shown) for a bit line and a storage node is formed, a plug material is deposited, and the chemical mechanical polishing is performed. , CMP) to form a bit line plug 5 and a storage node plug 6.
이때, 상기 플러그 형성공정은 패턴 미세화에 따른 에스펙트비(Aspect Ratio) 증가에 의해 발생하는 콘택이 개구되지 않는 (Contact Not Open) 문제를 해결하기 위해 하부에 미리 형성한다.In this case, the plug forming process is previously formed in the lower part in order to solve the problem of the contact not opening due to the increase of the aspect ratio due to the pattern miniaturization.
그다음, 도 3 에 도시된 바와같이, 하부의 비트라인용플러그(5) 및 스토리지노드용 플러그(6)위에 제1산화막(7)을 증착하고, 그 상부에 산화막과의 식각선택비를 갖는 장벽층, 즉 실리콘 옥시나이트라이드막(SiON)(8)를 증착한후 그 상부에 제2산화막(9)을 순차적으로 증착한다.Next, as shown in FIG. 3, a first oxide film 7 is deposited on the lower bit line plug 5 and the storage node plug 6, and a barrier having an etch selectivity with the oxide film thereon. After depositing a layer, that is, a silicon oxynitride film (SiON) 8, a second oxide film 9 is sequentially deposited on the layer.
이때, 상기 제1산화막(7) 및 실리콘옥시나이트라이드막(8)은 50 ∼ 1000 Å 두께로 형성하며, 상기 제2산화막(9)은 500 ∼ 5000 Å 두께로 형성한다.In this case, the first oxide film 7 and the silicon oxynitride film 8 are formed to have a thickness of 50 to 1000 GPa, and the second oxide film 9 is formed to have a thickness of 500 to 5000 GPa.
이어서, 도 4 에 도시된 바와같이, 도 3 에서 증착된 제2산화막(9)위에 비트라인 다마신용 라인/스페이스 패턴 마스크(10)를 형성한다.Subsequently, as shown in FIG. 4, the bit line damascene line / space pattern mask 10 is formed on the second oxide film 9 deposited in FIG. 3.
그다음, 도 5 에 도시된 바와같이, 상기 비트라인마스크(10)를 사용하여 상기 제2산화막(9)를 선택적으로 제거하여 라인/스페이스패턴을 형성한다.Then, as shown in FIG. 5, the bit line mask 10 is used to selectively remove the second oxide layer 9 to form a line / space pattern.
이때, 상기 제2산화막(9)에 라인/스페이스패턴을 형성할때 산화막과 실리콘 옥시나이트라이드막의 식각 선택비를 이용하여 실리콘 옥시나이트라이드막 상부에서 식각을 중시시키는 공정 방법 또는 산화막 식각시 과도식각(Over Etch) 타겟트를 산화막 두께의 10% - 100% 까지 진행하는 공정방법을 사용할 수 있다.At this time, when forming a line / space pattern on the second oxide layer (9) by using the etching selectivity of the oxide film and silicon oxynitride layer to focus on the etching on the silicon oxynitride layer or over-etching during the oxide layer etching (Over Etch) A process method of advancing the target to 10% to 100% of the oxide film thickness may be used.
또한, 상기 제2산화막(9) 식각시, 산화막과 실리콘 옥시나이트라이드막(SiON)과의 식각 선택비를 유지하기 위해 CF4/ CHF3/ Ar Base의 산화막 식각 가스중에서 CF4 가스를 많이 사용할때 산화막과 실리콘 옥시나이트라이드(SiON)의 식각선택비가 작아지므로 CHF3/ Ar Base의 식각 가스를 이용하여 식각공정을 진행하며, 산화막과의 식각선택비를 3:1 이상으로 유지하는 것이 바람직하다.In addition, when the second oxide layer 9 is etched, when the CF4 gas is used in the CF4 / CHF3 / Ar Base oxide layer etching gas to maintain the etching selectivity between the oxide layer and the silicon oxynitride layer (SiON), Since the etching selectivity of silicon oxynitride (SiON) is reduced, the etching process is performed using an etching gas of CHF 3 / Ar Base, and the etching selectivity with the oxide film is preferably maintained at 3: 1 or more.
이때, 상기 식각 진행시 제2산화막(9)이 선택적으로 제거되고, 그 하부의 실리콘 옥시나이트라이드(8) 및 제1산화막(7)까지 식각이 된다면 하부패턴과의 오정렬이 발생시에 비트라인과 비트라인용 플러그(5) 및 스토리지노드용 플러그(6)가 서로 접촉하게 되므로써 반도체 소자의 치명적인 불량(Fail)을 유발하게 된다.At this time, if the second oxide film 9 is selectively removed during the etching process and the silicon oxynitride 8 and the first oxide film 7 are etched below, the bit line and the lower pattern may be misaligned. The bit line plug 5 and the storage node plug 6 are brought into contact with each other to cause a fatal failure of the semiconductor device.
그러므로, 본 발명에서는 라인/스페이스패턴을 형성하기 위한 제2산화막(9) 식각시 산화막과 실리콘 옥시나이트라이드막의 식각선택비를 이용하여 하부의 실리콘 옥시나이트라이드막(8)에서 식각중지(Etch Stop)가 되도록 한다.Therefore, in the present invention, when the second oxide layer 9 is etched to form the line / space pattern, the etching stop is performed in the lower silicon oxynitride layer 8 by using the etching selectivity of the oxide layer and the silicon oxynitride layer. )
이어서, 도 6 에 도시된 바와같이, 식각방지막인 실리콘 옥시나이트라이드막(8)과 제1산화막(7)이 식각되어 비트라인콘택플러그(5)가 드러나고, 적절한 과도 식각에 의해 오정렬된 플러그주위의 산화막 손실이 적음을 알 수 있다.Subsequently, as shown in FIG. 6, the silicon oxynitride film 8 and the first oxide film 7, which are anti-etching films, are etched to expose the bit line contact plug 5, and the plug periphery is misaligned by an appropriate transient etching. It can be seen that the oxide film loss is low.
즉, 식각 타겟트는 실리콘 옥시나이트라이드막(8)과 제1산화막(7)의 두께만큼이므로 이에 대한 과도 식각이 진행되더라도 비트라인용 콘택플러그(5)주위의 산화막 손실을 매우 작게 할 수 있다.That is, since the etch target is as thick as the silicon oxynitride film 8 and the first oxide film 7, even if an excessive etching is performed, the oxide film loss around the bit line contact plug 5 can be made very small.
또한, 후속공정시에 라인/스페이스패턴과 콘택패턴의 오정렬 발생시 콘택식각중에 제 2산화막(9)이 콘택식각 타겟트만큼 손실이 발생하게 된다.In the subsequent process, when the misalignment of the line / space pattern and the contact pattern occurs, the second oxide layer 9 loses as much as the contact etching target during the contact etching.
이는 이후 공정인 비트라인 증착공정시에 콘택내부의 스페이스를 크게 하므로 비트라인물질의 증착정도를 개선시키는 효과가 있다.This increases the space inside the contact during the subsequent bit line deposition process, thereby improving the degree of deposition of the bit line material.
이때, 상기 라인/스페이스패턴에 비트라인콘택패턴을 형성하여 비트라인 콘택플러그를 개구시킬때, 실리콘 옥시나이트라이드막과 그 하부의 제1산화막까지 식각하고, 그 과도식각 타겟트는 실리콘 옥시나이트라이드막과 그 하부의 제1산화막을 합친 두께의 10% - 100% 까지 진행시킨다.At this time, when the bit line contact plug is formed by forming a bit line contact pattern in the line / space pattern, the silicon oxynitride layer and the first oxide layer under the etching are etched, and the transient etching target is a silicon oxynitride layer. And 10% to 100% of the combined thickness of the first oxide film and the lower portion thereof.
또한, 상기 라인/스페이스패턴위에 비트라인콘택마스크를 이용하여 비트라인콘택을 위한 식각을 진행할때, 제2산화막의 라인스페이스패턴에 콘택식각타겟트만큼의 콘택프로파일을 형성하여 후속공정인 비트라인증착 공정시 비트라인물질의 증착 정도를 개선시킨다.In addition, when etching the bit line contact using the bit line contact mask on the line / space pattern, a contact profile as much as a contact etching target is formed in the line space pattern of the second oxide layer, thereby forming a subsequent non-certification process. Improve the degree of deposition of bit line material in the process.
그다음, 도면에는 도시하지 않았지만, 비트라인 다마신용 라인/스페이스패턴과 콘택패턴상부에 질화막을 형성한다.Next, although not shown in the figure, a nitride film is formed over the line / space pattern for the bit line damascene and the contact pattern.
이어서, 도면에는 도시하지 않았지만, 상기 질화막을 마스크없이 식각하여 라인/스페이스패턴과 콘택패턴측벽에 질화막스페이서를 형성한다.Subsequently, although not shown in the drawing, the nitride film is etched without a mask to form a nitride film spacer on the sidewalls of the line / space pattern and the contact pattern.
이때, 상기 질화막은 자기정렬방식콘택(self-aligned Contact)공정에서 제1산화막을 식각방지막으로 사용한다. 이때, 상기 질화막의 두께는 100 ∼ 1000 Å로 형성한다.In this case, the nitride layer uses the first oxide layer as an etch stop layer in a self-aligned contact process. At this time, the thickness of the nitride film is formed to 100 ~ 1000 kPa.
또한, 상기 질화막을 마스크없이 식각할때, 그 과도식각 타겟트를 질화막 두께의 10% - 100% 까지 진행하는 공정 방법과, 질화막 과도식각시 실리콘옥시나이트라이드막이 제거되더라도 질화막에 대한 식각 선택비가 콘 하부의 제1산화막을 이용하여 식각을 중지시키는 방법을 사용한다.In addition, when the nitride film is etched without a mask, a process method of advancing the transient etching target to 10% to 100% of the thickness of the nitride film and an etching selectivity ratio to the nitride film even if the silicon oxynitride film is removed during the nitride film overetching A method of stopping etching by using a lower first oxide film is used.
이때, 상기 질화막은 CF4/ O2/ Ar 식각가스를 이용하며, 각 가스의 비율을 조절하여 질화막에 대한 산화막의 식각 선택비를 3:1 이상으로 유지하는 것이 바람직하다.In this case, the nitride film is CF4 / O2 / Ar etching gas, it is preferable to maintain the etching selectivity ratio of the oxide film to the nitride film 3: 1 or more by adjusting the ratio of each gas.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 이중 다마신 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of forming the double damascene of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 콘택 및 라인/스페이스 패턴을 동시에 형성하는 이중다마신 (Dual Damascene) 공정시에, 먼저 비트라인과 비트라인용 콘택플러그 및 스토리지노드용 콘택플러그와의 쇼트(Short)를 막기 위해 식각방지막인 실리콘 옥시나이트라이드막을 이용하여 제2산화막에 라인/스페이스 패턴을 형성시키고, 비트라인용 콘택플러그를 노출시키기 위한 콘택식각을 나중에 실시하므로써 오정렬된 플러그주위의 산화막이 손실되는 것을 최소화할 수 있다.In the present invention, in the dual damascene process of simultaneously forming a contact and a line / space pattern, first, in order to prevent a short between a bit line, a bit line contact plug, and a storage node contact plug, By forming a line / space pattern on the second oxide film using a silicon oxynitride film, which is an etching prevention film, and performing contact etching later to expose the contact plug for the bit line, the loss of the oxide film around the misaligned plug can be minimized. have.
또한, 라인/스페이스 패턴의 라인부분에 형성된 콘택패턴의 일부는 초미세패턴에서의 비트라인물질 또는 배선화시 금속 증착을 용이하게 하는 효과가 있다.In addition, a part of the contact pattern formed on the line portion of the line / space pattern has an effect of facilitating metal deposition at the time of wiring or bit line material in the ultra-fine pattern.
따라서, 본 발명은 하부패턴과 오정렬 발생시에 하부패턴의 손실 문제를 해결할 수 있어, 비트라인 공정 뿐 아니라 배선화 공정을 사용하는 메모리 또는 비메모리 소자의 제조 공정에 사용할 수 있으며, 특히 구리와 같이 식각 공정이 어려운 물질의 패터닝 공정에 적용할 수 있다.Therefore, the present invention can solve the problem of the loss of the lower pattern when the lower pattern and misalignment occurs, it can be used in the manufacturing process of the memory or non-memory device using the wiring process as well as the bit line process, especially etching process such as copper It is applicable to the patterning process of this difficult material.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100734083B1 (en) * | 2001-06-28 | 2007-07-02 | 주식회사 하이닉스반도체 | A method for forming contact hole of semiconductor device |
| US7566659B2 (en) | 2004-06-22 | 2009-07-28 | Samsung Electronics Co., Ltd. | Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same |
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| KR102432733B1 (en) | 2015-11-24 | 2022-08-17 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100734083B1 (en) * | 2001-06-28 | 2007-07-02 | 주식회사 하이닉스반도체 | A method for forming contact hole of semiconductor device |
| US7566659B2 (en) | 2004-06-22 | 2009-07-28 | Samsung Electronics Co., Ltd. | Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same |
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