KR100505426B1 - Method for forming bit line of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a bit line of a semiconductor device. The disclosed bit line forming method includes forming an interlayer insulating film made of BPSG on a semiconductor substrate on which a landing plug is formed; Etching the interlayer insulating film to form a bit line contact exposing a landing plug; Performing a wet clean to remove polymer residues in the bitline contacts; Performing a wet cleaning again to remove the native oxide film on the bottom of the bit line contact; Sequentially depositing a barrier film and a bit line metal film on the bit line contact and the interlayer insulating film; And patterning the metal film and the barrier film for the bit line, wherein the wet cleaning after the bit line contact etching and before the barrier film deposition is performed by HF and NH4F, respectively. It is characterized by performing using a BOE solution containing 0.10wt% and 39-41wt%. According to the present invention, the loss of the bitline contact CD can be lowered to half of the conventional level by using a BOE solution having a high NH4F composition ratio during wet cleaning after bitline contact etching and before barrier film deposition. Since the occurrence of bridges between line contacts can be prevented, the production yield can be improved.

Description

Method for forming bit line of semiconductor device

The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a method for preventing contact hole CD loss from wet cleaning after bit line contact etching and before depositing a barrier film.

As is well known, recent semiconductor manufacturing processes use metal materials having excellent electrical properties, such as tungsten, instead of conventional polysilicon as bit line materials. In forming the tungsten bit line, a barrier film of Ti / TiN is interposed between the landing plug and the tungsten film.

Hereinafter, a conventional tungsten bit line forming method will be briefly described.

First, a first interlayer insulating film is deposited on a semiconductor substrate on which a predetermined lower structure including a gate and a junction region is formed. Then, the first interlayer insulating layer is etched to form a large contact hole, ie, a landing plug contact, which exposes a plurality of gates and a junction region between the gates at the same time, and then the landing plug contact. A polysilicon film is embedded in the landing plug to form a landing plug.

Next, a second interlayer insulating film made of, for example, BPSG is deposited on the first interlayer insulating film including the landing plug. Then, the second interlayer insulating layer is etched to form a contact hole, that is, a bit line contact, which exposes the landing plug to be contacted with the bit line.

Next, after depositing a Ti / TiN barrier film on the bit line contact surface and the second interlayer insulating film, a tungsten film is deposited to fill the bit line contact on the Ti / TiN barrier film.

Then, the tungsten film and the Ti / TiN barrier film are etched to form a tungsten bit line.

Meanwhile, after the bit line contact etching and before the deposition of the Ti / TiN barrier film, BOE (Buffered Oxide) composed of a mixture of HF and NH4F for removal of polymer residue and removal of native oxide, respectively. Wet cleaning using an etchant) solution.

However, in the above-described wet cleaning, the loss of the interlayer insulating film is inevitably caused by BOE, which is a cleaning liquid, and thus, a bit line contact CD (critical dimension) loss is generated.

In addition, this bitline contact CD loss becomes larger as the wet cleaning is repeatedly performed, resulting in a bridge between the bitline contacts, as shown in FIG. 1, and thus device fail. Will cause.

In particular, such a bit line contact CD loss is very serious when BPSG, PSG, etc., which have a relatively high oxide etch rate, are used as the interlayer dielectric.

Accordingly, the present invention has been made to solve the above problems, and can prevent bit line contact CD loss from wet cleaning using BOE after bit line contact etching and before Ti / TiN barrier film deposition. It is an object of the present invention to provide a method for forming a bit line of a semiconductor device.

In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film made of BPSG on the semiconductor substrate on which the landing plug is formed; Etching the interlayer insulating film to form a bit line contact exposing a landing plug; Performing a wet clean to remove polymer residues in the bitline contacts; Performing a wet cleaning again to remove the native oxide film on the bottom of the bit line contact; Sequentially depositing a barrier film and a bit line metal film on the bit line contact and the interlayer insulating film; And patterning the metal film and the barrier film for the bit line, wherein the wet cleaning after the bit line contact etching and before the barrier film deposition is performed by HF and NH4F, respectively. It provides a method for forming a bit line of a semiconductor device, characterized in that performed using a BOE solution containing 0.10wt% and 39-41wt%.

Here, the wet cleaning is performed using a mixture of a piranha solution (H2SO4: H2O2 = 4: 1) or an SC-1 solution (NH4OH: H2O2: H2O = 1: 1: 5) mixed with a BOE solution. can do.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention is as follows.

The present invention by adjusting the content of the HF solution and NH4F solution constituting the BOE solution, more precisely, by increasing the content of the NH4F solution than that of the conventional, it becomes a standard for removing the natural oxide film compared to the conventional BOE solution While maintaining the etching rate of the oxide film, the etching rate of the doped oxide films such as BPSG and PSG, which are mainly used as the interlayer insulating film, is reduced, thereby minimizing the bit line contact CD loss due to the etching of the BPSG interlayer insulating film during wet cleaning. As a result, the generation of bridges between bit lines contacts is suppressed.

Table 1 below shows the composition of the conventional BOE solution according to the present invention.

HF NH4F Conventional BOE 0.06wt% 17wt% Invention BOE 0.09wt% 40wt%

Referring to Table 1, the BOE solution of the present invention hardly changes the HF content from 0.06 wt% to 0.08 to 0.10 wt%, precisely 0.09 wt%, but the content of NH4F is 39 to 17 wt%. Increase to ˜41 wt%, precisely 40 wt%.

Table 2 below shows the oxide film etch rate characteristics of the conventional BOE solution according to the present invention.

Conventional BOE Invention BOE Thermal Oxide Etch Rate 0.24 0.34 BPSG Etch Rate 1.67 0.77 Etch Speed Selection Ratio 7 2.3

Referring to Table 2, it can be seen that the BOE solution of the present invention is about three times improved in the etch rate selectivity of the BPSG film to the thermal oxide film compared to the conventional one from 7 to 2.3.

Therefore, in the case of using the above-described BOE solution of the present invention, the loss of the bitline contact CD is reduced to that of the conventional wet etching after etching the interlayer insulating film for forming the bitline contact and before the Ti / TiN barrier film deposition. It can be reduced to less than half.

Table 3 below shows the degree of bit line contact CD loss by the BOE solution according to the conventional and the present invention in the actual device.

washing Average CD (nm) CD loss (nm) Oxide material Conventional BOE 40 seconds Before cleaning 114.8 15.3 BPSG After cleaning 130.1 Invention BOE 40 seconds Before cleaning 118.7 7.5 After cleaning 126.2

Referring to Table 3 above, in the device using BPSG as the interlayer insulating film, the BOE solution of the present invention is used for wet cleaning before the bitline barrier film deposition, and thus the bitline contact CD loss is reduced by 50% compared with the case of using the conventional BOE solution. It can be seen that the degree is reduced.

In conclusion, the present invention can improve the etch rate selection ratio of the BPSG film and the thermal oxide film from the conventional 7: 1 to 2.3: 1 by increasing the composition ratio of NH4F in the BOE solution consisting of HF and NH4F. Accordingly, the bit line contact CD loss can be halved during the wet cleaning using the BOE after the bit line contact etching and before the bit line barrier film deposition, and thus, the bit line as the bit line contact CD grows in size. It is possible to prevent the occurrence of bridges between contacts.

Hereinafter, a method of forming a bit line according to the present invention will be described with reference to FIGS. 2A to 2C.

Referring to FIG. 2A, the junction region 25 and the gate 23 having the spacers 24 are formed on a semiconductor substrate 21 having the device isolation film 22 by a known process. Then, a first interlayer insulating film 26 is deposited on the entire surface of the substrate to cover the gate 23.

Next, the first interlayer insulating layer 26 is etched to form a landing plug contact that simultaneously exposes a plurality of gates 23 and a junction region between the gates 23. Then, after depositing a polysilicon film to fill the landing plug contact, the polysilicon film is chemically mechanical polished (CMP) until the gate 23 is exposed, and the substrate bonding region 25 between the gates 23 is formed. The landing plug 27 is formed on it.

Next, a second interlayer insulating film 28 made of, for example, BPSG, is deposited on the first interlayer insulating film 26 including the landing plug 27.

Referring to FIG. 2B, the second interlayer dielectric layer 28 is etched to form a bit line contact 29 exposing the landing plug 27 to be contacted with a bit line formed subsequently. Thereafter, a wet cleaning of the substrate result is performed to remove polymer residues and the like in the bitline contacts 29.

Here, the wet cleaning is performed using the new composition as described above, that is, the BOE solution in which the NH4F content in the BOE solution in which HF and NH4F are mixed is increased from about 17 wt% to about 40 wt%. At this time, since the BOE solution of the new composition has an etching rate selectivity ratio of about 2.3: 1 for the BPSG film and the thermal oxide film, the loss of the bit line contact CD is extremely insignificant.

Referring to FIG. 2C, the substrate resultant is again wet-washed using a BOE solution to remove the native oxide film generated on the bottom of the bit line contact. In this case, as described above, the BOE solution of the present invention has an etching selectivity ratio of about 2.3: 1 for the BPSG film and the thermal oxide film, so that the loss of the bit line contact CD is not large.

Next, after depositing the Ti / TiN barrier film 30 on the bit line contact and the second interlayer insulating film 28, the tungsten film on the Ti / TiN barrier film 30 to completely fill the bit line contact. (31) is deposited. Then, the tungsten film 31 and the Ti / TiN barrier film 30 are etched to form a tungsten bit line 32.

As described above, the present invention can reduce the loss of the bitline contact CD to a half level by using a BOE solution having a high NH4F composition ratio during the wet cleaning after the bitline contact etching and before the barrier film deposition. As a result, the occurrence of bridges between bit line contacts can be prevented, so that device failing can be prevented, so that the device manufacturing yield can be improved.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1 is a photograph for explaining the conventional problem.

2A to 2C are cross-sectional views of processes for explaining a method of forming a bit line according to the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: gate 24: spacer

25 junction area 26 first interlayer insulating film

27 landing plug 28: second interlayer insulating film

29: bit line contact 30: Ti / TiN barrier film

31 tungsten film 32 bit line

Claims (2)

Forming an interlayer insulating film made of BPSG on the semiconductor substrate on which the landing plug is formed; Etching the interlayer insulating film to form a bit line contact exposing a landing plug; Performing a wet clean to remove polymer residues in the bitline contacts; Performing a wet cleaning again to remove the native oxide film on the bottom of the bit line contact; Sequentially depositing a barrier film and a bit line metal film on the bit line contact and the interlayer insulating film; And patterning the bit line metal film and the barrier film, wherein the bit line forming method of the semiconductor device comprises: The wet cleaning after the bit line contact etching and before the barrier film deposition is performed using a BOE solution containing H8 and NH4F of 0.08 to 0.10 wt% and 39 to 41 wt%, respectively. Line formation method. The method of claim 1, wherein the wet cleaning is performed by using a mixed solution of a POE solution (H2SO4: H2O2 = 4: 1) or an SC-1 solution (NH4OH: H2O2: H2O = 1: 1: 5). Bit line forming method of a semiconductor device, characterized in that performed.