KR100501980B1 - Plasma Display Panel Set - Google Patents

Abstract

The present invention relates to a plasma display panel set capable of reducing thickness.

The present invention provides a plasma display panel including scan electrode lines, sustain electrode lines, and data electrode lines; A plasma display panel module including a scan driver board for driving the scan electrode lines in a reset period and an address period and a data driver board for driving the data electrode lines and connected to a rear surface of the plasma display panel; An external driver including a first sustainer board for driving the scan electrode lines in the sustain period outside the plasma display panel module and a second sustainer board for driving the sustain electrode lines in the sustain period; And an interface for relaying between the plasma display panel module and the external driver.

Description

Plasma Display Panel Set {Plasma Display Panel Set}

The present invention relates to a set of plasma display panels, and more particularly to a set of plasma display panels capable of reducing thickness.

Recently, plasma display panels (hereinafter referred to as PDPs), which are easy to manufacture large panels, have attracted attention as flat panel display devices. PDPs typically display an image by adjusting the discharge period of each pixel in accordance with digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 shows a discharge cell of one of the alternating current PDPs.

The discharge cell 30 shown in FIG. 1 includes an upper plate having sustain electrode pairs 12A and 12B, an upper dielectric layer 14 and a protective film 16 sequentially formed on the upper substrate 10, and a lower substrate 18. A lower plate having a data electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed thereon is provided.

Each of the sustain electrode pairs 12A and 12B is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 12A and 12B are separated into the scan electrode 12A and the sustain electrode 12B. The scan electrode 12A mainly supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12B mainly supplies a sustain signal. The data electrode 20 is formed to cross the sustain electrode pairs 12A and 12B. This data electrode 20 supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside.

The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the data electrode 20 to prevent ultraviolet rays generated by the discharge from leaking into adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 having such a structure is selected as the counter discharge between the data electrode 20 and the scan electrode 12A, and then maintains the discharge by the surface discharge between the sustain electrode pairs 12A and 12B. In such discharge cells, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

FIG. 2 shows the overall electrode arrangement structure of the PDP including the discharge cells 30 shown in FIG. In FIG. 2, the discharge cells 30 are configured at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the data electrode lines X1 to Xn.

The scan electrode lines Y1 to Ym supply the scan pulses and the sustain pulses so that the discharge cells 30 are scanned in units of lines, and the discharges are sustained in the discharge cells 30. The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to sustain the discharge in the discharge cells 30 together with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn supply data pulses synchronized with the scan pulse in line units so that the discharge cells 30 are selected according to the logic value of the data pulses.

A color of one pixel is realized by combining three discharge cells coated with R, G, and B phosphors 26, respectively.

As a method of driving such a PDP, an ADS (Address and Display Separation) driving method that is driven by being divided into an address period and a display period, that is, a sustain period is typical. The ADS driving method divides one frame 1F into a plurality of subfields SF1 to SFi corresponding to each bit of video data. Each of the subfields SF1 to SFi is further divided into a reset period for initializing a radiation cell, an address period for selecting a discharge cell, and a sustain period for discharging sustain of the selected discharge cell. Here, the PDP implements the corresponding gradation by assigning different weights to the subfields SF1 to SFi in the sustain period, and combining the sustain period for maintaining the discharge according to the video data.

3 illustrates a configuration of driving circuit boards installed on a rear surface of a conventional PDP module.

The PDP module shown in FIG. 3 includes a PDP 40 for displaying an image, a heat sink 64 for dissipating heat from the PDP 40 provided at the rear side of the PDP 40, and a heat sink 64. It includes a plurality of driving circuit boards installed on the back side of the.

The plurality of driving circuit boards include a Y driving board 45 for driving the scan electrode lines of the PDP 40, a Z sustainer board 48 for driving the sustain electrode lines Z1 to Zm, and a data electrode. A data driver board 50 for driving lines, a control board 42 for controlling the Y drive board 45 and a Z sustainer board 48 and a data driver board 50, and the circuit boards And a power board 66 for supplying power to each of 42, 45, 48, and 50.

The Y drive board 45 includes a scan driver board 44 and a Y sustainer board 46. The scan driver board 44 generates a reset pulse in the reset period, and generates a scan pulse in the address period to scan the scan electrode lines Y1 of the PDP 40 through an output bus (Oy) such as a flexible printed circuit (FPC). To Ym). The Y sustainer board 46 generates a Y sustain pulse in the sustain period and supplies it to the scan electrode lines Y1 to Ym through the scan driver board 44 and the output bus Oy.

The Z sustain board 48 generates Z sustain pulses in the sustain period and supplies them to the sustain electrode lines Z1 to Zm of the PDP 40 through an output bus Oy such as FPC.

The data driver board 50 generates data pulses in the address period and supplies the data pulses to the data electrode lines X1 to Xn of the PDP 40 through an output bus (Oy) such as an FPC.

The control board 42 generates each of the X, Y, and Z timing control signals, transmits the Y timing control signal to the Y driving board 45 through the first control bus C1, and transmits the Z timing control signal to the second control. The Z sustainer board 48 is supplied through the bus C2 and the X timing control signal is supplied to the data driver board 50 through the third control bus C3.

The power board 66 is connected to each of the Y driving board 45, the Z sustainer board 48, the data driver board 50 and the control board 42 through each of the first to fourth power buses P1 to P4. Supply the required drive voltage.

As such, a plurality of circuit boards of the conventional PDP module are all disposed on the rear surface of the PDP 40. Due to this, the configuration of the circuit boards is complicated and there is a limit in reducing the thickness of the PDP module. This is because the thickness of the PDP module depends on the circuit board components. For example, as the size of components of the Y and Z sustainer boards 46 and 48 and the power board 66 among the plurality of circuit boards is relatively large, there is a limit in reducing the thickness of the PDP module.

Accordingly, an object of the present invention is to provide a plasma display panel capable of reducing thickness by separating some driving circuits from a plasma display panel module including driving circuits for driving the plasma display panel.

In order to achieve the above object, the PDP set according to the present invention comprises a plasma display panel having scan electrode lines and sustain electrode lines and data electrode lines; A plasma display panel module including a scan driver board for driving the scan electrode lines in a reset period and an address period and a data driver board for driving the data electrode lines and connected to a rear surface of the plasma display panel; An external driver including a first sustainer board for driving the scan electrode lines in the sustain period outside the plasma display panel module and a second sustainer board for driving the sustain electrode lines in the sustain period; And an interface for relaying between the plasma display panel module and the external driver. The plasma display panel module controls the scan driver board, the data driver board, and the first and second sustainer boards. The external driving unit may further include a power board for supplying a driving voltage to the first and second sustainer boards and the module of the plasma display panel. The plasma display panel module may further include a sustain interface for relaying a driving signal supplied from the second sustainer board to the sustain electrode lines. The interface may include the plasma display from the power board. panel Power bus group comprising a plurality of power bus for transmitting a drive voltage to be supplied to; Control buses for transmitting control signals for controlling the external driver from the control board, and drive signal transmission buses for transmitting drive signals for supplying the plasma display panel module from each of the first and second sustainers. And an external driving unit embedded in a pedestal for supporting the plasma display panel module, and the interface is embedded in a stand between the plasma display panel module and the pedestal. The external driving unit may be installed in a wall-mounted form together with the plasma display panel module. Other objects and advantages of the present invention in addition to the above object are described with reference to the accompanying drawings. And obviously it will be revealed.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9.

4 illustrates a configuration of a PDP set according to an embodiment of the present invention.

The PDP set shown in FIG. 4 includes a PDP 70, a heat sink 80 provided on the back of the PDP 70, a scan driver board 74, Z interface 76, and data provided on the back of the heat sink 80. A PDP module including a driver board 78, a control board 72, a power board 96 separated from the PDP module, and an external driver 90 including Y and Z sustainer boards 92 and 94; do.

The PDP 70 has a structure in which the upper plate and the lower plate are joined while providing a gas discharge space. For example, scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm are formed in parallel on the upper plate of the PDP 70, and data electrode lines X1 to Xn on the lower plate. ) Is formed.

The heat sink 80 is installed to overlap the entire back surface of the PDP 70 so that heat from the PDP 70 can be easily discharged to the outside.

The control board 72 generates each of the X, Y, and Z timing control signals. The control board 72 transmits the first Y timing control signal to the scan driver board 74 through the first control bus C1 and the second Y timing control signal to the outside through the second control bus C2. With the Y sustainer board 92 separated, the Z timing control signal to the Z sustainer board 94 separated externally via the third control bus C3, and the X timing control signal with the fourth control bus C4. Supply to the data driver board 78 through.

The scan driver board 74 generates a reset pulse in the reset period and a scan pulse in the address period in response to the first Y timing control signal from the control board 72 to output the PDP (PDP) through an output bus (Oy) such as FPC. 70 to the scan electrode lines Y1 to Ym.

The data driver board 78 generates data pulses in the address period in response to the X timing control signal from the control board 78 to output the data electrode lines X1 of the PDP 70 through an output bus Ox such as an FPC. To Xn).

The Z interface 76 supplies the drive signal supplied from the external Z sustainer board 94 to the sustain electrode lines Z1 to Zm of the PDP 70 through an output bus Oz such as an FPC.

The Y sustainer board 92 generates a Y sustain pulse in the sustain period in response to the second Y timing control signal from the control board 72. The Y sustainer board 92 transmits the generated Y sustain pulses to the scan electrode lines Y1 to PDP 70 through the transfer bus Ty-> scan driver board 74-> output bus Oy. Ym).

The Z sustainer board 94 generates Z sustain pulses in the sustain period in response to the Z timing control signal from the control board 72. Then, the Z sustainer board 92 transmits the generated Z sustain pulses to the sustain electrode lines Z1 to PDP 70 via the transmission bus Tz-> Z interface 76-> output bus Oz. Zm).

The power board 96 is connected to the Y sustainer board 92, the Z sustainer board 94, the scan driver board 74, and the data driver board 78 through each of the first to fifth power buses P1 to P5. ), The driving voltage required for each of the control boards 72 is supplied.

As described above, in the PDP set according to the present invention, the Y and Z sustainer boards 92 and 94 supply the Y and Z sustain pulses which are the most important in driving the PDP 70 as well as occupy a large proportion compared to other circuit boards. ) And a power board 96 for supplying the driving voltages required for all circuit boards on the external driver 90 separated from the PDP module. Accordingly, it is possible to reduce the thickness and weight of the PDP module due to the Y and Z sustainer boards 92 and 94 and the power board 96.

For example, the PDP set according to the embodiment of the present invention is designed as a stand type having a PDP module 100 and the PDP module 100 having a stand 102 and a pedestal 104 as shown in FIG. 5.

In FIG. 5, the PDP module 100 includes a PDP 70, a heat sink 80, a control board 72, a scan driver board 74, a Z interface 76, a data driver board 78, and the like shown in FIG. 4. It includes.

The pedestal 104 includes an external drive unit 90 having a Y sustainer board 92, a Z sustainer board 94, and a power supply board 96 shown in FIG. Since the pedestal 104 includes relatively heavy circuit components, the weight of the pedestal module 100 decreases instead of the weight of the pedestal 104 increases, so that the pedestal 104 can be more stably supported. do. Generally, the pedestal 104 is intentionally made very heavy to support the PDP module 100 of about 30 kg. In the present invention, the heavy circuit components are built to naturally meet the purpose of the pedestal 104. . Accordingly, the PDP set of the present invention can maintain a more stable posture.

The stand 102 supports the PDP module 100 and also serves as an interface between the PDP module 100 and the pedestal 104. To this end, the stand 102 has a built-in power bus group 120 for transmitting a power signal, and a control bus group 122 for transmitting a control signal and the like as shown in FIG. As the power bus group 120 and the control bus group 122, a PCB or a good conductor is used.

Here, the power bus group 120 includes third to third power supplies for supplying driving voltages to the scan driver board 74, the data driver board 78, and the control board 72 from the power board 96 as shown in FIG. 4. 5 power buses P3 to P5.

The control bus group 122 is configured to supply a second Y control signal and a Z control signal from the control board 72 to the Y sustainer board 92 and the Z sustainer board 94 as shown in FIG. 4. 3 control buses C2 and C3, a transfer bus Ty for supplying Y sustain pulses from the Y sustainer board 92 to the scan driver board 74, and a Z interface 76 from the Z sustainer board 94. ) Includes a transmission bus (Tz) that supplies a Z sustain pulse.

The cover 124 of the stand 102 that surrounds the power bus group 120 and the control bus group 122 to secure the insulation and stability between them is made of an insulating material.

7 illustrates a wall-mounted PDP set according to an embodiment of the present invention, wherein the wall-mounted PDP set includes a PDP module 110, an external drive module 114, a PDP module 110, and an external drive module ( 114 has an interface 112 between them.

The PDP module 110 includes a PDP 70, a heat sink 80, a control board 72, a scan driver board 74, a Z interface 76, a data driver board 78, and the like illustrated in FIG. 4. .

The external drive module 114 includes an external drive unit 90 having a Y sustainer board 92, a Z sustainer board 94, and a power supply board 96 shown in FIG. As the external drive module 114 includes relatively heavy circuit components, the thickness and weight of the PDP module 100 are reduced, thereby facilitating the installation of the wall-mounted PDP set. Here, the external drive module 114 is installed on the wall together with the PDP module 110 as shown in FIG. 7 together with the interface 112, or can be moved and installed for convenience.

The interface 114 includes a power bus group 120 that transmits power signals as shown in FIG. 6, and a control bus group 122 that transmits control signals and the like. As the power bus group 120 and the control bus group 122, a PCB or a good conductor is used. Here, detailed configurations of the power bus group 120 and the control bus group 122 are as described above, and the cover 124 is made of an insulating material for insulation between the buses.

FIG. 8 shows a detailed circuit configuration of the Y driver separated into a scan driver board 74 in the PDP module shown in FIG. 4 and a Y sustainer board 92 in the external driver 90.

The Y driver shown in FIG. 8 is an output buffer unit 79, an energy recovery circuit 94, a set-up voltage supply unit 73, and a set-down in which the output buffer unit 79 and an output terminal are commonly connected. (Set-down) connected between the voltage supply unit 73, the scan reference voltage supply unit 75, the scan voltage supply unit 77, and the energy recovery circuit 93, the setup supply unit 71 and the output buffer unit 79 A second switch Q2 and a third switch Q3 connected between the energy recovery circuit 93 and the second switch Q2 are provided.

In such a Y drive section, an energy recovery circuit 94 is provided in the Y sustainer board 94 in the external drive section 90 shown in FIG. The setup voltage supply unit 71, the set-down voltage supply unit 73, the scan reference voltage supply unit 75, the scan voltage supply unit 77, the output buffer unit 79, the second and third switches Q2 and Q3 It is installed in the scan driver board 74 in the PDP module shown in FIG.

The output buffer unit 79 scans output signals of the energy recovery circuit 93, the setup voltage supply unit 71, the set-down voltage supply unit 73, the scan reference voltage supply unit 75, and the scan voltage supply unit 77. Eighth and ninth switches (Q8, Q9) for selectively outputting to any one of the scan line.

The energy recovery circuit 40 supplies a sustain pulse to its output node in the reset period and the sustain period. To this end, the energy recovery circuit 40 includes a source capacitor Cex, a tenth switch Q10 connected between an output node and a sustain voltage Vs supply line, and an output node and a ground voltage GND supply line. A twelfth switch connected in parallel between the eleventh switch Q11 connected to the source capacitor Cex, the inductor L connected in series between the source capacitor Cex, and the output node, and the source capacitor Cex and the inductor L; Thirteenth switches Q12 and Q13 are provided. In addition, the energy recovery circuit 40 includes second and third diodes D2 and D3 for preventing a reverse current formed between the twelfth and thirteenth switches Q12 and Q13 and the inductor L, respectively. The energy recovery circuit 40 has an output buffer unit 79-> second switch Q2-> third switch Q3-> inductor L-> third diode D3-> from the scan electrode line. The voltage recovered through the thirteenth switch Q13 is charged to the source capacitor Cex. The voltage discharged from the source capacitor Cex is converted into the twelfth switch Q12-> the second diode D2-> the inductor L-> the third switch Q3-> the second switch Q2-> After supplying to the sustain electrode line via the output buffer unit 79, the sustain voltage Vs supplied from the outside via the tenth switch Q10 is transferred from the third switch Q3 to the second switch Q2. Supply to the scan electrode line through the output buffer unit (79). Accordingly, excessive power consumption through the scan electrode lines in the setup period and the sustain period of the reset period is reduced.

The setup voltage supply unit 71 includes a first diode D1 and a first switch Q1 connected between the reference setup voltage Vr supply line and the second switch Q2, and a first diode D1 and a first diode. A first capacitor C1 connected between the node between the switches Q1 and the output terminal of the energy recovery circuit 40 is provided. Here, the first diode D1 blocks the reverse current flowing from the first capacitor C1 toward the reference setup voltage Vr supply line. The first capacitor C2 adds the base setup voltage Vr to the sustain voltage Vs supplied from the energy recovery circuit 93, and supplies it to the first switch Q1. The first switch Q1 gradually increases from the sustain voltage Vs to the sum of the sustain voltage Vs and the base setup voltage Vr (Vs + Vr) in the setup period during the reset period of the selective write subfield. Outputs This setup voltage is supplied to the scan electrode line through the second switch Q2 and the output buffer unit 79.

The setdown voltage supply 73 has a fourth switch Q4 connected between the output buffer 79 and the reference setdown voltage (-Vy) supply line. The setdown voltage supply unit 73 outputs a setdown voltage that gradually decreases from the sustain voltage Vs to the reference setdown voltage −Vy during the setdown period during the reset period of the selective write subfield. The set down voltage is supplied to the scan electrode line through the output buffer unit 79.

The scan reference voltage supply unit 75 includes fifth and sixth switches Q5 and Q6 connected in series between the scan reference voltage Vsc supply line and the output buffer unit 79, and the fifth and sixth switches Q5. And a second capacitor C2 connected in parallel with Q6). The fifth and sixth switches Q5 and Q6 output the scan reference voltage Vsc in the address period to be supplied to the scan electrode line through the output buffer unit 79. The second capacitor C2 adds the scan reference voltage Vsc to the voltage of the node between the fourth and sixth switches Q4 and Q6 to be supplied to the fifth switch Q5.

The scan voltage supply 77 has a seventh switch Q7 connected between the output buffer 79 and the scan voltage (-Vy) supply line. The seventh switch Q7 outputs a scan voltage -Vy in units of one horizontal period in the address period to be supplied to the scan electrode line through the output buffer unit 79.

As described above, the PDP set according to the present invention reduces the thickness and weight of the PDP module by installing Y and Z sustainer boards, which occupy relatively large weights, and a power supply board in an external drive separate from the PDP module. It becomes possible.

Accordingly, when the PDP set according to the present invention is implemented in a stand type, the thickness and weight of the PDP module may be reduced, and the weight of the pedestal supporting the PDP module may be increased by the built-in external drive unit to maintain a stable posture.

In addition, when the PDP set according to the present invention is implemented as a wall-mounted type, it is easy to install the PDP module on the wall by reducing the thickness and weight of the PDP module, and the separated external drive unit is also easily installed by the wall-type type with the PDP module. You lose.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell of a typical three-electrode alternating current PDP.

2 is an overall electrode layout of a typical PDP.

3 is a diagram illustrating a circuit board configuration of a conventional PDP module.

4 is a diagram illustrating a circuit board configuration of a PDP module according to an exemplary embodiment of the present invention.

FIG. 5 is a view showing the appearance of a PDP set to which the circuit board shown in FIG. 4 is applied.

FIG. 6 is a view schematically showing an internal configuration of the stand shown in FIG. 5; FIG.

FIG. 7 is a view showing another appearance of the PDP set to which the circuit board shown in FIG. 4 is applied.

FIG. 8 is a diagram showing a detailed circuit configuration of the scan driver board and the Y sustainer board shown in FIG. 4; FIG.

<Brief description of symbols for the main parts of the drawings>

10: upper substrate 18: lower substrate

12A: Scanning electrode 12B: Sustaining electrode

14 upper dielectric layer 16 protective film

20: data electrode 22: lower dielectric layer

24: partition 26: phosphor

30: discharge cell 40, 70: PDP

42, 72: control board 44, 74: scan driver board

45: Y drive board 46, 92: Y sustainer board

48, 94: Z sustainer board 50, 78: data driver board

64, 80: heat sink 66, 96: power board

76: Z interface board 100, 110: PDP module

102: stand 104: stand

120: power bus group 122: control bus group

124: cover 112: interface

114: external drive module

Claims (7)

A plasma display panel including scan electrode lines, sustain electrode lines, and data electrode lines; A plasma display panel module including a scan driver board for driving the scan electrode lines in a reset period and an address period and a data driver board for driving the data electrode lines and connected to a rear surface of the plasma display panel; An external driver including a first sustainer board for driving the scan electrode lines in the sustain period outside the plasma display panel module and a second sustainer board for driving the sustain electrode lines in the sustain period; And an interface for relaying between the plasma display panel module and the external driver. The method of claim 1, The plasma display panel module, And a control board for controlling the scan driver board, the data driver board, and the first and second sustainer boards. The method of claim 1, The external drive unit, And a power board for supplying a driving voltage to the first and second sustainer boards and the module of the plasma display panel. The method of claim 1, The plasma display panel module, And a sustain interface for relaying a driving signal supplied from the second sustainer board to the sustain electrode lines. The method of claim 3, wherein The interface is, A power bus group including a plurality of power buses for transmitting driving voltages supplied from the power board to the plasma display panel; Control buses for transmitting control signals for controlling the external driver from the control board, and drive signal transmission buses for transmitting drive signals for supplying the plasma display panel module from each of the first and second sustainers. And a control bus group including the plasma display panel set. The method of claim 1, The external driver is built in a pedestal for supporting the plasma display panel module, And the interface is embedded in a stand between the plasma display panel module and the pedestal. The method of claim 1, And the external driving unit is mounted on the wall together with the plasma display panel module.