KR100498604B1 - Method for forming charge storage electrode of semiconductor device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs.

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention.

It is an object of the present invention to provide a method of forming a charge storage electrode of a capacitor capable of increasing the area of an electron storage electrode even in a process without using a sacrificial film when forming a charge storage electrode of a semiconductor device.

3. Summary of the solution of the invention.

When forming the charge storage electrode of the capacitor, the polysilicon film is laminated, and trenches are appropriately formed in the preformed polysilicon film and the interlayer insulating film, so that the capacitance as much as the polysilicon pillar protruding on the interlayer insulating film and the surface level of the trench in the interlayer insulating film are obtained. Reduce It also improves device yield by preventing surface damage of exposed charge storage electrodes.

4. Intended use of the invention.

Used in capacitor manufacturing process in semiconductor device manufacturing process.

Description

Method for forming charge storage electrode of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a charge storage electrode of a semiconductor device for improving the capacity of the capacitor by improving the method of forming a charge storage electrode of the capacitor.

In accordance with the current trend, as semiconductor devices become highly integrated in manufacturing integrated circuits, there are various problems in the semiconductor device manufacturing process. For example, it is difficult to secure a capacity of a capacitor proportional to the area of the charge storage electrode.

As a solution to this problem, the first three-dimensional cell structure is to arrange transistors and capacitors in space to secure enough area and spacing of each device compared to the planar structure. Second, instead of the ONO film used as the dielectric of the capacitor, a dielectric having a larger dielectric constant, for example, an oxide film and a nitride film, TiO ₂ or Ta ₂ O ₅ , can be used to secure the capacitor capacity.

1A to 1D are cross-sectional views illustrating a method of forming a charge storage electrode of a capacitor according to the prior art, and FIG. 2 is a process diagram illustrating a step of a semiconductor device having a capacitor according to the prior art. Here, the symbol "A" is a step between the peripheral circuit region and the cell region, which is induced by the capacitor formation.

First, as shown in FIG. 1A, an interlayer insulating film 11 for insulating the elements is formed on a silicon substrate (not shown) having a lower layer where a predetermined process is completed. A contact hole is formed by an etching process using a contact hole mask, and an oxide film spacer 12 is formed on the side of the contact hole. Then, the first polysilicon layer 13 'for the charge storage electrode is formed on the entire structure. The thickness of this first polysilicon layer 13 'is 1000 mW.

Next, as shown in FIG. 1B, for example, a phosphorous layer (PSG) 14 is formed of a material having a selective etching ratio with the polysilicon layer 13 ′ on the entire structure, and the first charge is stored. The phosphor glass layer 14 and the first polysilicon layer 13 are etched using the electrode mask. Here, the phosphorus layer 14 is used as a sacrificial film.

Next, as shown in FIG. 1C, a second polysilicon layer 15 for forming a cylindrical capacitor charge storage electrode is formed at about 1500 kPa at a process temperature of about 580 ° C.

Finally, as shown in FIG. 1D, the second polysilicon layer 15 formed on the entire structure is anisotropically dry-etched to form the in-glass layer 14 and the vertical structure side surfaces of the first polysilicon layer 13. The spacer 15 is formed in the groove. Then, the in-glass layer 14 used as the sacrificial film is selectively wet removed to form the charge storage electrode of the cylindrical capacitor. Next, a dielectric layer and a plate electrode are formed to complete the capacitor.

However, as described above, the pattern size in the chip is unstable due to the sacrificial film in-glass layer 14 used to form the cylindrical sidewall, and the collision between the patterns due to the coupling between the in-glass layer 14 and the photoresist pattern. This is caused. In addition, when the in-glass layer 14 is removed, the surface of the lower charge storage electrode is damaged, which causes a problem of reducing the capacitor capacity.

In order to solve the above problems, the present invention provides a method of forming a charge storage electrode of a semiconductor device capable of increasing the area of the electron storage electrode by a process not using a sacrificial film when forming the charge storage electrode of the semiconductor device. To provide that purpose.

In order to achieve the above object, a method of forming a charge storage electrode of a semiconductor device according to the present invention includes: a first step of forming a contact hole by selectively etching an interlayer insulating layer on an upper surface of a substrate; A second step of forming a first conductive film filling the contact hole on the entire structure; Forming a first etching mask pattern for opening the first conductive film in the region including the contact hole with a first line width; Etching the first conductive layer using the first etching mask pattern and etching the interlayer insulating layer to a predetermined depth to form a trench; A fifth step of forming a second conductive film on a surface of the resultant product of which the fourth step is completed; A sixth step of forming a second etching mask pattern covering an upper portion of the region including the trench with a second line width greater than the first line width; And a seventh step of etching the second conductive film and the first conductive film by using the second etching mask pattern.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3G are cross-sectional views illustrating a method of forming a charge storage electrode of a capacitor according to an exemplary embodiment of the present invention, in which a process of omitting a process of forming a gate conductive film on a silicon substrate is omitted. A pattern for forming a charge storage electrode of a capacitor according to an embodiment.

First, as shown in FIG. 3A, a bit line 32 is formed on the interlayer insulating film 31 having a predetermined process completed, and an oxide film 33 is deposited thereon.

Next, as shown in FIG. 3B, the photoresist pattern 301 is formed on the upper portion of the etching mask pattern for the capacitor charge storage electrode, and the oxide film 33 and the interlayer insulating film 31 are selectively etched to form a silicon substrate ( (Not shown) forms a contact hole that is exposed.

Next, as shown in FIG. 3C, the first polysilicon film 34 is formed after the removal of the photoresist pattern 301. The first polysilicon film 34 is formed on the oxide film 33 at least about 5000 kV.

Next, as shown in FIG. 3D, a photoresist 302 pattern is formed on the entire structure to open the first polysilicon film 34 overlapping the contact hole region. The open region of the first polysilicon film 34 opened by the photoresist pattern 302 may be defined as "401" in FIG.

Next, as shown in FIG. 3E, the exposed polysilicon film 34 is removed by using the preformed photoresist 302 pattern as an etch barrier to set the etching target to 9000 Å, and then the oxide film 33 is about 4000 Å. ) Is partially etched to form trenches. The 3000 산화 oxide film 33 remaining here can play a sufficient role as the insulating film of the bit line 32.

Next, as shown in FIG. 3F, the residual photoresist pattern 302 is removed, and a doped second polysilicon film 35 is formed on the entire surface of about 1000 mW. After the photoresist is applied thereon, the photoresist pattern 303 overlapping the trench region formed by the above-described etching process is formed. In this case, the photoresist pattern 303 formed may be defined as “402” of FIG. 4.

Finally, as shown in Fig. 3G, the 1000 도 doped polysilicon film 35 is etched using the preformed photoresist pattern 303 as an etch barrier, followed by the 5000 Å first polysilicon film 34. Is etched to expose the oxide film 33. The residual photoresist pattern 303 is removed to expose the doped second polysilicon layer 35 to form a charge storage electrode having no damage to the surface.

The present invention, which proceeds to the above-described process, does not use the sacrificial oxide film used to form the conventional cylindrical charge storage electrode, resulting in surface damage of the charge storage electrode generated when the sacrificial oxide film is removed. It is possible to form a charge storage electrode having an increased surface area.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention, the polysilicon film is laminated when the charge storage electrode of the capacitor is formed, the trench is formed appropriately in the preformed polysilicon film and the interlayer insulating film, and the capacitance and the interlayer are as large as the polysilicon pillars protruding on the interlayer insulating film. The surface level difference by the trench in the insulating film is reduced. It also improves device yield by preventing surface damage of exposed charge storage electrodes.

1A to 1D are cross-sectional views illustrating a method of forming a charge storage electrode of a capacitor according to the prior art.

2 is a process chart showing a step of a semiconductor device having a capacitor according to the prior art.

3A to 3G are cross-sectional views illustrating a method of forming a charge storage electrode of a capacitor according to an embodiment of the present invention.

4 is a pattern for forming a charge storage electrode of a capacitor according to an embodiment of the present invention.

* Brief description of the main parts of the drawing

31: interlayer insulating film having a lower layer

32: bit line

33: oxide film

34: first polysilicon film

35: second polysilicon film

301, 302, 303: photoresist pattern

Claims (5)

Forming a bit line on the interlayer insulating film; Forming an oxide film on the entire structure of the substrate on which the bit lines are formed; Forming a contact hole by selectively etching the oxide film and the interlayer insulating film; A fourth step of forming a first conductive film filling the contact hole on the entire structure; Forming a first etching mask pattern for opening the first conductive film in the region including the contact hole with a first line width; A sixth step of etching the first conductive layer using the first etching mask pattern and etching the oxide layer by a predetermined thickness to form a trench; A seventh step of forming a second conductive film on a surface of the resultant product in which the sixth step is completed; An eighth step of forming a second etching mask pattern covering an upper portion of the region including the trench with a second line width larger than the first line width; And A ninth step of etching the second conductive layer and the first conductive layer using the second etching mask pattern; Method for forming a charge storage electrode of a semiconductor device comprising a. The method of claim 1 After the oxide film is formed to a thickness of at least 7000 kPa in the second step, the oxide film of about 4000 kPa is etched in the sixth step. A method of forming a charge storage electrode of a semiconductor device, wherein the remaining 3000 산화 oxide film serves as an insulating film of the bit line. The method of claim 1, The charge storage electrode formation method of the semiconductor element whose said 1st and 2nd conductive films are a polysilicon film. The method of claim 3, A charge storage electrode forming method of a semiconductor device, wherein the first conductive film is 3000 Å to 7000 Å. The method of claim 3, The second conductive film is 500 Å to 2000 전하 charge storage electrode forming method of a semiconductor device.

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