KR100498011B1 - Transistor and its manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method of fabricating the same, wherein a drain electrode, a substrate positioned on the drain electrode, A drain region formed thereon, a main body formed on the drain region, a plurality of source regions partially formed on the main body, trenches having side and bottom surfaces formed at a predetermined depth in the plurality of source regions, the main body and the drain region, A gate oxide film having a side surface and a bottom surface to cover the trench, a poly silicon gate filled on a surface of the gate oxide film of the trench, an oxide film formed on the poly silicon gate, a source electrode connecting the plurality of sources; The termination region to connect the polysilicon gate Generated according to the common gate electrode consisting of a transistor, the polysilicon gate is referred to as being formed on a portion of the bottom surface of the side and the adjacent side of the gate oxide film and the gate oxide film of the gate oxide film.

Description

Transistor and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method of manufacturing the same, and more particularly, a trench type metal oxide semiconductor field effect capable of improving switching speed by minimizing capacitance between a polysilicon gate and a drain region. Transistor) and a method of manufacturing the same.

Referring to FIG. 1A, a partial plan view of a conventional transistor is shown. Referring to FIG. 1B, a cross-sectional view of the line aa of FIG. 1A is illustrated, and FIG. 1C is a cross-sectional view of the bb line of FIG. 1A. have.

As shown, a conventional transistor includes a drain electrode 10 ', an N + type substrate 20' positioned over the drain electrode 10 ', and an N- type drain region formed over the N + type substrate 20'. 30 ', a P-type body 40' formed on the N-type drain region 30 ', an N + -type source region 50' partially formed on the P-type body 40 ', and A trench 60 'formed at a predetermined depth in the source region 50', the main body 40 ', and the drain region 30', a gate oxide film 70 'covering the surface of the trench 60', A polysilicon gate 80 'filled on the surface of the gate oxide film 70' of the trench 60 ', an oxide film 90' formed on the polysilicon gate 80 ', and the plurality of source regions 50'. ) And a common gate electrode 110 'formed in the termination region 120' such that the polysilicon gate 80 'is connected to the source electrode 100'.

Such a conventional transistor can be roughly divided into an equilibrium state, an off state to which a drain-source voltage is applied, and an on state to which a drain-source voltage is applied. For example, if the gate-source voltage is greater than the transistor threshold voltage and the drain-source voltage is greater than 0V, it is on. That is, in this case, as the N-type channel is formed in the main body 40 'adjacent to the gate oxide film 70', the source region 50 'and the drain region 30' are conductive, whereby the transistor is operated.

On the other hand, in the conventional transistors, trenches are formed in a substantially rectangular groove shape in cross section, and a gate oxide film is formed along the wall surface of the trench, and the gate oxide film is in contact with a large area. That is, the polysilicon gate is formed in contact with the entire bottom surface of the trench and the gate oxide film formed on the side surface of the trench.

However, when the polysilicon gate is in contact with the entire gate oxide film as described above, the following problem occurs.

First, when power is applied to the gate electrode, the source electrode, and the drain electrode, a parasitic capacitance of a predetermined capacity is formed because a gate oxide layer, which is a dielectric, is formed between the polysilicon gate and the drain region, and the polysilicon gate and the source region (and the main body). There is a problem that occurs.

Secondly, in particular, the capacitance generated between the polysilicon gate and the drain region acts as a variable that significantly reduces the switching speed of the transistor, so that the transistor of this structure cannot be adopted in a high speed operation circuit.

Accordingly, the present invention has been made to solve the above-described conventional problems, MOSFET (Trench type Metal Oxide Semiconductor Field Effect) that can improve the switching speed by minimizing the capacitance (capacitance) between the polysilicon gate and drain region Transistor) and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a drain electrode, a substrate positioned on the drain electrode, a drain region formed on the substrate, a body formed on the drain region, a plurality of source regions partially formed on the body, A trench formed in the plurality of source regions, the main body, and the drain region to have a side and a bottom surface at a predetermined depth, a gate oxide film having a side and a bottom surface to cover the trench, and a gate oxide film surface of the trench. In a transistor comprising a polysilicon gate, an oxide film formed on the polysilicon gate, a source electrode connecting the plurality of sources, and a common gate electrode formed in an end region to connect the polysilicon gate, the polysilicon gate is Side of the gate oxide and the gate oxide And a portion of the bottom surface of the gate oxide film adjacent to the side surface of the film.

Here, a portion of the center of the bottom surface of the gate oxide film may be in direct contact with the oxide film.

In addition, the deposition thickness of the polysilicon gate is preferably about 2000 kPa to 5000 kPa.

In addition, in order to achieve the above object, the transistor manufacturing method according to the present invention forms a semiconductor drain region having a predetermined thickness on the semiconductor substrate through an epitaxial process, the trench having a constant depth having a side surface and a bottom surface Forming a gate oxide film having a predetermined thickness on side and bottom surfaces of the trench, and depositing a polysilicon gate having a predetermined thickness on the side and bottom surfaces of the trench, and then forming a bottom surface of the gate oxide film. Etching the polysilicon gate so that the central region is exposed to the outside, depositing an oxide layer to completely fill the trench, and etching the oxide layer outside the trench, and depositing the oxide layer outside the trench, and depositing the oxide layer outside the trench. The main body is formed by ion implantation of impurities of a concentration, and the concentration is again added to the main body. Implanting an impurity to form a source region, an oxide film is formed to completely cover an upper portion of the polysilicon, and the source region is exposed, and a source electrode and a drain to be connected to the source region, the substrate and the polysilicon gate. Forming an electrode and a gate electrode is characterized in that.

Here, it is preferable that the deposition thickness of the polysilicon gate is within about 2000 kPa to 5000 kPa.

As described above, in the transistor according to the present invention, the parasitic capacitance between the polysilicon gate and the drain region can be minimized by allowing the polysilicon gate to be formed only in a portion of the side and bottom surfaces of the gate oxide film.

In addition, by minimizing the parasitic capacitance as described above, it is possible to greatly improve the switching speed of the transistor can be usefully used in electronic circuits requiring high-speed operation.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

2, a cross-sectional view of a transistor according to the present invention is shown.

Here, not all the drawings of the transistors according to the present invention are accumulated at a constant rate, and although one transistor is shown in the sectional view, it is natural that tens to tens of thousands of such transistors may be formed in one semiconductor die. In addition, in the present invention, since the structure of the common gate electrode formed in the termination region is the same as in the related art (see FIG. 1C), the drawings and reference numerals thereof will be omitted.

First, as shown in FIG. 2, the transistor according to the present invention includes a drain electrode 10, a substrate 20 positioned on the drain electrode 10, a drain region 30 formed on the substrate 20, And a main body 40 formed on the drain region 30, a plurality of source regions 50 partially formed on the main body 40, the plurality of source regions 50, a main body 40 and a drain region ( A trench 60 having a side surface 61 and a bottom surface 62 at a predetermined depth, and a gate oxide layer 70 having a side surface 71 and a bottom surface 72 to cover the trench 60. ), And the polysilicon gate 80 formed on a portion of the side surface 71 of the gate oxide film 70 and the bottom surface 72 of the gate oxide film 70 adjacent to the side surface 71 of the gate oxide film 70. And an oxide film 90 deposited in a space formed by the gate oxide film 70 and the polysilicon gate 80, and the plurality of source zeros. Consists of 50, and the source electrode 100 connecting to the polysilicon gate 80 (not shown) connected to a common gate electrode formed in the termination region as possible.

First, the drain electrode 10 may be formed of ordinary aluminum (Al) or the like, but the material is not limited thereto.

The substrate 20 may be a conventional N + type (or P + type, which will be described based on an N-channel FET in the following description). As is well known, an N + type semiconductor substrate is made by inserting N type impurities when forming a single crystal rod.

The drain region 30 is formed by an epitaxial method, and may be an N-type epitaxial layer. As is well known, the N-type drain region 30 is grown by injecting an N-type impurity gas, a silicon gas, and the like together on the substrate 20.

The main body 40 is formed by ion implanting P-type impurities into the drain region 30. Of course, this P-type body 40 is formed after the formation of the trench 60 having the side surface 61 and the bottom surface 62, but here, in order to understand the structure, regardless of the manufacturing process order in the stacking order Explain.

The source region 50 is formed by ion implanting N-type impurities into a portion of the P-type body 40. The concentration of the source region 50 is N +.

The trench 60 is formed in the plurality of source regions 50, the main body 40, and the drain region 30 to a predetermined depth, which is the drain region 30, the main body 40, and the source region 50. ) And a bottom surface 62 in the center of the drain region 30 and the side surface 61 in the form of cutting the up and down directions. Of course, the trench 60 extends to the termination region of the transistor.

The gate oxide layer 70 is formed to cover the trench 60 and a part of the outer surface thereof. Of course, like the trench 60, the gate oxide layer 70 also has a side surface 71 and a bottom surface 72.

The polysilicon gate 80 includes N-type impurities, which are filled in the surface of the gate oxide layer 70 of the trench 60. That is, the polysilicon gate 80 is formed only in a portion of the side surface 71 of the gate oxide film 70 and the bottom surface 72 of the gate oxide film 70 adjacent to the side surface 71 of the gate oxide film 70. It is. Therefore, in the figure, it is formed in substantially "II" form. In other words, the bottom surface 72 of the gate oxide film 70 has a structure in which a portion of the center thereof is in direct contact with the oxide film 90. In addition, the deposition thickness of the polysilicon gate 80 is preferably formed within approximately 2000 kPa to 5000 kPa. When the deposition thickness of the polysilicon gate 80 is set to 2000 GPa or less, the resistance from the gate electrode 110 'to the polysilicon gate 80 increases, so that the switching speed of the device is lowered and the polysilicon gate 80 This is because when the deposition thickness is set to 5000 GPa or more, the parasitic capacitance between the polysilicon gate 80 and the drain region 30 is too high, and the effect of improving the switching speed is lost. Of course, the polysilicon gate 80 is insulated from the source region 50 and the main body 40 by the gate oxide film 70.

As such, the polysilicon gate 80 may be formed only in a portion of the side surfaces 71 and the bottom surface 72 of the gate oxide layer 70, thereby causing parasitics between the polysilicon gate 80 and the drain region 30. Capacitance is minimized. In addition, by minimizing the parasitic capacitance, the switching speed of the transistor is greatly improved, thereby enabling the above transistor to be usefully used for an electronic circuit requiring high speed operation.

The oxide film 90 is deposited to a predetermined thickness in the polysilicon gate 80 and the space formed between the polysilicon gate 80 and the gate oxide film 70, which is a source electrode 100 or a body to be described below with the polysilicon gate 80. It plays a role of preventing the short with the 40.

The source electrode 100 serves to electrically connect the source regions 50 on both sides of the trench 60 with a metal such as aluminum, for example.

Finally, the common gate electrode is connected to the polysilicon gate 80 extending to the termination region, which may also be formed of ordinary aluminum.

3A to 3K, a method of manufacturing a transistor according to the present invention is illustrated sequentially.

As illustrated, the method of manufacturing a transistor according to the present invention includes the steps of providing the semiconductor substrate 20 and the drain region 30 (FIG. 3A), forming the trench 60 (FIG. 3B), and forming the gate oxide film 70. 3C, forming the polysilicon gate 80 (FIG. 3D), etching the polysilicon gate 80 (FIG. 3E), forming the oxide film 90 (FIG. 3F), and forming an oxide film 90 ) An etching step (FIG. 3G), a main body 40 forming step (FIG. 3H), a source region 50 forming step (FIG. 3I), an insulating oxide film 90 forming step (FIG. 3J), and an electrode ( 10,100) forming step (FIG. 3K).

First, the step of providing the semiconductor substrate 20 and the drain region 30 includes a conventional N + type semiconductor substrate, as shown in FIG. 3A, and forms an N-type epitaxial layer by a conventional epitaxial method. Is done. The N + type semiconductor substrate is formed by inserting N type impurities when forming a single crystal rod.

Subsequently, as shown in FIG. 3B, the trench 60 may be formed by forming a trench 60 in the form of a recess in the drain region 30 by a conventional photolithography method. The trench 60 has side surfaces 61 formed at both sides thereof, and a bottom surface 62 is formed at the center of both side surfaces 61 of the trench 60.

Subsequently, forming the gate oxide layer 70 may include a gate having a very thin thickness (for example, approximately 500 GPa) along the side surface 61 and the bottom surface 62 of the trench 60, as shown in FIG. 3C. An oxide film 70 is formed. Of course, the gate oxide layer 70 also has a side surface 71 and a bottom surface 72 in a form corresponding to the trench 60.

Subsequently, as shown in FIG. 3D, the polysilicon gate 80 may be formed by immersing an N-type impurity in the side surface 71 and the bottom surface 72 of the gate oxide layer 70 and the outer circumference thereof. The polysilicon gate 80 is deposited to a certain thickness. Therefore, the polysilicon gate 80 is not formed to fill the trench 60 completely, but is thinly formed only on the side surface 71, the bottom surface 72, and the outer periphery of the gate oxide film 70.

Here, the deposition thickness of the polysilicon gate 80 is preferably formed within about 2000 kPa to 5000 kPa. When the deposition thickness of the polysilicon gate 80 is set to 2000 GPa or less, the resistance from the gate electrode 110 'to the polysilicon gate 80 increases, so that the switching speed of the device is lowered and the polysilicon gate 80 This is because when the deposition thickness is set to 5000 GPa or more, the parasitic capacitance between the polysilicon gate 80 and the drain region 30 is too high, and the effect of improving the switching speed is lost.

Subsequently, in the etching of the polysilicon gate 80, as shown in FIG. 3E, the polysilicon gate 80 contacts only the side surface 71 of the gate oxide layer 70 through a conventional photolithography process. To be That is, the polysilicon gate 80 remains only in a portion of the side surface 71 of the gate oxide film 70 and the bottom surface 72 of the gate oxide film 70 adjacent to the side surface 71 of the gate oxide film 70. Do it. Therefore, the bottom surface 72 of the gate oxide film 70 has a form in which a portion of the center is exposed to the outside through the polysilicon gate 80.

Subsequently, in the forming of the oxide film 90, as shown in FIG. 3F, the oxide film is filled so that the space formed between the trench 60, that is, the side surface 71 and the bottom surface 72 of the gate oxide film 70 is completely filled. 90 is deposited.

Subsequently, in the etching of the oxide layer 90, as illustrated in FIG. 3G, all of the oxide layer 90 on the outer circumference of the trench 60 is removed by a conventional photolithography process. In this case, it is preferable that the top surface of the oxide film 90 and the top surface of the polysilicon gate 80 are flush with each other. Of course, the gate oxide film 70 of the outer periphery of the trench 60 is still left as it is.

Subsequently, the main body 40 is formed by ion implanting P-type impurities into the drain region 30, as shown in FIG. 3H.

Subsequently, as shown in FIG. 3I, the source region 50 may be formed by ion implanting N-type impurities into a predetermined region in the main body 40, which is an outer circumference of the trench 60.

Subsequently, the forming of the oxide film 90 is performed by depositing a silicon oxide film 90 to a predetermined thickness on the polysilicon gate 80 as shown in FIG. 3J. The oxide film 90 serves to prevent a short between the gate electrode and the source electrode 100 connected to the polysilicon gate 80. Of course, at this time, the remaining gate oxide layer 70 remaining on the upper surface of the source region 50 and the main body 40 is etched away.

Lastly, in the forming of the electrodes 10 and 100, as shown in FIG. 3K, the source regions 50 of both sides of the trench 60 are connected with a metal made of aluminum to form a source electrode 100. A drain electrode 10 is formed by depositing a metal of aluminum on a bottom surface of the substrate 20, and a gate electrode (not shown) is formed by depositing a metal of aluminum at an end of the polysilicon gate 80. . Here, the gate electrode is not shown because it is in the inward or outward direction of the figure, but the connection state thereof is shown in the prior art figure 1c. That is, the gate electrode is connected to the polysilicon gate 80 exposed through the oxide film 90.

As described above, the transistor and the method of manufacturing the same according to the present invention have the effect that the parasitic capacitance between the polysilicon gate and the drain region is minimized by allowing the polysilicon gate to be formed only in a portion of the side and bottom surfaces of the gate oxide film. .

In addition, by minimizing the parasitic capacitance as described above, the switching speed of the transistor is greatly improved, and thus there is an effect that it can be usefully used in electronic circuits requiring high-speed operation.

What has been described above is only one embodiment for carrying out the transistor according to the present invention and a method of manufacturing the same, and the present invention is not limited to the above-described embodiment, as claimed in the following claims of the present invention Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

FIG. 1A is a partial plan view of a conventional transistor, FIG. 1B is a cross-sectional view illustrating a-a line of FIG. 1A, and FIG. 1C is a cross-sectional view of b-b line of FIG. 1A.

2 is a cross-sectional view showing a transistor according to the present invention.

3A to 3K are sequential explanatory diagrams showing a method of manufacturing a transistor according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10; Drain electrode 20; Board

30; Drain region 40; main body

50; Source region 60; Trench

61; Side 62 of the trench; Bottom of trench

70; A gate oxide film 71; Side of gate oxide

72; A bottom surface 80 of the gate oxide film; Polysilicon gate

90; Oxide film 100; Source electrode

110 '; Gate electrode 120 '; Termination area

Claims (5)

A drain electrode, a substrate positioned on the drain electrode, a drain region formed on the substrate, a body formed on the drain region, a plurality of source regions partially formed on the body, the plurality of source regions, a body, and a drain A trench having side and bottom surfaces with a predetermined depth in the region, a gate oxide film having side and bottom surfaces covering the trench, a poly silicon gate filled on the gate oxide surface of the trench, and a top of the poly silicon gate A transistor comprising a formed oxide film, a source electrode connecting the plurality of sources, and a common gate electrode formed in a termination region to connect the polysilicon gate, And the polysilicon gate is formed on a portion of a bottom surface of the gate oxide film and a side surface of the gate oxide film and adjacent to the side surface of the gate oxide film. The transistor of claim 1, wherein a portion of the center of the gate oxide layer is in direct contact with the oxide layer. The transistor of claim 1, wherein the deposition thickness of the polysilicon gate is within about 2000 kV to 5000 kPa. Forming a semiconductor drain region having a predetermined thickness on the semiconductor substrate through an epitaxial process, and forming a trench having a predetermined depth having side and bottom surfaces in the drain region; Forming a gate oxide film having a predetermined thickness on side and bottom surfaces of the trench; Depositing a polysilicon gate having a predetermined thickness on side and bottom surfaces of the trench, and etching the polysilicon gate to expose a central region of the bottom surface of the gate oxide layer to the outside; After depositing the oxide layer to completely fill the trench, etching the oxide layer outside the trench; Forming a main body by implanting a predetermined concentration of impurities into a drain region that is an outer circumference of the trench, and implanting a predetermined concentration of impurities into the main body to form a source region; And, Forming an oxide film so as to completely cover an upper portion of the polysilicon gate and to expose the source region, and forming a source electrode, a drain electrode, and a gate electrode to be connected to the source region, the substrate, and the polysilicon gate. Method of manufacturing a transistor. The method of claim 4, wherein the deposition thickness of the polysilicon gate is within about 2000 kPa to 5000 kPa.