KR100497072B1 - A memory device - Google Patents

Abstract

The memory cell includes a FET having a gate connected to a word line and a drain connected to a bit line, a capacitor having one end connected to a source of the FET and the other end connected to a first power source, and a first provided between the word line and the source of the FET. And a second negative differential resistance element provided between the source of the FET and the second power supply.

Description

Memory device {A MEMORY DEVICE}

The present invention relates to a memory device, and more particularly, to a memory having a negative differential resistance element such as a tunneling diode.

Semiconductor Random Access Memory (hereinafter referred to as RAM), in particular, a 1T / 1C (1-transistor / 1-capacitor) dynamic RAM (DRAM) formed of a plurality of cells, each of which consists of one transistor and one capacitor element ), The simplification of the memory configuration has resulted in densities reaching current gigabit levels. However, in 1T / 1C DRAM, since the charge current accumulated in the capacitor element is lost at a fixed rate due to the leakage current, it is necessary to periodically perform the refresh operation at a rate of about several times to several tens of times per second for the capacitor element.

In static RAM (SRAM), no refresh operation is required and the speed obtained is generally faster than DRAM, but the fact that SRAM requires flip-flop circuitry makes this more complicated than DRAM, and typically, six transistors or four Since it is constructed like a memory using a transistor and two polysilicon negative differential resistance elements, the degree of integration is lower than in the case of DRAM.

Therefore, a memory configuration that can have the same degree of integration as DRAM without requiring a refresh operation like SRAM is required.

Such a memory configuration is disclosed, for example, in SRAM form using a resonant tunneling diode (RTD) in Japanese Patent Laid-Open No. 10-69766.

8 is a circuit diagram illustrating the configuration of a conventional memory cell, and FIG. 9 is a diagram illustrating the circuit operation of FIG. 8 in a standby state.

As shown in Fig. 8, the memory cell is provided between the N-channel FET 103, the N-channel FET 103, and the cell plate CP, whose gate and drain are connected to the word line 101 and the bit line 102, respectively. And a cell capacitance 104 connected to the first and second negative differential resistance elements 105 and 106 connected in series between the power supply potentials VDD and VSS. The cell nodes SN of the negative differential resistance elements 105 and 106 are connected to the source of the N channel FET 103.

When the memory cell is in the standby state, that is, when the word line potential is low and the N channel FET 43 is in the off state, the memory cell retains the contents of the memory by the charge stored in the cell capacitance 104. do. In conventional DRAM, due to the leakage current, the amount of charge stored in the memory cell changes, and information cannot be kept static. On the other hand, the series circuit formed by the negative differential resistance elements 105 and 106 has two stable operating points shown by 111 and 112 in FIG. Therefore, since the cell node SN voltage is determined as one of two voltages corresponding to the two stable operating points 111 and 112, it is possible to maintain static information.

However, in the above-described conventional memory cell, in order to drive the negative differential resistance element, since the interconnects for supplying the power supply voltages VDD and VSS to each memory cell are required, only the surface area of the cell is increased. Rather it reduces the possible degrees of freedom in cell layout.

It is therefore an object of the present invention to solve the above problems by providing a memory device having a small cell surface area and a high degree of freedom in cell layout.

In order to achieve the above object, the present invention adopts the following basic technical configuration.

A first aspect of the invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET whose gate is connected to a word line and a drain is connected to a bit line, one end of which is connected to a source of the FET. And a first negative differential resistance element provided between the capacitor and the other end connected to the first power source, the word line and the source of the FET, and a second negative differential resistance element provided between the source of the FET and the second power source.

In a second aspect of the invention, the FET is an N-channel FET and the potential of the second power supply is a predetermined potential that is greater than 0V.

In a third aspect of the invention, the FET is a P channel FET and the potential of the second power supply is 0 V.

In a fourth aspect of the present invention, the negative differential resistance element is an Esaki diode or a resonance tunneling diode.

A fifth aspect of the invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET whose gate is connected to a word line and a drain is connected to a bit line, one end of which is connected to a source of the FET. And a first negative differential resistance element provided between the capacitor and the other end connected to the power source, the word line and the source of the FET, and a second negative differential resistance element provided between the source of the FET and the power source.

A sixth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET having a gate connected to a word line and a drain connected to a bit line, and one end connected to a source of the FET. And a capacitor having the other end connected to the first power source, a resistor element provided between the word line and the source of the FET, and a negative differential resistance element provided between the source of the FET and the second power source.

A seventh aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET having a gate connected to a word line and a drain connected to a bit line, and one end connected to a source of the FET. And a capacitor having the other end connected to the power supply, a resistance element provided between the word line and the source of the FET, and a negative differential resistance element provided between the source of the FET and the power source.

An eighth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET having a gate connected to a word line and a drain connected to a bit line, one end of which is connected to a source of the FET And a capacitor having the other end connected to the first power source, a negative differential resistance element provided between the word line and the source of the FET, and a resistance element provided between the source of the FET and the second power source.

A ninth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising a FET having a gate connected to a word line and a drain connected to a bit line, and one end connected to a source of the FET. And a capacitor having the other end connected to the power source, a negative differential resistance element provided between the word line and the source of the FET, and a resistance element provided between the source of the FET and the power source.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(1st embodiment)

1A and 1B are circuit diagrams showing memory cells forming a memory device according to the first embodiment of the present invention. FIG. 2 is a graph showing the voltage versus current static characteristics of the negative differential resistance element used in the circuits of FIGS. 1A and 1B, FIG. 3A is an equivalent circuit diagram of the circuit of FIG. 1A in a standby state, and FIG. It is a graph.

As shown in Fig. 1A, the memory device of this embodiment has a memory cell disposed at an intersection of a bit line and a word line. As shown in Fig. 1A, each of these memory cells has an N-channel FET 103, a source and a cell of the N-channel FET 103, whose gate and drain are connected to the word line 1 and the bit line 2, respectively. Negative differential resistance formed by the cell capacitance 4 connected between the plates CP and the first and second negative differential resistance elements 5 and 6 connected in series between the word line 1 and the reference voltage line. Device pair 15. The node MN between the negative differential resistance elements 5, 6 is connected to the source of the N-channel FET 3 and one terminal of the cell capacitance 4. As shown in Fig. 2, the first and second negative differential resistance elements 5 and 6 each have an N type (voltage controlled type) negative differential resistance characteristic. Tunneling diodes such as Ezaki diodes and RTDs can be examples of negative differential resistance elements.

The operation of the above-described memory cell is described below.

As shown in Fig. 3A, when the memory cell is in the standby state, since the N-channel FET 103 is in the off state, the potential of the word line is kept at 0V. In FIG. 3A, a circuit element corresponding to the circuit element of FIG. 1A is shown using the same reference numerals as in FIG. 1A. The current source 8 represents a current flowing in the memory cell node MN or a leakage current flowing outward from the memory cell node MN. In this case, the potential at the connection point 7 to which the second negative differential resistance element 6 is connected is set to VDD. When the potential at the memory cell node MN between the negative differential resistance elements 5 and 6 changes from 0 V to the power supply potential VDD, the current indicated by the curves 9 and 8 in FIG. 3B is the negative differential resistance. It flows into the element 5. In the curve 9 showing the current flowing through the negative differential resistance element 5, the leakage current IL is added. The negative differential resistance element pairs 15 formed by the negative differential resistance elements 5 and 6 operate stably at the current indicated by the two crossing points 11 and 12 of the curves 9 and 10.

In the conventional DRAM, the leakage current corresponding to the leakage current IL provided by the current source 8 causes variations in the charge stored in the cell capacitance, so that information cannot be kept static.

However, in the memory device according to the present embodiment of the present invention, as described above, even when there is a leakage current, the negative differential resistance element pair 15 is stably at one of the two stable operating points 11 and 12. It works. Therefore, the potential on the memory cell node MN is fixed to one of the potentials VL and VH at the two stable operating points 11 and 12, and remains the same as long as the power supply voltage is supplied. For this reason, the amount of charge stored in the cell capacitance 4 is one of two levels of charge corresponding to the stable potentials VL and VH of the memory cell node MN, and as long as the power supply voltage is supplied, this charge level is It remains in the same state, so that stable information can be maintained.

The current levels of the negative differential resistance elements 5 and 6 are preferably as low as possible from the viewpoint of power consumption. However, when the leakage current IL exceeds the peak current value of the negative differential resistance element, the stable point 12 no longer exists. Therefore, it is necessary to extend the peak current value of the negative differential resistance element at least larger than the leakage current IL to ensure the above-mentioned bistability. This condition can be satisfied by using a negative differential resistance element having a valley current at the same level as the leakage current value. However, when the ratio between the peak current value and the valley current of the negative differential resistance element is approximately 10, when the variation of the leakage current value characteristic between the memory cells is taken into consideration, the peak current level of the negative differential resistance element is the average leakage current. It is preferred to be approximately 50 to 100 times the value (approximately 1 to 10 fA). The bi-stability of the negative differential resistance element pair 15 eliminates the need for the periodic refresh operation required in conventional DRAM, thereby reducing power consumption in the standby state. For example, VDD is 3.3V, the parasitic capacitance and cell capacitance of the bit line are 270 fF and 27 fF, respectively, and the average leakage current level is 1 fA, and the negative differential resistor peak current value and peak / valley current ratio are 100, respectively. In the case of fA and 10, the standby power is approximately 2 orders of magnitude when compared to DRAM having the same VDD, the same bit line parasitic capacitance, the same cell capacitance, and the same average leakage current level, and refreshing every 128 milliseconds. There is a reduction in consumption.

The memory cell read / write operation and the storage operation of the above-described memory are substantially the same as in the conventional 1T / 1C DRAM. That is, in the read operation, while the bit line is precharged to a specific potential, the voltage of the selected word line is raised to VDD so that the N channel FET is turned on. When this is done, a potential change occurs in the bit line by the charge stored in the cell capacitance, which is amplified by a differential amplifier disposed outside the cell. The bit line data amplified by the differential amplifier is read out of the memory as a high state or a low state depending on the amount of charge stored in the memory capacitance, and also returned to the cell through the N-channel FET to rewrite the data. In the write operation, similarly to the read operation, while maintaining the data read from each memory cell on the bit line, the bit line voltage of only the overwrite cell is forcibly changed in accordance with the input information, Overwrite cell information.

During the panning operation and during the writing operation, when the potential of the word line is changed to VDD, the potential of one terminal of each of the negative differential resistance elements 5 and 6 becomes VDD, and the negative differential resistance element pair 15 is a memory cell node. The potential of (MN) is raised to VDD. However, since the current level in the negative differential resistance element is selected to be sufficiently smaller than the N-channel FET or sense amplifier driving current, the time constant value for raising the potential of the memory cell node MN to VDD is greater than the memory cell access time. Bigger For example, in the case of a peak current level of 100 fA and a bit line parasitic capacitance of 270 fF for the negative differential resistance element, the time constant value for raising the potential of the memory cell node MN is greater than 3 seconds. Since this is sufficiently longer than the average cell access time of 80 nanoseconds, under these conditions, the influence of the negative differential resistance element pair 15 on the memory cell access time can be ignored.

As described above, in the memory device according to the embodiment of the present invention, within the range where the bi-stability is not sacrificed, the current level of the negative differential resistance element is formed as small as possible. As a result, in the memory device according to the present embodiment, since the influence of the negative differential resistance element on the read and write operations can be ignored, the device has the same access time as the DRAM access time, and in a lower standby state than the DRAM. Can achieve power consumption.

As described above, the memory device of the present invention has a FET 3 whose gate is connected to the word line 1 and the drain is connected to the bit line 2, one end of which is connected to the source of the FET and the other end of which is the first power source. A capacitor (4) connected to the 31, a first negative differential resistance element 5 provided between the word line 1 and the source of the FET, and a second provided between the source of the FET and the second power supply 32. A two negative differential resistance element 6 is provided.

The cell plate voltage can be set to be VDD / 2, as in conventional DRAM. However, at a cell capacitance allowable voltage of VDD or more, the voltage of the cell plate can be set to VDD as shown in FIG. 1B. In this case, since the value of the cell plate potential and the potential of the reference voltage line to which the negative differential resistance element 6 is connected are the same, the cell plate and the reference voltage line can be combined, thereby eliminating the need for a separate reference voltage line. Provide an advantage.

(2nd embodiment)

4 is a circuit diagram of a memory cell forming a semiconductor device according to the second embodiment of the present invention.

 As shown in Fig. 4, the memory device of this embodiment has a memory cell disposed at an intersection of a bit line and a word line. As shown in Fig. 4, each of these memory cells has a P-channel FET 23, a source and a cell of the P-channel FET 23, whose gate and drain are connected to the word line 21 and the bit line 22, respectively. Negative differential resistance elements formed by cell capacitance 24 connected between plates CP, first and second negative differential resistance elements 25 and 26 connected in series between word line 21 and reference voltage line. Has a pair 35. The node MN between the negative differential resistance elements 25 and 26 is connected to one terminal of the source and the cell capacitance 24 of the P channel FET 23. The reference voltage line potential is set to 0V. That is, the memory device of the second embodiment is configured to replace the N-channel FET of the memory device of the first embodiment with a P-channel FET and to set the potential of the reference voltage line to 0V. In this case, since the P-channel FET is in the off state from the standby state, the potential of the word line 21 is maintained at VDD. As a result, voltages 0 V and VDD are applied to the terminals of the negative differential resistance element pair 35 formed by the series connection of the first negative differential resistance element 25 and the second negative differential resistance element 26. The same type of bistable operation as shown in Fig. 3B for the first embodiment is obtained. However, in this case, the operating curve of the first negative differential resistance element and the operating curve of the second negative differential resistance element are interchanged with each other.

In the memory device according to the second embodiment, similarly to the memory device of the first embodiment, the current level of the negative differential resistance element is set to be as small as possible in a range in which the bistable operation is not lost. As a result, in the memory device of the second embodiment, the device has the same access time as the access time of the DRAM, for the same reason as applied to the memory device of the first embodiment, and even lower power of the DRAM in the standby state. Consumption can be achieved. When the cell plate voltage is set to 0 V, the terminal of the second negative differential resistance element 26 can be connected to the cell plate CP, thereby eliminating the need for a reference voltage line.

(Third embodiment)

FIG. 5 is a circuit diagram showing a memory cell according to the third embodiment of the present invention, and FIG. 6 is a diagram showing the operation of the circuit of FIG.

As shown in Fig. 5, the memory device according to the third embodiment of the present invention has a memory cell disposed at an intersection point of a bit line and a word line. As shown in Fig. 5, each of these memory cells has an N-channel FET 43, a source and a cell of the N-channel FET 43, whose gate and drain are connected to the word line 41 and the bit line 42, respectively. The cell capacitance 44 connected between the plates CP, and the resistance element 45 and the negative differential resistance element 46 connected in series between the word line 41 and the reference voltage line are provided. The node MN between the resistance element 45 and the negative differential resistance element 46 connected in series is connected to the source of the N-channel FET 43 and one terminal of the cell capacitance 44. The reference voltage line potential is set to VDD. That is, the memory cell of the third embodiment is configured such that the first subdifferential differential resistance element of the first embodiment is replaced with a resistance element.

As shown in Fig. 6, in the case where the potential of the memory cell node MN, which is the connection point between the resistance element 45 and the negative differential resistance element 46, changes from 0 V to the power supply potential VDD, the resistance element By adjusting the resistance value of (45), three intersection points of the current curve 49 of the resistance element 45 and the current curve 50 of the negative differential resistance element 46 are obtained. In this case, the leakage current IL is added to the current curve 49 of the resistance element 45. The two points 51 and 52 which are the intersection points between the current curve 49 of the resistance element and the current curve 50 of the negative differential resistance element 46 are stable operating points. Therefore, the potential of the memory cell node MN is fixed to one of the voltages VL and VH at the operating points 51 and 52, and remains the same as long as the power supply voltage is supplied. For this reason, the amount of charge stored in the cell capacitance 44 is one of two charge amounts corresponding to the stable potentials VL and VH of the memory cell node, and maintains this state as long as the power supply voltage is supplied, thereby keeping the information stable. Can be. Even when the ratio between the peak current value and the valley current value of the negative differential resistance element 46 is not large, the resistance value of the resistance element 45 can be precisely controlled and stable operation can be performed. This embodiment has the advantage that the number of negative differential resistance elements can be reduced as compared with the circuits shown in the first and second embodiments of the present invention.

As another method, the above-described effect can be obtained by replacing the N-channel FET 43 with the P-channel FET and setting the potential of the reference voltage line to 0V. Alternatively, as shown in FIG. 7, it is also possible to replace the resistance element 45 with the negative differential resistance element 51 and the negative differential resistance element 46 with the resistance element 52. Do.

While the preferred embodiments of the present invention have been described by way of example, it will be appreciated that these are merely exemplary embodiments and do not limit the scope of the invention and that various modifications may be made within the scope of the invention. . For example, negative differential resistance elements such as Ezaki diodes, resonant tunneling diodes or other tunneling diodes and N-type Gunn diodes may be used. It is also possible to use two of the three terminals of the resonance tunneling transistor or the resonance tunneling hot electron transistor. In addition, the FET used for the memory cell may be a bipolar transistor, and furthermore, the cell capacitance 4 may be omitted if it is possible to provide a sufficiently high capacitance to the negative differential resistance element.

As described above, the present invention provides at least one negative differential resistance element between a memory cell node and a word line or between a memory cell node and a reference voltage line of a memory cell forming a conventional 1T / 1C DRAM. Bi-stability of the charge stored in the memory capacitance can be achieved to keep the information static.

In addition, the present invention eliminates the need for a separate reference voltage line by allowing the reference voltage line and the cell plate to have the same potential, thereby enabling the connection of the negative differential resistance element in the complete cell, and the degree of freedom in the cell layout. The same degree of integration as conventional DRAM can be achieved without sacrificing the cost.

1A and 1B are circuit diagrams showing memory cells of a memory device according to the first embodiment of the present invention.

FIG. 2 is a graph showing the voltage versus current static characteristics of the negative differential resistance element used in the circuit of FIG. 1A. FIG.

3A is an equivalent circuit diagram of the circuit of FIG. 1A in a standby state, and FIG. 3B is a graph showing its operation.

4 is a circuit diagram showing a memory cell of the memory device according to the second embodiment of the present invention.

Fig. 5 is a circuit diagram showing a memory cell of the memory device according to the third embodiment of the present invention.

6 illustrates the operation of the circuit of FIG.

7 is another circuit diagram of a memory cell according to the third embodiment of the present invention.

8 is a circuit diagram showing a conventional memory cell.

9 illustrates the operation of the circuit of FIG. 8 in a standby state.

* Description of the symbols for the main parts of the drawings *

1, 21, 41, 101: word line 2, 22, 42, 102: bit line

3, 43, 103: FET 4, 24, 44, 104: capacitor

5, 25, 105: first negative differential resistance element

6, 26, 106: second negative differential resistance element

7, 27, 47: connection point to reference voltage line

8: current source

45: resistance element

Claims (13)

A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a first power source; A first negative differential resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a second negative differential resistance element having one end connected to the source of the FET and the other end connected to a second power source. The method of claim 1, The FET is an N-channel FET, and the potential of the second power supply is a predetermined potential that is greater than 0V. The method of claim 1, The FET is a P-channel FET, and the potential of the second power supply is a ground potential. The method of claim 1, And the negative differential resistance element is an Ezaki diode or a resonance tunneling diode. A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a power source; A first negative differential resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a second negative differential resistance element having one end connected to the source of the FET and the other end connected to the power supply. A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a first power source; A resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a negative differential resistance element having one end connected to the source of the FET and the other end connected to a second power source. The method of claim 6, The FET is an N-channel FET, and the potential of the second power supply is a predetermined potential that is greater than 0V. The method of claim 6, The FET is a P-channel FET, and the potential of the second power supply is a ground potential. A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a power source; A resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a negative differential resistance element having one end connected to the source of the FET and the other end connected to the power supply. A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a first power source; A negative differential resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a resistance element having one end connected to the source of the FET and the other end connected to a second power source. The method of claim 10, The FET is an N-channel FET, and the potential of the second power supply is a predetermined potential that is greater than 0V. The method of claim 10, The FET is a P-channel FET, and the potential of the second power supply is a ground potential. A memory device having a memory element provided at an intersection of a word line and a bit line, The memory device, A FET having a gate connected to the word line and a drain connected to the bit line; A capacitor having one end connected to a source of the FET and the other end connected to a power source; A negative differential resistance element having one end connected to the word line and the other end connected to the source of the FET; And And a resistance element having one end connected to the source of the FET and the other end connected to the power supply.