JPH0778945A - Negative resistance diode memory - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory which uses a pair of negative resistance diodes so as to allow less leak current at the time of reading and writing information on a desired memory cell. CONSTITUTION:A negative resistance diode memory is provided with a memory element formed by connecting two negative resistance diodes RTD 1 and RTD 2 in series permitting to face each other, and a reading/writing diode D connected to the connecting points of the two negative resistance diodes. The diode D has a spacer layer SP between the actual peak of the potential barrier which controls the flow of carriers and a conductive area from which the carriers start so as to take at least a partial applying voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory,
In particular, it relates to a semiconductor memory using a pair of negative resistance diodes.

In the field of information processing electronic devices, memory devices for storing information play an important role. Static memory devices, which can store information without a refresh operation, are particularly easy to handle and have a wide range of applications.

Normally, the basic structure of a static memory cell is formed by using two transistors and two loads, but if a negative resistance diode is used, the basic structure of a static memory cell can be formed by two elements. it can.

[0004]

2. Description of the Related Art As the amount of information in an information processing device increases, a large capacity memory is required. In particular, it is desired to increase the capacity of a high-speed random access memory that can be directly accessed by the CPU.

In order to increase the capacity, it is desirable that the number of semiconductor elements required for each memory cell is smaller.
By connecting negative resistance diodes such as resonance tunnel diodes in series, two stable operating points can be obtained, and the basic configuration of the static memory cell can be formed.

Compared with the basic structure of an ordinary static memory cell using four transistors or two transistors and two load resistors, the structure can be remarkably simplified and the capacity can be easily increased.

6 and 7 show examples of the structure of a resonant tunnel diode memory. FIG. 6A shows two resonant tunneling diodes (RTD) and one tunneling diode (T
2D schematically shows a cross-sectional structure of a memory cell configured using D).

On the supporting substrate 101, n-type InGaAs is formed.
Layer 102, non-doped InAlAs layer 103, n-type In
The GaAs layer 104 is laminated to form a tunnel diode TD1 having a rectangular potential barrier. 2 on the n-type InGaAs layer 104 of the tunnel diode TD1
Two resonance tunnel diodes RTD1 and RTD2 are formed.

Resonant tunneling diodes RTD1 and RT
D2 is n-type InGaAs layers 106a and 106b, non-doped AlAs layers 107a and 107b, and i-type InGa.
As layers 108a, 108b, AlAs layers 109a, 10
9b and n-type InGaAs layers 110a and 110b are laminated.

Cr / Au is used as an electrode on each RTD.
The layers 112a and 112b are stacked. These Cr
The / Au layers 112a and 112b form a pair of word lines. Although not shown, the n-type InGaAs layer 102 is connected to one bit line.

FIG. 6B is a circuit diagram showing an equivalent circuit of the configuration shown in FIG. Two resonance tunnel diodes RTD1 and RTD2 are connected in series, and both ends thereof are connected to a pair of word lines W1 and W2.

Further, two resonance tunnel diodes RT
The tunnel diode TD1 is connected to the interconnection point of D1 and RTD2, and the other end is connected to the bit line B.

Two resonant tunneling diodes RTD1,
The interconnection point of RTD2 constitutes a memory node, and the tunnel diode TD1 constitutes a read element and a write element for this memory node.

FIG. 6C is a potential diagram showing the potential profile in the resonant tunneling diode. In the figure, the horizontal axis represents the layer thickness direction, and the vertical axis represents energy for charge carriers.

The two AlAs layers 107 and 109 form a potential barrier, and i-type InGa sandwiched between the two is formed.
The As layer 108 constitutes a potential well. Note that n-type InG is provided outside the two potential barriers.
The conductive regions formed by the aAs layers 106 and 110 are connected.

The state of charge carriers (electrons) in the potential well 108 is quantized in the potential well sandwiched by the potential barriers and takes discrete energy values. Therefore, when a voltage is applied between the conductive regions 106 and 110 on both sides, a negative resistance as shown in FIG.

FIG. 6E shows a potential profile in the tunnel diode TD. Similar to FIG. 6 (C)
The horizontal axis represents the layer thickness direction, and the vertical axis represents the potential for charge carriers.

Two n-type InGaAs layers 102 and 104
The InAlAs layer 103 sandwiched between has a high potential for electrons and constitutes a potential barrier. When a positive voltage is applied to one of the n-type InGaAs layers, for example 102, the potential profile changes as shown by the broken line, the potential barrier decreases, and it becomes possible to transport charge carriers. Since the structure is symmetric, this characteristic is the same even when a positive voltage is applied to either of the n-type InGaAs layers 102 and 104.

Therefore, the tunnel diode TD shown in FIG. 6 (E) exhibits IV characteristics as shown in FIG. 6 (F). Next, the characteristics of the series connection circuit of the two resonant tunnel diodes RTD will be described with reference to FIG. It is assumed that two resonant tunneling diodes RTD1 and RTD2 are connected in series via an interconnection part and are connected to a DC voltage V _B.

FIG. 7B shows the characteristics of the circuit shown in FIG. Two resonant tunneling diodes RTD1 and R
The characteristics of TD2 are inverted and overlapped at the power supply voltage V _B , and three intersections P1, P2, and P3 are generated.

Of these three intersections P1 to P3, the intermediate intersection P3 is a stable point only in the quasi-static state, and is actually an uneasy point. If the power supply voltage V _B increases, it moves to the upper stable point P1, and if it decreases, it moves to the lower stable point P1.

The intersections P1 and P2 on both sides are stable operating points. Therefore, two resonant tunneling diodes RTDs
The voltage at the intersection P of 1 and RTD2 is one of the two voltages V1 and V2 corresponding to P1 and P2.

Two resonant tunneling diodes RTD1,
The potential at the intersection of RTD2 can be read out through the third diode. In addition, by injecting or drawing out a current from the intersection P through the third diode, the potential of the connection P can be changed and writing can be performed.

For example, if a sufficient current is supplied from the third diode to the connection point P, the potential at the connection point rises and the high level state is set. Further, if a sufficient amount of current is drawn from the connection point P, the potential of the connection point P drops and the low level state is set.

As a memory device, a large number of such memory cells are arranged in a matrix, a large number of memory cells are connected to one word line, and a large number of memory cells are also connected to one bit line. Information from each memory cell can be selectively read / written by adjusting the potential of each word line and each bit line.

In order to efficiently perform this read / write operation, the characteristic of the third diode for read / write is that the current suddenly rises at a certain potential, as shown in FIG. 7C. It is preferable to have.

If the third diode having such a steep characteristic is used, a voltage above the threshold value is applied only to a predetermined memory cell, and a voltage below the threshold value is applied to other memory cells. Read / write can be efficiently performed.

When the characteristic of the third diode used for reading / writing has a considerable leakage current even at a rising voltage or less as shown in FIG. 7D, when reading information from a desired memory cell. In addition, a considerable amount of leak current also flows from other memory cells. For this reason, if a large number of cells are connected to the bit line, the drive current may become too large, or read / write may not be performed normally.

[0029]

As described above,
As a diode for reading / writing a memory cell using a diode having a negative resistance, it is desired that the current rapidly increases when a voltage higher than a threshold value is applied.

By the way, in the characteristics of the tunnel diode as shown in FIG. 6E, the average height of the potential barrier is reduced by voltage application, but the potential at the highest point of the potential barrier hardly changes. Therefore, the change in current with respect to the applied voltage is unlikely to be sharp. Therefore, the leak current when writing / reading information to / from a desired memory cell becomes large.

It is an object of the present invention to provide a negative resistance diode memory having a small leak current when reading / writing information from / to a desired memory cell. Another object of the present invention is to provide a negative resistance diode memory capable of high-speed read / write operation.

[0032]

The negative resistance diode memory of the present invention comprises two negative resistance diodes (RTD1,
A memory element in which the RTDs 2) are connected in series to face each other, and a read / write diode (D) connected to an interconnection point of the two negative resistance diodes, which is a potential barrier for limiting the flow of carriers. And a read / write diode having a spacer layer (SP) which bears at least part of the applied voltage between the highest point and the conductive region on the starting side of the carrier.

[0033]

A basic memory structure having a simple structure is formed by connecting a pair of negative resistance diodes in series so as to face each other.

A third diode, which is connected to the interconnection point of the two negative resistance diodes, has a spacer layer between the starting conductive region of the carriers and the substantial highest point of the potential barrier, The applied voltage is effectively applied to the spacer layer. Therefore, the potential is effectively controlled by the application of the voltage at the substantially highest point of the potential barrier, and the current rises sharply.

[0035]

EXAMPLE A phenomenon in which charge carriers flow across a potential barrier in a diode is that the height of the highest point of the potential barrier is lowered first, and then the barrier is deformed by applying an electric field to pass (tunnel) the barrier. Due to the increase of electrons.

In the case of the conventional tunnel diode having the rectangular potential barrier, the current increase is mainly due to the deformation of the barrier due to the application of the electric field, and the height of the highest point of the barrier cannot be easily lowered.

In general, the steepness of the current-voltage dependence of a diode is the largest, and the I-value of an ideal pn diode is large.
= I _O {exp (eV / kT) -1}. This dependence is obtained when the current exceeds the highest point of the potential barrier and is determined by the emission, and the height of the highest point of the potential barrier changes with the applied voltage. Such a situation is realized by a pn junction or a Schottky junction.

In the conventional rectangular potential barrier tunnel diode, the highest point of the potential barrier occurs at a position adjacent to the conductive region on the low potential side (conductive region on the side where carriers start) of the barrier.

Since the distance between the conductive region on the starting side of carriers and the highest point of the potential barrier is short, the height of the highest point of the potential barrier depends on the applied voltage. It only appears in the change in height of the highest point. If 1 / n of the applied voltage contributes to a height change of the potential barrier highest point, characteristic of the diode is _{I = I O {exp (eV} / nkT) -1} , and the it is significantly lower steepness of the current-voltage characteristic Can understand.

Therefore, the present inventor proposes to insert a spacer layer that bears a potential between the conductive region on the side where the carrier starts and the highest point of the potential barrier. As shown in the potential diagram of FIG. 1A, a spacer layer 3 that bears a part of the applied voltage is inserted between the conductive region 1 where carriers start and the region 2 where the highest point of the potential barrier is formed. To do. Note that another conductive region 4 is connected after the region forming the potential barrier.

For comparison, the shape of the potential barrier in a conventional tunnel diode having a rectangular potential barrier is shown by 2a. That is, the shape of the potential barrier is changed from the rectangular shape indicated by 2a to the trapezoidal shape indicated by 2 and 3.

As shown in the potential diagram of FIG. 1B, when the potential of the conductive region 4 where the carrier reaches is lowered with respect to the conductive region 1 where the carrier starts, the potential of the intermediate regions 3 and 2 is reduced. Changes as shown.

Here, the highest point of the potential barrier is substantially formed by the boundary H between the regions 3 and 2. Since this boundary is separated by the length of the spacer layer 3 from the conductive region 1 from which carriers start, the applied voltage is effectively applied to the highest point of the potential barrier, and the highest point of the potential barrier is lowered.

By comparing with the potential profile of the conventional rectangular barrier, the magnitude of change in the maximum point of the potential barrier can be clearly understood. When a voltage is applied to the conductive region 4 to cause a current to flow, if the highest point of the potential barrier is at the boundary J between the intermediate region 2 and the conductive region 4, the rate of change is maximum. In this case, exp (eV
The voltage dependence of / kT) is obtained.

However, in this case, the voltage dependence of the current in the opposite polarity is reduced. Conductive area 4 for reading information
Is used (when the carrier is an electron, a positive voltage is applied), it is preferable to perform another operation as described later for writing information.

As described above, by providing the spacer layer 3 between the highest point H of the potential barrier and the conductive region 1 in which the carriers start, the rate at which the highest point of the potential barrier changes with the applied voltage is increased. Therefore, the steepness of the current-voltage characteristic can be improved.

By changing the flowing current largely with a small change in the applied voltage, it becomes possible to allow the current to flow only in the selected specific memory cell. As a result,
It becomes possible to normally perform read / write operations on a large number of memory cells. Hereinafter, a specific configuration example for realizing the operation described with reference to FIG. 1 will be described.

FIG. 2 shows a negative resistance diode memory according to an embodiment of the present invention. FIG. 2A is a schematic sectional view showing the structure of the negative resistance diode memory cell. A p-type InGaAs layer 11 and an n-type InGaAs 12 are laminated on the substrate 1 which provides physical support, and constitutes a pn junction diode D1. On this pn junction diode D1, two resonance tunnel diodes RTD1 and RTD2 similar to those described in FIG. 6 are laminated.

Each resonant tunnel diode RTD has n-type InGaAs layers 6a and 6b and InAlAs layers 7a and 7b.
b, non-doped InGaAs layers 8a, 8b, InAlA
s9a, 9b and n-type InGaAs layers 10a, 10b are laminated. On the RTD1 and RTD2, a Cr / Au layer 12a acting as a word line,
12b are stacked.

The potential profile in each resonant tunnel diode RTD is 2 as shown in FIG.
Two potential barrier regions 7 and 9 with a region 8 serving as a potential well sandwiched between two conductive regions 6 and 10.
Are formed.

In the potential well region 8 sandwiched between the potential barrier regions 7 and 9, the carrier energy state is quantized and takes discrete values. For this reason,
Negative resistance is indicated.

In the pn junction diode D1, a potential profile as shown in FIG. 2C is formed. At the pn junction between the p-type region 11 and the n-type region 12, a depletion layer develops and bears the applied voltage of the pn junction diode D1. When a voltage is applied to the pn junction diode D1, the depletion layer SP around the pn junction expands and contracts to absorb the applied voltage.

The highest point of the potential barrier when electrons move from the n-type region 12 to the p-type region 11 exists at the end of the depletion layer around the pn junction. That is, the spacer layer SP formed by the depletion layer is inserted between the conductive region where the carrier starts and the highest point of the potential barrier.

[0054] According to this embodiment, the read / write diode of the memory cell is formed at the pn junction diode, the IV characteristic _{I = I O {exp (eV} / kT) -
1] shows the exponential dependence expressed as 1}.

Therefore, it is possible to apply a bias voltage so that a desired memory cell becomes conductive, and to adjust the diode with respect to other cells so as to maintain a sufficiently high impedance. Therefore, the contents of a specific cell can be stably read without being interfered with by the contents of other cells.

When writing information to this memory cell, a current in the reverse bias direction of the diode is required. In this case, the potential difference between the word line pair to which the selected memory cell is connected is reduced from that in the normal information holding state, and then the pulse voltage is applied to the bit line. By this operation, writing can be performed.

When the potential difference between the word line pair is reduced, the current value required to write the cell state is reduced. When a pulse voltage is applied to the bit line, a current flows in a pulsed manner through the diode in the reverse bias state, and it is possible to write information only to the cell selected by this current.
In the following embodiments, the same writing can be performed when a current in the reverse bias direction is required.

FIG. 3 shows a resonant tunnel diode memory cell according to another embodiment of the present invention. FIG. 3A is a cross-sectional view schematically showing the structure of the memory cell. An n-type InGaAs layer 13, on the substrate 1 providing physical support,
(InAlAs) _x (InGaAs) _1-x composition gradient layer 1
4, the n-type InGaAs layer 15 is laminated to form the roof-type potential diode D2. Resonant tunnel diodes RTD1 and RTD2 similar to those shown in FIG. 2A are formed on the diode D2.

FIG. 3B is a graph schematically showing the composition gradient in the diode D2 of the roof type potential.
The horizontal axis is the depth direction of the stack, and the vertical axis is (InAlAs)
_x represents the composition x of (InGaAs) _1-x . The composition x is I
It linearly increases from the interface with the nGaAs layer toward its midpoint.

Due to such a composition gradient, a potential as shown in FIG. 3C is formed. That is, in the composition gradient layer 14, the potential increases as the composition x increases. Therefore, the highest point of the potential barrier occurs in the central portion of the composition gradient layer 14.

By changing the position where the composition x takes the maximum value, the position of the highest point of the potential barrier can be changed, and the position of the highest point of the potential barrier can be changed to the n-type InG.
It can also be brought to the boundary with the aAs layer 13.

When a potential profile that makes it difficult for a direct current to flow in the reverse bias state, the same voltage application method as described with reference to FIG. 2 can be adopted for the write operation.

When the position of the highest point of the potential barrier is arranged in the central portion of the composition gradient layer, the IV characteristics are positive and negative and are substantially symmetrical. In either case, in the read operation, the change in the height of the potential barrier highest point becomes much larger due to the voltage application, as compared with the diode having the rectangular potential barrier. Therefore, the steepness of the IV characteristic is improved.

When the position of the highest point of the potential barrier is located in the central portion, the steepness of the IV characteristic of the diode is improved on both the positive polarity and the negative polarity of the voltage. Also, the stability of the operation is increased.

FIG. 4 shows the structure of a resonant tunnel diode memory according to another embodiment of the present invention. FIG. 4 (A) shows
It is sectional drawing which shows a structure roughly. In this embodiment, the read / write diode D3 sandwiched between the substrate 1 and the RTD1 and RTD2 is formed by the layer 16 having planar doping.

The planar doping layer 16 is made of n-type InG.
It is formed of an aAs layer, and the donor impurity 17, the acceptor impurity 18, and the donor impurity 19 are planarly doped in the layer.

From these impurities, the movable carrier escapes, and the immobile fixed charge remains at that position. Therefore, positive charges remain at the positions of the donor impurities 17 and 19,
Negative charges remain at the positions of the acceptor impurities 18. Such planar doping can be performed at a high concentration and is advantageous for forming a steep potential profile.

FIG. 4B shows a potential profile formed by such planar doping. The potential profile formed has the same tendency as the potential profile formed by the composition gradient. The technique of forming the potential barrier by the potential profile by the planar doping has an advantage that it is easier than the technique of controlling the potential profile by continuously controlling the composition ratio of the crystal layer.

FIG. 5 shows a negative resistance diode memory according to another embodiment of the present invention. FIG. 5A is a sectional view schematically showing the configuration of the negative resistance diode memory. In the present embodiment, the W layer 21 is formed on the substrate 1, and the n-type InGaAs layer 23 is laminated thereon. The W layer 21 forms a Schottky contact with the n-type InGaAs layer 22. For this reason, in the stack, FIG.
A potential profile as shown in (B) is formed.

Since the W layer 21 and the n-type InGaAs layer 22 form a Schottky contact, the n-type InGaAs layer 22
A depletion layer due to the Schottky barrier is formed inside. In the case of this configuration, when a positive voltage is applied to the W layer 21, the potential barrier due to the Schottky barrier is lowered and information can be read.

The control of the highest point of the potential barrier at this time is similar to that of the pn diode, and most of the applied voltage can be effectively utilized. In the case of writing information, it is difficult to inject a DC voltage from the W layer 21. Therefore, the charge injection may be performed by applying a pulse voltage as described in the embodiment of FIG.

In this embodiment, since the W layer 21 is made of a metal having a low resistivity, the resistance of the bit line is low and the operating speed is high. Moreover, since the barrier structure of the read / write diode is simple,
Simplifies the manufacturing process.

If a superconductor layer is used instead of the W layer 21, the resistance of the bit line can be further reduced. In this case, the word line can also be made of a superconductor such as Nb.

At low temperature, the resistance of the bit line and the word line becomes almost 0, and the voltage drop of the wiring is remarkably reduced,
It is possible to apply exactly the same voltage to all cells. Although the present invention has been described above with reference to the embodiments, the present invention is not limited thereto. For example, by separating the position of the highest potential barrier of the read / write diode connected to the interconnection point of the negative resistance diode from the position close to the connection point of the negative resistance diode to the position close to the bit line, It is sufficient that the height of the potential barrier highest point can be efficiently controlled by the voltage applied to the line. The spacer layer for separating the position of the highest point of the potential barrier from the conductive region may be formed of a plurality of layers.

It will be apparent to those skilled in the art that other various modifications, improvements, combinations and the like are possible.

[0076]

As described above, according to the present invention,
In the read / write diode of the negative resistance diode memory, the applied voltage is effectively applied to the potential barrier highest point by separating the position of the potential barrier highest point from the conductive region where the carrier starts, and the current changes sharply. Can be made. Therefore, information can be effectively read / written only from the selected memory cell.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the basic idea of the present invention.

FIG. 2 is a sectional view and a diagram showing a negative resistance diode memory according to an embodiment of the present invention.

FIG. 3 is a sectional view and a diagram for explaining a negative resistance diode memory according to another embodiment of the present invention.

FIG. 4 is a sectional view and a diagram for explaining a negative resistance diode memory according to another embodiment of the present invention.

FIG. 5 is a sectional view and a diagram for explaining a negative resistance diode memory according to another embodiment of the present invention.

FIG. 6 is a sectional view, a circuit diagram and a diagram for explaining a resonance tunnel diode memory according to a conventional technique.

FIG. 7 is a diagram for explaining a resonant tunneling diode memory according to a conventional technique.

[Explanation of symbols]

1, 4 Conductive region 2 Potential barrier region 3 Spacer layer 6, 10 n-type InGaAs layer 7, 9 InAlAs layer 8 InGaAs layer 10 Substrate 11 p-type InGaAs layer 12 n-type InGaAs layer 13, 15 n-type InGaAs layer 14 (InAlAs ) _X (InGaAs) _1-x layer (composition gradient layer) 16 planar doping layer 21 W layer 22 n-type InGaAs layer RTD resonant tunneling diode TD tunneling diode D diode

Claims (6)

[Claims] 1. Two negative resistance diodes (RTD1,
A memory element in which the RTDs 2) are connected in series so as to face each other, and a read / write diode (D) connected to an interconnection point of the two negative resistance diodes, which is a potential barrier for limiting the flow of carriers. Negative resistance diode memory comprising a read / write diode having a spacer layer (SP) which bears at least part of the applied voltage between the highest point and the conductive region on the starting side of the carrier. 2. The negative resistance diode memory according to claim 1, wherein the two negative resistance diodes are two resonant tunneling diodes formed on a common conductive layer. 3. The negative resistance diode memory according to claim 1, wherein the read / write diode has a semiconductor pn junction. 4. The read / write diode has a planarly doped region.
Negative resistance diode memory described. 5. The negative resistance diode memory according to claim 1, wherein the read / write diode has a Schottky contact. 6. A read / write diode having a contact between a semiconductor region and a superconductor.
Negative resistance diode memory described.