KR20120074187A - Swithching element operating bidirectionally and memory using the same - Google Patents

Abstract

PURPOSE: A switching element and a memory using a same are provided to have high integration and a great on/off ratio by implementing a switching element with a bidirectional driving property through a semiconductor process. CONSTITUTION: A oxide thin film(710) is deposited on a Si substrate(700). An N/P/N structure(720) is formed at etched parts of the oxide thin film. The N/P/N structure includes a first N-type doping layer(723), a second P-type doping layer(725) and a third N-type doping layer(727). The second P-type doping layer is performed a lower doping concentration than the first N-type doping layer and the third N-type doping layer. A P/N/P structure(730) includes a first P-type doping layer(733), a second N-type doping layer(735) and a third P-type doping layer(737).

Description

Switching elements operating in both directions and memories using these switching elements {SWITHCHING ELEMENT OPERATING BIDIRECTIONALLY AND MEMORY USING THE SAME}

The present invention relates to a switching element that operates in both directions, and a memory using the switching element, and more particularly, to the driving characteristics of the switching element included in the memory cell.

Although much research has been conducted to reduce the size of the device for high integration, the method of reducing the size of the device for high integration has reached a physical limit. Recently, researches to improve the degree of integration of devices by changing conditions other than the size of devices have been actively conducted. One of the techniques for improving density, one of the most studied ones, is a technology for improving the information storage capability of a device (Multi Level Cell, MLC) to store multiple information in one cell. MLC creates two states through electrical operation in one cell and saves only "0" and "1", and creates four states through electrical operation in one cell. 1 "," 10 "," 01 ", that is, the four types of information can be stored in one cell to increase the degree of integration. The MLC method is highly efficient because it improves the characteristics of each cell but the existing process size does not change.

Second is wafer bonding / die stacking. This is a method of increasing density by stacking wafers and dies through physical bonding after finishing the process for each wafer unit according to the conventional method. This method is also being applied and developed in many places as it can bring about an existing process as it is and improve the bonding technology to steadily increase the density.

The third method is to stack cells by layering a memory using a material that can be stacked in a 3D cell stacking method.

The stacking structure method has a similar aspect to the stacking method through wafer bonding method. However, in the case of wafer bonding, the larger the number of stacking layers, the larger the area occupied by the electrode pads of the substrate, and thus, there is a limit in that many layers cannot be stacked. There is a lot of research going on as a way to overcome this problem.

Of the three methods, the wafer bonding method is the most widely used method at present, but it is the most inefficient method in terms of cost. Therefore, the method of integrating devices using MLC (Multi Level Cell) method and 3D stacked structure in the direction of next-generation memory There is a lot of research going on.

1 illustrates a cross point memory structure.

Referring to FIG. 1, a memory element unit cell (hereinafter, referred to as a memory cell) using a variable resistance material may include a memory element 100, which is a resistance change material, and switching for selection of each memory element. The device 110 may include a switching element and a connection unit 120 connecting the memory element 100 and the switching element 110 to each other. A memory using a charge, such as a DRAM or a flash memory, must use a transistor as a switching device. However, in a memory device using a resistance change such as a resistive RAM (RRAM), a switching device 110 for selecting unit cells is selected. , Switching Element) can use transistor or diode element. In the case of using a diode as a switching element, the unit cell structure of the memory element is simpler than using a transistor, which enables not only a high density memory but also a high current density compared to the transistor, thereby overcoming the current reduction due to device scaling. have.

In general, the memory device is composed of word lines 130 and word lines crossing each other perpendicularly to each other, and bit lines 140 and 1D at the point where the word lines and the bit lines cross each other. Memory cells such as (Diode) -1R (Resistor) may be disposed. This structure of memory is referred to as cross point memory.

In order to realize the device directness required by the next-generation memory device, it is effective not only to scale the memory cells horizontally, but also to use a three-dimensional stacked memory structure. A three-dimensional stacked memory structure, which is formed by vertically stacking a resistive change memory device such as an RRAM and a diode as a switching device, can be easily implemented to maximize memory integration. However, in the case of a diode used as a switching element in a 3D stacked memory structure, a p / n junction diode using a high temperature process of a general Si substrate cannot be used. In addition, when the diode is used as the switching element of the memory cell, bidirectional driving characteristics cannot be obtained.

In order to reduce the cell size of the memory device, it is essential to reduce the size of the switching device included in the memory cell. However, conventional memories have a limitation in that they cannot be stacked because they use a single crystal silicon transistor as a switching element, so that the size of the memory cell is reduced by using a diode-like structure. Currently, switching devices used in a memory that uses a resistive memory device such as STT-MRAM (Spin-Tranfer Torque Magnetic Random Access Memory) should be able to flow current in both directions due to driving characteristics. However, P / N diodes installed on Si or Poly-Si substrates used as switching elements in conventional memories cannot be used in memories that must have bidirectional driving characteristics such as STT-MRAM due to the unidirectional driving characteristics. In the conventional Random Random Memory (RRAM) and Polymer RAM (PoRAM), metal oxide-based diodes such as TiO are used for bidirectional driving characteristics.However, metal oxide-based diodes are damaged due to high-temperature processes, resulting in damage to underlying layers. Due to the weak feasibility of the process, product production is difficult.

Accordingly, a first object of the present invention is to implement a switching device having a bidirectional driving characteristic for improving the degree of integration of the device.

In addition, a second object of the present invention is to implement a memory using a switching device having a bi-directional drive characteristic for improving the integration of the device.

A switching device having a bidirectional driving characteristic according to an aspect of the present invention for achieving the first object of the present invention described above in the first doped layer, the first doped layer doped with a first type of impurities on a semiconductor substrate A second doped layer doped with a second type of impurity to be stacked, wherein the second type of impurity is different from the first type of impurity, and doped with the first type of impurity to be deposited on the second doped layer Including a third doped layer, the doping concentration of the first doped layer and the third doped layer may have a higher doping concentration than the concentration of the second doped layer. In the switching device having the bidirectional driving characteristic, the first type of impurities may be N type impurities, and the second type of impurities may be P type impurities. In the switching device having the bidirectional driving characteristic, the first type of impurities may be P type impurities, and the second type of impurities may be N type impurities. The switching element having the bidirectional driving characteristic may have a doping concentration higher than that of the other doping layer among at least one of the doping concentrations of the first and third doping layers. The first doped layer, the second doped layer and the third doped layer may be formed by being doped into a group 4 element-based semiconductor substrate. The Group 4 element-based semiconductor substrate may be a semiconductor substrate made of at least one of Silicon, Poly-Silicon, Ge, SiGe, and GaAs.

In addition, a memory having a bidirectional driving characteristic according to an aspect of the present invention for achieving the above-described second object of the present invention comprises a first doped layer doped with a first type of impurity on the semiconductor substrate, the first doped layer A doped second type of dopant with a second type of impurity to be stacked, wherein the second type of impurity is different from the first type of impurity and doped with an impurity of the first type to be deposited on the second doped layer A memory cell having a switching element having a bidirectional driving characteristic comprising a third doped layer, and a resistive memory element connected to the third doped layer through a conductive connection structure, wherein doping concentrations of the first and third doped layers are included. May have a higher doping concentration than that of the second doped layer. In the memory having the bidirectional driving characteristic, the first type of impurities may be N type impurities, and the second type of impurities may be P type impurities. In the memory having the bidirectional driving characteristic, the first type of impurities may be P type impurities, and the second type of impurities may be N type impurities. In the memory having the bidirectional driving characteristic, a difference in doping concentration between the first doped layer and the third doped layer may be equal to or less than a predetermined value. The memory having the bidirectional driving characteristic may have a doping concentration of at least one of the doping concentrations of the first and third doping layers higher than that of the other doping layer. The first doped layer, the second doped layer and the third doped layer may be formed by being doped into a group 4 element-based semiconductor substrate. The Group 4 element-based semiconductor substrate may be a semiconductor substrate made of at least one of Silicon, Poly-Silicon, Ge, SiGe, and GaAs. The resistive memory device is a MTJ (Magetic Tunneling Junction) and can read and write data using a change in the magnetization direction of the variable ferromagnetic layer included in the MTJ. The resistive memory device may include one of a magnetic tunneling junction (MTJ), a resistive RAM (RRAM) memory device, a phase-change RAM (PRAM) memory device, and a polymer RAM (PoRAM) memory device. The memory having the bidirectional driving characteristic includes at least one word line and at least one bit line, and memory cells including the switching element and the resistive memory element share the same bit line but have different word lines, or The word lines may be shared but arranged with different bit lines. In the memory having the bidirectional driving characteristic, one end of the switching element may be connected to the bit line, and one end of the resistive memory element may be connected to a word line.

As described above, according to the switching device operating in both directions and the memory using the switching device according to the embodiment of the present invention, a high integration and excellent by implementing a switching device having a small size and bidirectional driving characteristics using a semiconductor process A memory having On / Off Ratio characteristics may be provided.

1 illustrates a cross point memory structure.
FIG. 2 is a conceptual diagram illustrating an MRAM memory cell using a magnetic tunneling junction (MJT) as a memory device and a diode structure as a selection device.
FIG. 3 is a conceptual diagram illustrating a spin transmission torque phenomenon of a magnetic tunneling junction (MTJ), which is one of resistive memory devices.
4 is a conceptual diagram and graph illustrating bidirectional driving characteristics of an STT-MRAM having bidirectional driving characteristics according to an embodiment of the present invention.
5 is a graph showing the bidirectional driving characteristics of the MTJ included in the STT-MRAM as a relationship between current and resistance.
6 is a graph illustrating an operating characteristic of an RRAM, which is one of resistive memory devices.
7 is a conceptual diagram illustrating a switching device for bidirectional driving according to an embodiment of the present invention.
8 is a conceptual diagram illustrating a process of fabricating an STT-MRAM using an N / P / N structure having bidirectional driving characteristics as a switching device according to an embodiment of the present invention.
9 is an IV characteristic graph showing bidirectional driving and reading characteristics of a switching device having bidirectional driving characteristics according to an embodiment of the present invention.
FIG. 10 is an IV characteristic graph showing bidirectional driving and reading characteristics of a switching device having bidirectional driving characteristics according to an embodiment of the present invention.
11 to 13 are diagrams illustrating a bonding concept and a band diagram when a bias is applied to an N / P / N structure according to an embodiment of the present invention.
14 is a conceptual diagram illustrating an STT-MRAM array according to an embodiment of the present invention.
15 is a conceptual diagram illustrating an RRAM array according to an embodiment of the present invention.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Hereinafter, in an embodiment of the present invention, for convenience of description, STT-MRAM (Spin-Tranfer Torque Magnetic Random Access Memory) and RRAM (Resistive RAM) will be described as examples, but the bidirectional driving characteristics disclosed herein will be described. The switching element may be used in other types of memory using a resistive memory element, such as PRAM (Phase-Change RAM), PoRAM (Polymer RAM), and the like. A memory using a switching element having such a bidirectional driving characteristic is also within the scope of the present invention. Included.

In addition, according to an embodiment of the present invention, a memory element unit cell (hereinafter, referred to as a memory cell) using a variable resistance material may be a memory element that is a resistance change material and a memory element. It has a structure including a switching element.

FIG. 2 is a conceptual diagram illustrating an MRAM memory cell using a magnetic tunneling junction (MJT) as a memory device and a diode structure as a selection device.

In the conventional magnetic random access memory (MRAM), a transistor is used as a switching element. However, the MRAM disclosed in FIG. 2 uses a diode structure as a selection element, and thus a memory cell size is larger than that of a conventional MRAM using a transistor as a selection element. Can be reduced.

Referring to FIG. 2, the MRAM may be implemented in a structure in which the MTJ 200 is stacked on the P-type impurity region 210 of the PN diode.

The MRAM dopes the N + region 220 to the semiconductor substrate 230 and forms the P-N diode by doping the P-type impurity region 210 on the line of the N + region 220. The barrier conductive layer 215 is stacked on the P-type impurity region 210, and the fixed ferromagnetic layer 201, the tunnel junction layer 203, and the variable ferromagnetic layer 205 are disposed on the barrier conductive layer 215. The MTJ 200 may be stacked, and a word line 207 may be formed on the MTJ 200.

2 shows the operation of the MRAM when the magnetization directions of the fixed ferromagnetic layer 201 and the variable ferromagnetic layer 205 are the same, and the lower end of FIG. 2 shows the fixed ferromagnetic layer 201 and the variable ferromagnetic layer 205. This shows the operation of the MRAM when the magnetization directions are different.

The MRAM cell may store data of logic "1" or logic "0" according to the magnetization direction of the variable ferromagnetic layer 205 of the MTJ 200. The conceptual diagram shown at the top of FIG. 2 shows a magnetization state that stores logic "1", and the conceptual diagram shown at the bottom of FIG. 2 shows a magnetization state that stores logic "0".

The write operation of the MRAM is performed by applying a voltage of a predetermined level for generating a write current through the word line 207 while a constant trigger voltage is applied to the PN diode. In this case, the magnetization polarity of the variable ferromagnetic layer 205 of the MTJ 200 is determined according to the polarity of the write current according to the level of the voltage applied to the word line 207. According to the polarity of the current supplied to the word line 10, the MRAM cells having the upper and lower structures of FIG. 2 may store logic “1” and logic “0”, respectively.

The read operation of the MRAM cell is performed by sensing the amount of current adjusted according to the magnetization polarity direction of the variable ferromagnetic layer 205 of the MTJ 200. Specifically, the amount of current I1 flowing between the word line 207 and the PN diode varies depending on the magnetization polarity direction of the MTJ 200, and thus the amount of current sensed in the MRAM cell varies. That is, when a constant trigger voltage is applied to the word line 207 and a constant sensing voltage is applied to the PN diode, the tunneling current I1 flows to the MTJ 200. At this time, when the magnetization polarity directions of the fixed ferromagnetic layer 201 and the variable ferromagnetic layer 205 are in the same direction as in the upper end of FIG. 2, the amount of current I1 is large, and the fixed ferromagnetic layer 201 and the variable ferromagnetic layer 205 are separated. If the magnetization polarity direction is reversed as in the bottom of FIG. 2, the amount of current I1 is small. The magnetization direction of the variable ferromagnetic layer 205 may be sensed by sensing a large amount and a small amount of current flowing in the MRAM cell, and the stored information may be sensed.

Referring to FIG. 2, as a switching device, a diode is implemented based on a Si semiconductor substrate and a resistive memory device such as MJT is connected to an upper portion of the diode. In the conventional MRAM memory device, a magnetic field is applied from the outside to change the magnetization direction of the variable ferromagnetic layer 205 to use a current change according to the change of the magnetization direction.

In the case of STT-MRAM, unlike the MRAM, a method of directly changing the magnetization direction of the variable ferromagnetic layer by applying a current to the MTJ element, which is a resistive memory element, is directly transferred using a spin-transfer torque (STT) phenomenon. Using direct magnetization redirection, STT-MRAM can be used as a memory to replace the next generation DRAM because of its excellent cycling characteristics and high-speed read characteristics. In particular, the vertical STT-MRAM is also attracting attention as a next-generation DRAM replacement device because it reduces the current density decrease due to the decrease in cell size, which is advantageous in terms of scalability.

In order to implement the STT-MRAM using the spin transfer torque method, a device having bidirectional driving characteristics must be used as the switching element. Therefore, the P / N diode installed in the Si or Poly-Si substrate, which is the switching element of the MRAM shown in FIG. It cannot be used because of its driving characteristics.

In conventional RRAM (Resistance Random Access Memory) and PoRAM (Polymer RAM), metal oxide-based diodes such as TiO are used for bidirectional driving characteristics.However, metal oxide-based diodes have a lower layer during semiconductor processing due to high temperature processes. Due to the damage and weakness of feasibility in the semiconductor process, the production of the product is difficult.

FIG. 3 is a conceptual diagram illustrating a spin transmission torque phenomenon of a magnetic tunneling junction (MTJ), which is one of resistive memory devices.

Referring to the top of FIG. 3, the spin of the conduction electrons is filtered while current flows through the NM / FM / NM structure composed of nonmagnetic metal (NM) and magnetic metal (FM). The probability of reflection at the interface between the magnetic and magnetic metals depends on the spin direction and this phenomenon is called spin-filtering. As a result of spin filtration, the spin direction of the conduction electrons is aligned with the magnetization direction of FM.

Referring to the bottom of FIG. 3, in the spin valve structure consisting of NM / FM1 / NM / FM2 / NM, the flow of spin filtered by FM1, that is, the spin-polarized current, is non-parallel to FM1. Collinear) Once again filtered by FM2 with magnetization. In the second spin filtration process, the spin direction of the conduction electrons is aligned with the magnetization direction of FM2. Since the spin angular momentum must always be preserved, the amount of change in the spin angular momentum of the conduction electrons is transmitted to the magnetization of the FM2, thereby applying a torque, that is, a spin transfer torque.

Spin transfer torque enables several types of current-induced magnetization behavior, such as magnetization reversal, magnetization precession motion, and domain wall motion.

The current-driven magnetization inversion scheme can now be used as a new recording scheme for magnetic random access memory (MRAM). Before the spin transfer torque was proposed, a field-induced magnetization switching (FIMS) method of inverting the magnetization direction by applying only a magnetic field from the outside has been adopted as a recording method of MRAM. However, in order to go to the highly integrated MRAM, the size of the magnetic cell is continuously reduced. In the conventional FIMS, there is a critical problem that the required write current is continuously increased as the size of the magnetic unit decreases. In the case of STT-MRAM adopting the spin transfer torque as a new recording method, the size of the write current also decreases with the decrease of the magnetic cell size, and thus can be used for high density memory.

)를 예측한다. STT-MRAM uses the same read method as the conventional MRAM technology, while adopting a current-driven magnetization reversal as a writing method, instead of applying a magnetic field. The spin transfer torque theory based on the Macrospin concept is based on the following equation (1).

Predict

[Equation 1]

는 고유 감쇠 상수,

는 스핀 분극화 인자,

는 포화 자화량,

는 자기 단위 부피,

는 이방성 자기장을 의미한다.

Is the intrinsic damping constant,

Is the spin polarization factor,

Is the saturation magnetization,

Is the magnetic unit volume,

Means anisotropic magnetic field.

Since the inversion current is proportional to the volume of the magnetic cell, the current-driven magnetization inversion scheme provides a scrambling writing method to the STT-MRAM. In addition, the current-driven magnetization inversion scheme solves the problem of write selectivity of the existing MRAM based on the magnetic field-driven magnetization inversion.

In the magnetic field driving magnetization inversion, a cell located at the intersection of two lines using two orthogonal current lines is selected to be magnetized inversion by a current simultaneously applied to two orthogonal lines. The cells located in each current line are necessarily half-selected except one selected cell located at the intersection. If the distribution of write current across each half-selected cells is not very narrow, unintended magnetization reversal may occur, which is directly linked to memory malfunction.

However, in the current driven magnetization inversion, since the current flows only through the selected cell, there is no semi-selected cell, and thus, there is no writing error related to the selection sensitivity problem, thereby improving performance over the conventional magnetic field driving magnetization inversion method.

4 is a conceptual diagram and graph illustrating bidirectional driving characteristics of an STT-MRAM having bidirectional driving characteristics according to an embodiment of the present invention.

4 illustrates a magnetic tunneling junction (MTJ) structure including a variable ferromagnetic layer 400, a tunnel junction layer 410, and a fixed ferromagnetic layer 420.

방향일 경우, 가변 강자성층(400)의 자화 방향이 스핀 전달 토크를 받아 고정 강자성층(420)의 방향과 동일한 방향으로 변화하여 저항이 감소하여 전류가 흐르는 것을 나타낸 개념도이다. Referring to Figure 4, the upper left is the current

In the direction, the magnetization direction of the variable ferromagnetic layer 400 receives the spin transfer torque and changes in the same direction as the direction of the fixed ferromagnetic layer 420 to decrease the resistance to flow a current.

방향일 경우, 가변 강자성층(400)의 자화 방향이 스핀 전달 토크를 받아 고정 강자성층(420)의 방향과 반대 방향으로 변화하여 저항이 증가하여 전류가 흐르지 않는 것을 나타낸 개념도이다. The upper right is the current

In the direction, the magnetization direction of the variable ferromagnetic layer 400 receives the spin transfer torque and changes in a direction opposite to that of the fixed ferromagnetic layer 420 to increase resistance and thus prevent current from flowing.

5 is a graph showing the bidirectional driving characteristics of the MTJ included in the STT-MRAM as a relationship between current and resistance.

방향으로 계속 증가할 경우 특정한 임계값 이상이 되면 가변 강자성층(400)의 자화 방향이 고정 강자성층(420)의 자화 방향과 반대 방향이 되고 저항이 급격히 증가한다. 5, the current is

If it continues to increase in the direction or more than a certain threshold value, the magnetization direction of the variable ferromagnetic layer 400 becomes the opposite direction of the magnetization direction of the fixed ferromagnetic layer 420 and the resistance increases rapidly.

인 경우, 가변 강자성층(400)의 자화 방향이 고정 강자성층(420)의 자화 방향과 동일하여 전류를 잘흘릴 수 있게 된다. On the contrary

In this case, the magnetization direction of the variable ferromagnetic layer 400 is the same as the magnetization direction of the fixed ferromagnetic layer 420 so that the current can flow well.

That is, the STT-MRAM should be able to change the state of data by making the direction of the current flowing in the MTJ different. Therefore, the switching element used for STT-MRAM must have bidirectional driving characteristics. When the transistor is used for the switching element to have bidirectional driving characteristics, the size of the switching element included in the memory cell increases, so that the size of the memory cell can be reduced even if the size of the magnetic cell is reduced by using an STT-MRAM structure that directly applies the current to the MTJ. There is a limit to shrinking.

6 is a graph illustrating an operating characteristic of an RRAM, which is one of resistive memory devices.

RRAM is composed of simple metal / insulator / metal (MIM, Metal / Insulator / Metal) structure, unlike DRAM and flash memory, which use a charge storage capacitor. Use resistance switching phenomenon.

FIG. 6 is a graph showing current-voltage characteristic curves of a typical RRAM classified into two types according to characteristics of a switching operation.

There are two types of RRAM that exhibit unidirectional and bidirectional characteristics.

The left graph of FIG. 6 shows current-voltage operating characteristics of an RRAM having unipolar characteristics, and the right graph of FIG. 6 shows current-voltage operating characteristics of an RRAM having bipolar characteristics.

Both types of RRAM can have two different resistance states under one voltage. Once the state has changed, it remains in that state even when no external power is supplied until the next switching occurs. In general, a small resistance state is called 'ON', a large state is called 'OFF', and two states are used to store two bits of information.

Unipolar RRAMs with unidirectional characteristics can switch both states at one polarity. That is, only by changing the magnitude of the voltage at one polarity voltage, the operating state of the RRAM can be switched to ON and then to OFF.

Bipolar RRAMs, on the other hand, require a change to the other polarity voltage, that is, a polarity change, in order to switch from one polarity voltage to ON and then to OFF. Both types of RRAM have their advantages and disadvantages. Typically, unipolar RRAMs can operate with only one polarity, which has advantages in terms of design and power consumption over bipolar RRAMs. In addition, the information stored once does not change over time, compared to bipolar RRAM.

Bipolar RRAMs have advantages in comparison to unipolar RRAMs in that they have a small dispersion and operate at relatively small currents. Next-generation resistive memory, PRAM, RRAM, and MRAM, has a current flowing through the cell when a voltage is actually applied, unlike the operation mechanism of conventional commercially available memory that accumulates charges. Should be absolutely small.

In other words, in order to integrate the memory with high current, it must be possible to drive with a small current and the polarity of the selection device is required. Therefore, a switching device of a memory including a resistive memory device such as an STT-MRAM or an RRAM can provide bidirectional current to the memory device. It should have a bidirectional drive characteristic.

7 is a conceptual diagram illustrating a switching device for bidirectional driving according to an embodiment of the present invention.

Referring to FIG. 7, a memory cell according to an embodiment of the present invention may include a Si substrate 700, an oxide thin film 710, and an N / P / N structure 720 from below.

In addition, in one embodiment of the present invention, for convenience of description, the substrate of the memory cell is assumed to be a Si substrate, but a semiconductor including Poly-Silicon, Ge, GaP, GaAs, SiGe, etc., which is a Group 4 element-based semiconductor substrate, in addition to the Si substrate, is used. The substrate may also be used as a substrate for forming a memory cell according to an embodiment of the present invention.

An oxide thin film 710 may be deposited on the Si substrate 700 and the portion for forming the N / P / N structure 720 according to an embodiment of the present invention may be etched.

An N / P / N structure 720 may be formed in a portion etched in the oxide thin film 710.

The N / P / N structure 720 is a structure in which an N-type first doping layer 723, a P-type second doping layer 725, and an N-type third doping layer 727 are sequentially stacked, so that current is bidirectionally generated. It has a property that can flow and can change the current characteristics flowing according to a specific voltage according to the degree of doping of the semiconductor.

Hereinafter, although the embodiment of the present invention describes using the N / P / N structure 720 as the switching element of the memory cell, the P / N / P structure may also be used as the switching element.

In addition, the N / P / N structure 720 (or P / N / P) shown in FIG. 7 uses the N / P / N structure 720 as a switching device for convenience of description, and exhibits a bidirectional driving characteristic. As shown in FIG. 7, the N / P / N structure of the memory cell is different from the embodiment having the N / P / N structure of the vertical structure shown in FIG. Can be used as

Hereinafter, in an embodiment of the present invention, the N-type doped layer 723 of the lower portion of the N / P / N structure 720, the P-type layer of the doped layer in the middle P type, P type The second doped layer 725 and the N-doped layer on the top may be used in the same meaning as the term N-type third doped layer 727. In the same manner, the P-type first doped layer 733 may be a P-type doped layer below the P / N / P structure 730, and the N-type second doped layer may be an intermediate N-doped layer ( 735, the upper P-doped layer may be used in the same sense as the term P-type third doped layer 737.

7 shows the doping concentration of the N-type third doping layer 727 and the N-type first doping layer 723 higher than that of the P-type second doping layer 725 in the N / P / N structure. Doping implements a switching device having bidirectional driving characteristics.

7 illustrates a memory structure using the N / P / N structure 720 as the switching element, and a lower left portion of FIG. 7 illustrates the memory structure using the P / N / P structure 730 as the switching element. .

Referring to the upper left of FIG. 7, in the switching element of the N / P / N structure 720, the doping concentration of the N layer, which is the N type third doping layer 727 and the N type first doping layer 723, is the same. The doping concentration (hereinafter, the same doping concentration range refers to a concentration range including a range of concentration errors occurring in manufacturing) and the P type second doping layer 725, which is an intermediate doping layer, is an N type first doping layer. 723 and the N-type third doping layer 727 may be implemented at a lower doping concentration.

Referring to the lower left of FIG. 7, in the same manner as the N / P / N structure 720, in the case of the switching element of the P / N / P structure 730, the P type first doping layer 733 and the P type agent are made. The doping concentration of the P layer, which is the three doping layer 737, is doped at the same concentration (hereinafter, the same doping concentration refers to a concentration range including a range of concentration errors occurring in manufacturing) and the N type second intermediate doping layer. The doped layer 725 may be implemented at a lower doping concentration than the upper and lower doped layers.

When using an N / P / N structure or a P / N / P structure by using the difference in concentration between layers according to an embodiment of the present invention, it may have a bidirectional driving characteristic that the diode could not have when the diode was used as a switching element. The memory can be driven by the current, so that the memory can be highly integrated.

7 is a conceptual diagram illustrating a switching device having bidirectional driving characteristics by varying concentrations of an upper doping layer and a lower doping layer.

Referring to the upper right of FIG. 7, the N-type third doping layer 747 and the N-type first doping layer 743 are higher than the P-type second doping layer 725 as the N / P / N structure 740. Doped to concentration. The N-type third doped layer 747 and the N-type first doped layer 743 may be asymmetrically doped at relatively different concentrations.

In the same manner, referring to the lower right side of FIG. 7, the P-type third doping layer 757 and the P-type first doping layer 753 may be the N-type second doping layer (P / N / P structure 750). Doped to a concentration higher than 755). The P-type third doped layer 757 and the P-type first doped layer 753 may be asymmetrically doped at different concentrations.

When the same doping concentration is used for the upper and lower doping layers, the symmetrical read characteristics are used. However, when a different doping concentration is used for the upper and lower doping layers, the memory may have an asymmetric read characteristic.

In the resistive memory device, in addition to bidirectional driving characteristics, asymmetric read operation characteristics are important requirements. When reading a specific cell at + bias, the other cells connected to the bit line should be biased in the reverse direction and there should be no leakage current.

That is, a switching device characteristic in which a driving current flows at a specific voltage and a +/- on / off ratio is more than a predetermined ratio at a read voltage is required.

When the memory has an asymmetric read characteristic by using different doping concentrations for the upper and lower doped layers, the on / off ratio of the memory having the bidirectional driving characteristic is higher than that of the symmetric read characteristic, which is relatively better. It may have a memory operation characteristic.

That is, according to an embodiment of the present invention, a switching device having bidirectional driving and asymmetric read characteristics may be implemented by adjusting the doping concentrations of the upper and lower layers or the doping concentrations of the middle layer.

According to the exemplary embodiment of the present invention, the switching element having the bidirectional driving characteristic may have an N / P / N structure or a P / N / P structure, and in the case of an N / P / N structure according to the stacking order, the N-type first It may have a doping layer, a second P-type doping layer, an N-type third doping layer, in the case of a P / N / P structure P-type first doping layer, N-type second doping layer, P-type third doping layer Can have

In the following embodiment of the present invention, a concept including a first doping layer, a second N-type second doping layer, and a second P-type doping layer in a concept including an N-type first doping layer and a P-type first doping layer The term "third doping layer" may be used in a concept including a doping layer, an N-type third doping layer, and a P-type third doping layer.

8 is a conceptual diagram illustrating a process of fabricating an STT-MRAM using an N / P / N structure having bidirectional driving characteristics as a switching device according to an embodiment of the present invention.

8 illustrates a process of fabricating an STT-MRAM using an Si substrate as a semiconductor substrate and an N / P / N structure as a switching device having bidirectional driving characteristics. However, such a structure is shown as one embodiment for convenience of description, and unless the semiconductor substrate is released from the essence of the present invention, the semiconductor substrate is a poly-silicon, ge, gap, gaas, sige, SiGe, which is a group 4 element-based semiconductor substrate in addition to the Si substrate. The semiconductor substrate may be used as a substrate for forming a memory cell according to an embodiment of the present invention, and the switching element may also use a P / N / P structure.

FIG. 8 illustrates a process of fabricating an STT-MRAM using MTJ as a memory device for convenience of description, and it is also possible to implement a memory such as an RRAM PRAM other than an STT-MRAM using a resistive memory device other than MTJ. Do.

Referring to FIG. 8, an oxide thin film 803 is deposited on a Si substrate 800. The deposited oxide thin film is etched to form a region for forming a switching device having bidirectional driving characteristics. Poly silicon 805 is deposited on the etched region by low pressure chemical vapor deposition (LPCVD). The deposited polysilicon is planarized by a chemical mechanical polishing (CMP) process. The flattened polysilicon is implanted with N type impurities by ion implantation to form a lower doped layer 805 and then annealing is performed. The intermediate doped layer 807 is formed by doping with P type impurities of a doping type opposite to the lower doped layer. Thereafter, the upper doping layer 809 is formed by doping with an N type material using the same doping type as the lower doping layer to form a switching device having an N / P / N structure.

It is also possible to implement a switching element of the P / N / P structure in the same manner.

According to one embodiment of the present invention, the first doped layer and the third doped layer may have a higher doping concentration than the second doped layer.

The first doped layer and the third doped layer have the same doping concentration range (hereinafter, the same doping concentration range refers to a concentration range including a range of concentration errors occurring in manufacturing) or the first doping layer and the third doping layer It can have different doping concentration ranges.

When the first doped layer and the third doped layer have different doping concentration ranges, the memory device according to an embodiment of the present invention may have an asymmetric read characteristic.

Finally, an STT-MRAM memory cell having a bidirectional driving characteristic may be implemented by connecting an MTJ (811, Magnetic Tunneling Junction) device on the formed switching device (850).

The MTJ device is a resistive memory device, and according to an embodiment of the present invention, a memory cell using a switching device having bidirectional driving characteristics may be implemented by using other resistive memory devices such as RRAM and PRAM instead of MTJ.

The above-described method of manufacturing a memory having a bidirectional driving characteristic is an embodiment for implementing a memory having a bidirectional driving characteristic, and a manufacturing process of a memory having a bidirectional driving characteristic is added or deleted unless it is omitted from the essence of the present invention. It is also possible that the fabrication process of the memory having the bidirectional driving characteristic is implemented by a process method different from the above-described process.

9 is an I-V characteristic graph showing bidirectional driving and reading characteristics of a switching device having bidirectional driving characteristics according to an embodiment of the present invention.

In the N / P / N structure shown in the graph, the upper N-type doping layer and the lower N-type doping layer have the same doping concentration, and the intermediate P-type doping layer has lower concentration than the upper N-type doping layer and the lower N-type doping layer. In case of using N / P / N structure as switching structure, it shows IV characteristics.

The left graph of FIG. 9 shows I-V characteristics on a linear scale when the upper and lower doping layers have the same doping concentration. The arrow direction shown in the left graph of FIG. 8 indicates that the I-V characteristic curve changes as the concentration of the intermediate P-type doped layer changes.

In the right graph of FIG. 9, when the upper and lower doping layers have the same doping concentration, I-V characteristics are shown on a log scale. The arrow direction shown in the graph on the right of FIG. 8 indicates that the I-V characteristic curve changes with the change of the concentration of the intermediate P-type doped layer.

When the upper and lower N-type doping layers have the same concentration, they may have a symmetrical I-V characteristic curve.

10 is an I-V characteristic graph showing bidirectional driving and reading characteristics of a switching device having bidirectional driving characteristics according to an embodiment of the present invention.

The left side of FIG. 10 shows I-V characteristics on a log scale when the upper and lower doped layers have different doping concentrations.

Referring to the left graph of FIG. 10, when the driving voltage is 2 V, a current of about A flows, so that a read operation may be performed in the memory.

(여기서,

는 읽기 전압 2V임.)을 인가하고, 비선택된 셀의 워드 라인에는 0 V를 인가할 수 있다. 이러한 전압의 인가로 비선택된 셀에는 1V의 전압이 인가되고 On/Off Raio는

값을 가질 수 있다.When performing a read operation on the selected cell, the bit line of the unselected cell

(here,

Is a read voltage of 2V), and 0V may be applied to a word line of an unselected cell. The voltage of 1V is applied to the unselected cells by the application of this voltage, and On / Off Raio

It can have a value.

이며 비선택된 메모리셀에는 약

정도의 전류가 흐르게 된다. 본 발명의 일실시예에 따른 메모리 소자의 On/Off Ratio값이

일 경우, 스위칭 소자로써 트랜지스터를 사용한 경우의 On/Off Ratio 값과 동일한 범위의 값이다.That is, in the memory according to the embodiment of the present invention, when the voltage of 1V is applied to the non-selected memory cell and the voltage of 1V is applied, the On / Off Ratio is increased.

And unselected memory cells are about

This is enough current to flow. On / Off Ratio value of the memory device according to an embodiment of the present invention

In this case, the value is in the same range as the On / Off Ratio value when the transistor is used as the switching element.

11 to 13 are diagrams illustrating a bonding concept and a band diagram when a bias is applied to an N / P / N structure according to an embodiment of the present invention.

Referring to FIG. 11, a first N region and a second N region, which are highly doped N + regions of both ends, are disclosed, and a lightly doped P region is disclosed.

In equilibrium with no bias applied across the N + region, the Fermi level E _F remains at the same level regardless of the region. If the doping concentrations of the first N region and the second N region are the same, the energy levels E _C1 and E _C2 of the conduction bands of the two N regions are the same.

In addition, the depletion region appearing at the junction of the two N regions and the P region has a low width in the N region heavily doped and a wide width in the P region heavily doped. This is due to the interaction of the electrostatic force generated by the recombination and recombination of the electrons and holes by the junction.

In addition, the above-described junction structure may be modeled as two diodes connected in the reverse direction. That is, one diode is configured between the first N region and the P region, one diode is configured between the P region and the second N region, and the two diodes have a common anode connected, and the cathode is connected at both ends of the device. It is modeled as a constituent aspect.

Referring to FIG. 12, when a bias is applied to the first N region and the second N region, a reverse bias is applied to the first N region and the P region, and a positive bias is applied between the P region and the second N region.

The applied reverse bias increases the energy band gap E _CP -E _CN1 or E _VP -E _VN1 between the first N region and the P region. This is due to the reverse bias of the Fermi energy level E _FP in the P region. And the difference between the Fermi energy levels E _FN1 in the first N region. Further, the gap of the energy band between the P-region and the N region 2 by the positive bias (E -E _{CN2 CP} or _VP E -E _VN2) is reduced.

In addition, the width of the depletion region at the junction increases or decreases with the application of the bias. That is, the depletion region of the first N region and the P region to which the reverse bias is applied extends toward the bulk. On the other hand, the depletion region of the P region to which the positive bias is applied and the second N region is reduced toward the junction.

In the above structure, a reverse bias is applied between the first N region and the P region. Therefore, no current flows due to the application of the bias. Although the positive bias is applied to the P region and the second N region, the reverse bias is applied to the first N region and the P region in series connection thereto, so that current flow is blocked.

However, if the magnitude of the bias voltage applied in the above-described structure is continuously increased, breakdown may occur due to reverse bias between the first N region and the P region. This is due to the zener breakdown phenomenon that occurs at normal low voltages. In other words, the reverse bias allows the energy bands to intersect at relatively low voltages. This means that the conduction band of the first N region and the valence band of the P region cross each other. Thus, the empty energy state of the conduction band of the first N region and the filled energy state of the valence band of the P region are arranged side by side at the same or the same height. In addition, if the width of the potential barrier due to the depletion region separating the two bands is sufficiently narrow, electron tunneling occurs. That is, tunneling of electrons from the valence band of the P region to the first N region occurs, and generation of reverse current due to reverse bias occurs. Therefore, a current is generated from the first N region to the P region according to the tunneling phenomenon. The above phenomenon corresponds to a section in which the amount of current sharply increases as the voltage increases in FIG. 10.

This can be modeled as a connection of a zener diode connected in reverse with respect to the bias applied and a diode disposed in forward direction in series with it. That is, the first N region and the P region where the tunneling phenomenon occurs are modeled as a zener diode, and the P region and the second N region where the positive bias is applied are modeled as the diodes connected forward.

Referring to FIG. 13, when the magnitude of the bias applied continuously is increased, the P region is filled with the depletion region. That is, the concentration gradient of the holes constituting the original P region does not appear, and a depletion region in which only ions exist while the carrier is removed appears between the first N region and the second N region. This means that the P region is completely pinched off. Therefore, even if the size of the bias is increased between the first N region and the second N region, an increase in current does not occur.

When this is explained through an energy band diagram, the energy barrier E _CN2 -E _CN1 between the first N region and the second N region is greatly increased by the applied bias, and the bulk region in the P region is completely removed. Only a linear increase in the band occurs. In addition, due to the above-described breakdown phenomenon, electrons in the valence band of the second N region move through the conduction band of the first N region through tunneling. Therefore, the movement of the current occurs according to the bias applied. However, since there is a pinch-off region between the two N regions, even if an additional bias increases, the increase in the amount of current is not proportional. This means that at pinch-off, the amount of current is saturated.

The above-described configuration may be modeled as one zener diode connected in the reverse direction. That is, it is modeled as a Zener diode in which the first N region forms a cathode and the second N region forms an anode.

In addition, the above-described N / P / N structure can be utilized as a bidirectional switching device. For example, when using a state modeled as a configuration of one zener diode by applying a relatively high voltage for turn-on, the N / P / N device may be turned on for a predetermined applied voltage and supply a predetermined saturation current.

In addition, when a low voltage is applied, the N / P / N device may be set to a state where tunneling operation does not occur. That is, a reverse bias is applied at the P / N junction, and thus the off state can be realized by blocking the flow of current.

In addition, the above-described structure has the characteristic of bidirectional switching. 11 to 13 illustrate that the anode of the power source is connected to the first N region, the cathode of the power source is connected to the second N region, but the cathode of the power source is connected to the first N region, and the power source is connected to the second N region. A configuration in which the anodes are connected can be formed. When the power source is connected in the opposite direction to FIGS. 11 to 13, the modeling of the circuit is also reversed in polarity. However, only the polarity is different, and the aspects of the operation will be the same.

14 is a conceptual diagram illustrating an STT-MRAM array according to an embodiment of the present invention.

Referring to FIG. 14, the STT-MRAM array includes a plurality of word lines WL1 to WL4 (1100, 1103, 1105, and 1107), a plurality of bit lines BL1 to BL3 (1110, 1113, and 1115), and an STT-MRAM cell 1120. It may include.

The STT-MRAM cell may use the MTJ 1123 as a memory element and may have an N / P / N structure 1125 or a P / N / P structure as a switching element.

The MTJ 1123 and the N / P / N structure 1125 may be connected in series and each end thereof may be connected to the word lines 1100, 1103, 1105, and 1107 and the bit lines 1110, 1113, and 1115.

In FIG. 14, only the memory cell structure using the N / P / N structure 1125 as the switching element is illustrated for convenience of description.

In the bidirectional driving N / P / N structure 1125 according to an embodiment of the present invention, the doping concentration of the N-type third doping layer and the N-type first doping layer is higher than that of the P-type second doping layer. May have a concentration.

The concentration of the N-type first doped layer and the N-type third doped layer may be in the same range or may have a higher concentration of one of the N-type first doped layer or the N-type third doped layer.

N / P / N structures of a plurality of STT-MRAM cells may be included in the same bit line, and a plurality of MTJs may be included in the same word line.

In the case where a specific cell 1127 including the MTJ 1123 and the N / P / N structure 1125 is selected to write data, the driving voltage 2V is applied to the bit line 1110 of the specific cell 1127 and the specific cell is written. The magnetization direction may be reversed by applying a voltage of 0 V to the word line 1100 of the device to flow a current equal to or greater than the magnetization inversion threshold current value.

의 전압을 걸고 비선택된 셀의 워드 라인(1103, 1105, 1107)에는

의 전압을 인가하여 비선택된 셀로 많은 전류가 흐르는 것을 방지하여 On/Off Ratio를 높힐 수 있다.Bit lines 1113 and 1115 of unselected cells except for specific cells 1127 are included in the bit lines 1113 and 1115.

Word lines 1103, 1105 and 1107 of unselected cells

The on / off ratio can be increased by preventing a large current from flowing to the unselected cells by applying a voltage of.

In addition, when the specific cell 1127 is selected to erase data, the magnetization is performed by applying a driving voltage of 2V to the word line 1100 of the specific cell 1127 and applying a voltage of 0V to the bit line 1110 of the specific cell. The magnetization direction can be reversed by flowing a current equal to or greater than the inversion threshold current value.

의 전압을 걸고 비선택된 셀의 비트 라인(1113, 1115)에는

의 전압을 인가하여 비선택된 셀로 많은 전류가 흐르는 것을 방지하여 On/Off Ratio를 높힐 수 있다.Word lines 1103, 1105, and 1107 of unselected cells except for specific cells 1127 are included in the word lines 1103, 1105, and 1107.

Bit lines 1113 and 1115 of unselected cells

The on / off ratio can be increased by preventing a large current from flowing to the unselected cells by applying a voltage of.

That is, a memory according to an embodiment of the present invention includes a plurality of word lines and bit lines, and memory cells including a switching element and a resistive memory element share the same bit line but have different word lines or the same word line. Can be arranged with different bit lines. In addition, one end of the switching element may be connected to the bit line and one end of the resistive memory element may be connected to the word line.

15 is a conceptual diagram illustrating an RRAM array according to an embodiment of the present invention.

Referring to FIG. 15, the RRAM array may include a plurality of word lines WL1 to WL4 1200, 1203, 1205 and 1207, a plurality of bit lines BL1 to BL3 1210, 1213 and 1215, and an RRAM cell 1220. have.

The RRAM cell 1220 is a memory device, in which an RRAM device 1223 and a N / P / N structure 1225 are connected in series and each end thereof has word lines 1200, 1203, 1205, 1207 and bit lines 1210, 1213, and 1215.

The N / P / N structure 1225 may be modeled with the circuits disclosed in FIGS. 11 to 13 according to voltage differences applied between bit lines and word lines. Thus, depending on the level of voltage required during a read or write operation, the N / P / N structure 1225 exhibits bidirectional switching characteristics.

The RRAM element 1223 may be used and may have an N / P / N structure 1225 or a P / N / P structure as a switching element.

In the bidirectional driving N / P / N structure 1225 according to an embodiment of the present invention, the doping concentration of the third N-type doping layer and the first N-type doping layer is higher than that of the second P-type doping layer. May have a concentration.

The concentration of the third N-type doping layer and the first N-type doping layer may be in the same range or may have a higher concentration of one of the third N-type doping layer or the first N-type doping layer.

N / P / N structures of a plurality of RRAM cells may be included in the same bit line, and a plurality of RRAM memory elements may be included in the same word line.

When a specific cell 1227 including the RRAM element 1223 and the N / P / N structure 1225 is selected and written in the same manner as the STT-MRAM, data is written to the bit line 1210 of the specific cell 1227. The magnetization direction may be reversed by applying a driving voltage of 2V and applying a voltage of 0V to the word line 1200 of a specific cell to flow a current equal to or greater than the magnetization inversion threshold current value.

의 전압을 걸고, 비선택된 셀의 워드 라인(1203, 1205, 1207)에는

의 전압을 인가하여 비선택된 셀로 많은 전류가 흐르는 것을 방지하여 On/Off Ratio를 높힐 수 있다.Bit lines 1213 and 1215 of unselected cells except for specific cells 1227 are included in the bit lines 1213 and 1215.

At a voltage of, the word lines 1203, 1205 and 1207 of the unselected cells are

The on / off ratio can be increased by preventing a large current from flowing to the unselected cells by applying a voltage of.

In addition, when data is erased by selecting a specific cell 1227, the magnetization is performed by applying a driving voltage of 2V to the word line 1200 of the specific cell 1227 and applying a voltage of 0V to the bit line 1210 of the specific cell. The magnetization direction can be reversed by flowing a current equal to or greater than the inversion threshold current value.

의 전압을 걸고, 비선택된 셀의 비트 라인(1213, 1215)에는

의 전압을 인가하여 비선택된 셀로 많은 전류가 흐르는 것을 방지하여 On/Off Ratio를 높힐 수 있다.Word lines 1203, 1205, and 1207 of unselected cells except for specific cells 1227 are included in the word lines 1203, 1205, and 1207.

Is applied to the bit lines 1213 and 1215 of the unselected cells.

The on / off ratio can be increased by preventing a large current from flowing to the unselected cells by applying a voltage of.

That is, a memory according to an embodiment of the present invention includes a plurality of word lines and bit lines, and memory cells including a switching element and a resistive memory element share the same bit line but have different word lines or the same word line. Can be arranged with different bit lines. In addition, one end of the switching element may be connected to the bit line and one end of the resistive memory element may be connected to the word line.

According to an embodiment of the present invention, the driving voltage applied to the word line and the bit line to perform the read and write operations in the memory may be different, and the read and write of the memory with different driving voltages are not removed from the nature of the present invention. Implementation of the invention to perform the operation is also included in the scope of the invention.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

200: MTJ 201: fixed ferromagnetic layer
203: Tunnel junction layer 205: Variable ferromagnetic layer
700 Si substrate 710 Oxide thin film
720: N / P / N structure

Claims (11)

In a memory having a bidirectional driving characteristic,
A first doped layer doped with a first type of impurity on the semiconductor substrate;
A second doped layer doped with a second type of impurity such that the second type of impurity is different from the first type of impurity so as to be stacked on the first doped layer; And
A switching element having a bidirectional driving characteristic comprising a third doped layer doped with impurities of the first type so as to be stacked on the second doped layer; And
Including a memory cell having a resistive memory device connected to the third doped layer through a conductive connection structure,
2. The memory of claim 1, wherein the doping concentrations of the first doped layer and the third doped layer have a higher doping concentration than that of the second doped layer. The memory device of claim 1, wherein the memory having the bidirectional driving characteristic comprises:
And the first type of impurity is an N type impurity and the second type of impurity is a P type impurity. The memory device of claim 1, wherein the memory having the bidirectional driving characteristic comprises:
And the first type of impurity is a P type impurity, and the second type of impurity is an N type impurity. The memory device of claim 1, wherein the memory having the bidirectional driving characteristic comprises:
And a difference between a doping concentration between the first doped layer and the third doped layer is less than or equal to a predetermined value. The memory device of claim 1, wherein the memory having the bidirectional driving characteristic comprises:
And at least one of the doping concentrations of the first and third doping layers has a higher doping concentration than that of the other doping layer. The method of claim 1, wherein the first doped layer, the second doped layer and the third doped layer,
A memory having bidirectional driving characteristics, wherein the memory is doped to a group 4 element-based semiconductor substrate. The semiconductor substrate of claim 6, wherein the Group 4 element-based semiconductor substrate
A memory having a bidirectional driving characteristic, characterized in that the semiconductor substrate made of at least one of Silicon, Poly-Silicon, Ge, SiGe and GaAs. The memory device of claim 1, wherein the resistive memory device comprises:
A memory having a bidirectional driving characteristic, which is a MTJ (Magetic Tunneling Junction) and reads and writes data using a change in magnetization direction of a variable ferromagnetic layer included in the MTJ. The memory device of claim 1, wherein the resistive memory device comprises:
A memory having a bidirectional driving characteristic comprising one of a MTJ (Magetic Tunneling Junction), a RRAM (Resistive RAM) memory element, a Phase-Change RAM (PRAM) memory element, and a Polymer RAM (PoRAM) memory element. The memory device of claim 1, wherein the memory having the bidirectional driving characteristic comprises:
Memory cells including at least one word line and at least one bit line and including the switching element and the resistive memory element share the same bit line but have different word lines or share the same word line but different bit lines Memory having a bidirectional driving characteristic, characterized in that arranged with. The memory of claim 10, wherein the memory having the bidirectional driving characteristic includes:
Wherein one end of the switching element is connected to the bit line and one end of the resistive memory element is connected to a word line.

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