KR100490493B1 - Method for fixing semiconductor chip - Google Patents
Method for fixing semiconductor chip Download PDFInfo
- Publication number
- KR100490493B1 KR100490493B1 KR10-2000-0062391A KR20000062391A KR100490493B1 KR 100490493 B1 KR100490493 B1 KR 100490493B1 KR 20000062391 A KR20000062391 A KR 20000062391A KR 100490493 B1 KR100490493 B1 KR 100490493B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- bonding
- bonding means
- vacuum
- cavity
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
본 발명은 반도체 칩 고정 방법에 관한 것으로서, 부재의 캐비티를 마감하며 부착된 접착수단에 다수개의 홀을 형성함으로써, 반도체 칩이 접착수단에 부착된 상태에서 와이어 본딩 공정을 실시할 때, 히트블럭상의 진공홀로부터 제공되는 진공이 상기 접착수단의 홀을 통하여 반도체 칩의 저면까지 제공되어, 반도체 칩의 부착상태가 상기 진공흡착으로 더욱 견고하게 고정되도록 한 반도체 칩 고정방법을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fixing a semiconductor chip, wherein a plurality of holes are formed in a bonding means attached to an end of a cavity of a member, so that when the semiconductor chip is subjected to a wire bonding process in a state in which the semiconductor chip is attached to the bonding means, It is an object of the present invention to provide a method for fixing a semiconductor chip in which a vacuum provided from a vacuum hole is provided to the bottom surface of the semiconductor chip through the hole of the bonding means, so that the adhesion state of the semiconductor chip is more firmly fixed by the vacuum suction.
이에, 상기 접착수단의 홀을 통한 진공흡착으로 더욱 견고히 고정된 반도체 칩의 본딩패드에 대하여 와이어 본딩이 정확하게 이루어지게 되는 장점을 제공하게 된다.Thus, the wire bonding is precisely performed with respect to the bonding pad of the semiconductor chip more firmly fixed by vacuum adsorption through the hole of the bonding means.
Description
본 발명은 반도체 칩 고정 방법에 관한 것으로서, 더욱 상세하게는 부재의 캐비티에 부착되어 있는 접착수단에 다수개의 홀을 형성하여, 접착수단에 칩을 부착시 상기 홀을 통하여 진공을 제공함으로써, 접착수단에 부착된 칩을 더욱 견고하게 잡아줄 수 있도록 한 반도체 칩 고정 방법에 관한 것이다.The present invention relates to a method for fixing a semiconductor chip, and more particularly, by forming a plurality of holes in the bonding means attached to the cavity of the member, and providing a vacuum through the holes when attaching the chip to the bonding means, The present invention relates to a method for fixing a semiconductor chip to more firmly hold a chip attached thereto.
통상적으로 반도체 패키지는 전자기기의 집약적인 발달과 소형화 경향으로 인하여 고집적화, 소형화, 고기능화를 실현할 수 있는 구조로 제조되고 있는 추세에 있는 바, 그에따라 칩 스케일의 반도체 패키지가 개발되어 제조되고 있다.BACKGROUND ART In general, semiconductor packages are being manufactured in a structure capable of realizing high integration, miniaturization, and high functionality due to the intensive development and miniaturization of electronic devices. Accordingly, chip-scale semiconductor packages have been developed and manufactured.
상기 칩 스케일의 반도체 패키지의 제조 방법을 첨부한 도 3을 참조로 간략히 설명하면 다음과 같다. A method of manufacturing the chip scale semiconductor package is briefly described with reference to FIG. 3.
베이스 역할을 하는 수지층(24)상에 전도성패턴이 식각 처리되어 있고, 이 전도성패턴중 와이어 본딩용 전도성패턴(20a)과 볼랜드용 전도성패턴(20b)의 일부를 노출시키며 솔더마스크(22)가 도포되어 있으며, 중앙에는 캐비티(12)가 형성된 구조의 부재를 제공하는 단계와; 상기 캐비티(12)를 마감하며 부재(10)의 저면에 접착수단(14)을 부착하는 단계와, 상기 캐비티(12)상에 노출된 접착수단(14)면에 반도체 칩(18)을 부착하는 단계와; 상기 반도체 칩(18)의 본딩패드와 상기 부재(10)의 상면으로 노출된 와이어 본딩용 전도성패턴(20a)간을 와이어(30)로 본딩하는 단계와; 상기 반도체 칩(18)의 상면과, 상기 와이어(30)와, 상기 와이어 본딩용 전도성패턴(20a)등을 수지(32)로 몰딩하는 단계와; 상기 부재(10)의 상면에 노출된 볼랜드용 전도성패턴(20b)에 인출단자(34)를 부착하는 단계와; 상기 칩(18)의 일면이 외부로 노출되도록 상기 접착수단(14)을 떼어내는 단계를 마지막으로 첨부한 도 3에 도시한 바와 같은 구조의 칩 스케일 반도체 패키지(100)가 완성된다.The conductive pattern is etched on the resin layer 24 serving as a base, and the solder mask 22 exposes a portion of the conductive pattern 20a for wire bonding and the conductive pattern 20b for borland. Providing a member having a structure applied thereto, the cavity having a cavity 12 formed therein; Attaching the bonding means 14 to the bottom surface of the member 10 while closing the cavity 12, and attaching the semiconductor chip 18 to the surface of the bonding means 14 exposed on the cavity 12. Steps; Bonding between the bonding pad of the semiconductor chip 18 and the conductive pattern 20a for wire bonding exposed to the upper surface of the member 10 with a wire 30; Molding the upper surface of the semiconductor chip (18), the wire (30), the conductive pattern for wire bonding (20a), etc. with a resin (32); Attaching the lead terminal 34 to the conductive pattern 20b for the ball land exposed on the upper surface of the member 10; A chip scale semiconductor package 100 having a structure as shown in FIG. 3 is finally completed with the step of detaching the adhesive means 14 so that one surface of the chip 18 is exposed to the outside.
이때, 첨부한 도 4에 도시한 바와 같이, 상기 부재(10)의 캐비티(12)를 마감하며 부착된 접착수단(14)에 반도체 칩(18)을 부착한 후, 와이어 본딩을 실시하는 공정에 있어서, 우선 상기 부재(10)가 와이어 본딩용 히트블럭(28)상에 올려지게 된다.In this case, as shown in FIG. 4, the semiconductor chip 18 is attached to the bonding means 14 attached to the cavity 12 of the member 10, and then wire bonding is performed. First, the member 10 is placed on the wire bonding heat block 28.
다음으로, 상기 히트블럭(28)상에 형성된 진공홀(26)로부터 상기 캐비티(12)를 마감하고 있는 접착수단(14)의 저면에 진공을 제공되어, 접착수단(14)의 저면을 견고하게 잡아주게 된다.Next, a vacuum is provided to the bottom of the bonding means 14 closing the cavity 12 from the vacuum hole 26 formed on the heat block 28 to firmly secure the bottom of the bonding means 14. I will catch you.
다음으로, 상기 접착수단(14)의 상면에 부착된 반도체 칩(18)의 본딩패드와, 상기 부재(10)의 상면으로 노출된 와이어 본딩용 전도성패턴(20a)간을 캐필러리와 같은 와이어 본딩 수단으로 와이어 본딩 작업을 진행하게 된다.Next, a wire, such as a capillary, between the bonding pad of the semiconductor chip 18 attached to the upper surface of the bonding means 14 and the conductive pattern 20a for wire bonding exposed to the upper surface of the member 10. The wire bonding operation is performed by the bonding means.
이때, 상기 와이어 본딩 수단이 반도체 칩(18)에 대하여 1차본딩시 그 가압력 인하여, 접착력을 갖는 접착수단의 상면상에서 반도체 칩(18)이 미세하게 미끌리며 움직이게 된다.At this time, when the wire bonding means is first bonded to the semiconductor chip 18, the semiconductor chip 18 is finely slid and moved on the upper surface of the bonding means having the adhesive force.
상기와 같이, 반도체 칩이 움직이게 되면, 반도체 칩의 본딩패드에 대한 와이어 본딩의 정확성이 떨어지게 되어, 와이어 본딩의 불량을 초래하는 단점이 있었다.As described above, when the semiconductor chip is moved, the accuracy of wire bonding with respect to the bonding pad of the semiconductor chip is reduced, resulting in a defect in wire bonding.
따라서, 본 발명은 상기와 같은 단점을 해결하기 위하여 부재의 캐비티를 마감하며 부착된 접착수단에 다수개의 홀을 형성함으로써, 반도체 칩이 접착수단에 부착된 상태에서 와이어 본딩 공정을 실시할 때, 히트블럭상의 진공홀로부터 제공되는 진공이 상기 접착수단의 홀을 통하여 반도체 칩의 저면까지 제공되어, 반도체 칩의 부착상태가 상기 진공흡착으로 더욱 견고하게 고정되도록 한 반도체 칩 고정방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above disadvantages, the present invention forms a plurality of holes in the bonding means attached to the end of the cavity of the member, so that the heat bonding process is performed when the semiconductor chip is attached to the bonding means. It is an object of the present invention to provide a method for fixing a semiconductor chip in which a vacuum provided from a vacuum hole on a block is provided to the bottom surface of the semiconductor chip through the hole of the bonding means, so that the adhesion state of the semiconductor chip is more firmly fixed by the vacuum suction. have.
이에, 상기 접착수단의 홀을 통한 진공흡착으로 더욱 견고하게 고정된 반도체 칩은 와이어 본딩수단의 본딩력에도 흔들리지 않게 되어, 결국 반도체 칩의 본딩패드에 대한 와이어 본딩이 정확하게 이루어지는 장점을 제공하게 된다. Thus, the semiconductor chip more firmly fixed by vacuum adsorption through the holes of the bonding means is not shaken even by the bonding force of the wire bonding means, thus providing the advantage that the wire bonding to the bonding pad of the semiconductor chip is accurately performed.
상기한 목적을 달성하기 위한 본 발명의 반도체 칩 고정 방법은:The semiconductor chip fixing method of the present invention for achieving the above object is:
부재(10)의 캐비티(12)를 마감하며 부착된 접착수단(14)에 다수개의 홀(16)을 형성하고, 이 홀(16)이 형성된 접착수단(14)에 반도체 칩(18)을 부착하여, 상기 부재(10)가 올려진 히트블럭(28)의 진공홀(26)로부터 제공된 진공이 상기 접착수단(16)의 홀(16)을 통하여 반도체 칩(18)의 저면까지 제공되도록 함으로써, 반도체 칩(18)의 저면이 진공흡착으로 고정되도록 한 것을 특징으로 한다.A plurality of holes 16 are formed in the bonding means 14 which closes the cavity 12 of the member 10 and attaches the semiconductor chip 18 to the bonding means 14 in which the holes 16 are formed. Thus, the vacuum provided from the vacuum hole 26 of the heat block 28 on which the member 10 is raised is provided to the bottom surface of the semiconductor chip 18 through the hole 16 of the bonding means 16, The bottom surface of the semiconductor chip 18 is characterized in that it is fixed by vacuum adsorption.
상기 캐비티(12)에 부착된 접착수단(14)의 홀(16)은 반도체 칩(18)의 크기보다 작은 분포면적을 갖도록 형성된 것을 특징으로 한다.The hole 16 of the bonding means 14 attached to the cavity 12 is formed to have a distribution area smaller than that of the semiconductor chip 18.
여기서 본 발명을 실시예로서, 첨부한 도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 칩 고정 방법을 설명하기 위한 단면도로서, 도면부호 10은 부재를 나타낸다.1 is a cross-sectional view for explaining a method of fixing a semiconductor chip according to the present invention, and reference numeral 10 denotes a member.
상기 부재(10)는 베이스층인 수지층(24)의 상면에 동재질의 전도성패턴이 식각 처리되어 형성되어 있고, 상기 전도성패턴중에 와이어 본딩용 전도성패턴(20a)과 볼랜드용 전도성패턴(20b)을 노출시키며 솔더마스크(22)층이 도포되어 있으며, 특히 중앙부분에는 관통된 캐비티(12)가 형성되어 있는 구조의 인쇄회로기판이다.The member 10 is formed by etching a conductive pattern of the same material on the upper surface of the resin layer 24 which is a base layer, and among the conductive patterns, a conductive pattern 20a for wire bonding and a conductive pattern 20b for borland. It is a printed circuit board having a structure in which a solder mask 22 layer is applied, and in particular, a penetrating cavity 12 is formed in a central portion thereof.
상기와 같은 부재(10)의 저면에는 캐비티(12)를 마감하며 테이프와 같은 접착수단(14)이 부착되는 바, 첨부한 도 2에 도시한 바와 같이 상기 캐비티(12)와 일치되는 접착수단(14)의 면에는 다수의 관통된 홀(16)이 형성된다.On the bottom of the member 10, the cavity 12 is closed and an adhesive means 14, such as a tape, is attached to the bottom surface of the member 10. As shown in FIG. 2, the adhesive means coincides with the cavity 12 ( The surface of 14 is formed with a plurality of through holes 16.
특히, 상기 접착수단(14)에 형성된 홀(16)의 분포면적은 반도체 칩(18)의 크기보다 작은 면적을 갖도록 형성함이 바람직하고, 그 분포면적내에서 홀(18)의 크기는 최대한 작게, 홀의 수(18)는 최대한 많게 형성함이 바람직하다.In particular, the distribution area of the holes 16 formed in the bonding means 14 is preferably formed to have an area smaller than the size of the semiconductor chip 18, and the size of the holes 18 within the distribution area is as small as possible. , The number of holes 18 is preferably formed as much as possible.
따라서, 상기와 같은 구비된 부재(10)의 캐비티(12)에 반도체 칩(18)을 집어넣으면서 다수의 홀(16)을 갖는 상기 접착수단(14)에 반도체 칩(18)을 부착시키게 된다.Accordingly, the semiconductor chip 18 is attached to the bonding means 14 having the plurality of holes 16 while the semiconductor chip 18 is inserted into the cavity 12 of the provided member 10.
다음으로, 상기 반도체 칩(18)이 부착된 상태에서 와이어 본딩 공정을 실시하게 되는데, 첨부한 도 1에 도시한 바와 같이 반도체 칩(18)이 부착된 부재(10)를 와이어 본딩용 히트블럭(28)상에 올려놓은 후, 와이어(30) 본딩 공정을 실시하게 된다.Next, a wire bonding process is performed in a state in which the semiconductor chip 18 is attached, and as shown in FIG. 1, a member 10 to which the semiconductor chip 18 is attached is attached to a heat block for wire bonding. 28), the wire 30 is bonded.
이때, 히트블럭(28)상에 형성된 진공홀(26)로부터 상기 캐비티(12)에 부착되어 있는 접착수단(14)의 저면에 진공이 제공되어, 접착수단(14)이 진공흡착으로 고정되는데, 상기 진공홀(26)로부터 제공된 진공이 접착수단(14)에 형성된 홀(16)을 통하여 반도체 칩(18)의 저면까지 제공되어진다.At this time, a vacuum is provided from the vacuum hole 26 formed on the heat block 28 to the bottom surface of the bonding means 14 attached to the cavity 12, so that the bonding means 14 is fixed by vacuum adsorption. The vacuum provided from the vacuum hole 26 is provided to the bottom surface of the semiconductor chip 18 through the hole 16 formed in the bonding means 14.
따라서, 상기 접착수단(14)의 홀(16)을 통하여 제공된 진공에 의하여 반도체 칩(18)은 더욱 견고하게 고정되어진다.Therefore, the semiconductor chip 18 is more firmly fixed by the vacuum provided through the hole 16 of the bonding means 14.
이에따라, 캐필러리와 같은 와이어 본딩수단이 반도체 칩(18)의 본딩패드에 1차본딩(볼본딩)을 하게 되는 바, 이때의 와이어 본딩수단의 본딩 가압력에도 견고히 고정된 상태인 반도체 칩은 움직이지 않게 되어, 정확한 와이어 본딩이 이루어지게 된다.Accordingly, the wire bonding means such as the capillary is subjected to the first bonding (ball bonding) to the bonding pad of the semiconductor chip 18, the semiconductor chip is firmly fixed to the bonding pressing force of the wire bonding means at this time is moved In this case, accurate wire bonding is achieved.
한편, 상기와 같이 반도체 칩(18)의 본딩패드에 대한 정확한 볼본딩과, 부재상(10)에 노출된 와이어 본딩용 전도성패턴(20a)에 대한 스티치본딩이 진행된 후, 상기 반도체 칩(18)과 와이어(30)와 와이어 본딩용 전도성패턴(20a)등을 수지(32)로 몰딩하는 공정을 진행시키고, 상기 부재(10)의 상면으로 노출된 볼랜드용 전도성패턴(20b)에 솔더볼과 같은 인출단자(34)를 부착함으로써, 첨부한 도 3에 도시한 바와 같은 칩 스케일의 반도체 패키지(100)가 완성된다.Meanwhile, as described above, after accurate ball bonding of the bonding pad of the semiconductor chip 18 and stitch bonding of the conductive pattern 20a for wire bonding exposed to the member 10 are performed, the semiconductor chip 18 may be used. And a process of molding the wire 30 and the wire bonding conductive pattern 20a with the resin 32 and drawing out solder balls, such as solder balls, on the conductive pattern 20b for borland exposed to the upper surface of the member 10. By attaching the terminal 34, the chip-scale semiconductor package 100 as shown in FIG. 3 is completed.
이상에서 본 바와 같이, 본 발명에 따른 반도체 칩 고정 방법에 의하면 부재의 캐비티에 부착된 접착수단에 다수의 홀을 형성하여, 접착수단에 반도체 칩이 부착되는 동시에 상기 홀을 통하여 제공되는 진공에 의하여 반도체 칩이 더욱 견고하게 고정되도록 함으로써, 와이어 본딩시 반도체 칩은 와이어 본딩수단의 본딩력에도 흔들리지 않게 되어, 결국 반도체 칩의 본딩패드에 대한 와이어 본딩이 정확하게 이루어지는 장점을 제공하게 된다.As described above, according to the method for fixing a semiconductor chip according to the present invention, a plurality of holes are formed in the bonding means attached to the cavity of the member, and the semiconductor chip is attached to the bonding means and at the same time by a vacuum provided through the holes. Since the semiconductor chip is more firmly fixed, the semiconductor chip is not shaken by the bonding force of the wire bonding means during wire bonding, thereby providing the advantage that the wire bonding to the bonding pad of the semiconductor chip is accurately performed.
도 1은 본 발명에 따른 반도체 칩 고정 방법을 설명하는 단면도,1 is a cross-sectional view illustrating a semiconductor chip fixing method according to the present invention;
도 2는 본 발명에 따른 반도체 칩 고정 방법을 설명하는 평면도,2 is a plan view illustrating a semiconductor chip fixing method according to the present invention;
도 3은 본 발명에 따른 반도체 칩 고정 방법에 따라 제조된 반도체 패키지를 나타내는 단면도,3 is a cross-sectional view showing a semiconductor package manufactured according to the method for fixing a semiconductor chip according to the present invention;
도 4는 종래의 반도체 칩 고정 방법을 나타내는 단면도.4 is a cross-sectional view showing a conventional semiconductor chip fixing method.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 부재 12 : 캐비티10 member 12 cavity
14 : 접착수단 16 : 홀14: bonding means 16: hole
18 : 반도체 칩 20a : 와이어 본딩용 전도성패턴18: semiconductor chip 20a: conductive pattern for wire bonding
20b : 볼랜드용 전도성패턴 22 : 솔더마스크20b: conductive pattern for borland 22: solder mask
24 : 수지층 26 : 진공홀24: resin layer 26: vacuum hole
28 : 히트블럭 30 : 와이어28: heat block 30: wire
32 : 수지 34 : 인출단자32: Resin 34: Outgoing terminal
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0062391A KR100490493B1 (en) | 2000-10-23 | 2000-10-23 | Method for fixing semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0062391A KR100490493B1 (en) | 2000-10-23 | 2000-10-23 | Method for fixing semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020031717A KR20020031717A (en) | 2002-05-03 |
| KR100490493B1 true KR100490493B1 (en) | 2005-05-19 |
Family
ID=19694946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0062391A KR100490493B1 (en) | 2000-10-23 | 2000-10-23 | Method for fixing semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100490493B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2003231137A1 (en) * | 2003-04-29 | 2004-11-26 | Semiconductor Components Industries L.L.C. | Method of making a low profile packaged semiconductor device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04365334A (en) * | 1991-06-13 | 1992-12-17 | Nec Kyushu Ltd | Semiconductor device |
| KR930001398A (en) * | 1991-06-18 | 1993-01-16 | 김광호 | Semiconductor package |
| KR940002981A (en) * | 1992-07-29 | 1994-02-19 | 김광호 | Semiconductor Package Structure and Manufacturing Method |
| KR940010298A (en) * | 1992-10-06 | 1994-05-24 | 김광호 | Semiconductor package and manufacturing method thereof |
| KR970023896A (en) * | 1995-10-30 | 1997-05-30 | 김광호 | Semiconductor Chip Package Without Die Bonding Layer |
| KR970077418A (en) * | 1996-05-23 | 1997-12-12 | 김광호 | Manufacturing method of hardened dough using lead frame |
| KR980012330A (en) * | 1996-07-22 | 1998-04-30 | 김광호 | How to make a package |
| KR19980083302A (en) * | 1997-05-13 | 1998-12-05 | 황인길 | Semiconductor package and manufacturing method thereof |
-
2000
- 2000-10-23 KR KR10-2000-0062391A patent/KR100490493B1/en active IP Right Grant
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04365334A (en) * | 1991-06-13 | 1992-12-17 | Nec Kyushu Ltd | Semiconductor device |
| KR930001398A (en) * | 1991-06-18 | 1993-01-16 | 김광호 | Semiconductor package |
| KR940002981A (en) * | 1992-07-29 | 1994-02-19 | 김광호 | Semiconductor Package Structure and Manufacturing Method |
| KR940010298A (en) * | 1992-10-06 | 1994-05-24 | 김광호 | Semiconductor package and manufacturing method thereof |
| KR970023896A (en) * | 1995-10-30 | 1997-05-30 | 김광호 | Semiconductor Chip Package Without Die Bonding Layer |
| KR970077418A (en) * | 1996-05-23 | 1997-12-12 | 김광호 | Manufacturing method of hardened dough using lead frame |
| KR980012330A (en) * | 1996-07-22 | 1998-04-30 | 김광호 | How to make a package |
| KR19980083302A (en) * | 1997-05-13 | 1998-12-05 | 황인길 | Semiconductor package and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020031717A (en) | 2002-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100244580B1 (en) | Method for manufacturing circuit board having matal bump and semiconductor chip package | |
| JP6057190B2 (en) | Method for manufacturing semiconductor element or package | |
| US7193329B2 (en) | Semiconductor device | |
| KR20010067329A (en) | A method of manufacturing a semiconductor device | |
| US6353326B2 (en) | Test carrier with molded interconnect for testing semiconductor components | |
| US6432746B2 (en) | Method for manufacturing a chip scale package having slits formed on a substrate | |
| KR100490493B1 (en) | Method for fixing semiconductor chip | |
| KR100199286B1 (en) | Chip-scale package having pcb formed with recess | |
| KR100386636B1 (en) | PCB Manufacture Method for Semiconductor Package | |
| KR100341530B1 (en) | Method of making solder ball pad in BGA type PCB | |
| US20070123066A1 (en) | Interconnection element for BGA housings and method for producing the same | |
| KR100522838B1 (en) | Semiconductor package and method for manufacturing the same | |
| KR100353557B1 (en) | A fabricating method of package | |
| KR100426493B1 (en) | Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same | |
| KR100900182B1 (en) | Semiconductor package | |
| KR100508261B1 (en) | Semiconductor package and method for manufacturing the same | |
| KR100195512B1 (en) | Chip scale package and method for manufacturing the same | |
| KR100708042B1 (en) | Manufacturing method of substrate for semiconductor package | |
| KR100355747B1 (en) | Semiconductor package and manufacturing method the same | |
| KR20020031610A (en) | Semiconductor package and method for manufacturing the same | |
| KR200274132Y1 (en) | Semiconductor Package Manufacturing Equipment | |
| JPS6240749A (en) | Pin grid array | |
| KR100818079B1 (en) | A method for manufacturing of ball grid array package | |
| JP2867547B2 (en) | Method of forming conductive protrusions | |
| JP2006351607A (en) | Circuit board, its manufacturing method and manufacturing method of semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130502 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20140430 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20150430 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20160503 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20170510 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20180509 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20190507 Year of fee payment: 15 |