KR100486234B1 - Interlayer connection method of semiconductor device - Google Patents
Interlayer connection method of semiconductor device Download PDFInfo
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- KR100486234B1 KR100486234B1 KR1019980005815A KR19980005815A KR100486234B1 KR 100486234 B1 KR100486234 B1 KR 100486234B1 KR 1019980005815 A KR1019980005815 A KR 1019980005815A KR 19980005815 A KR19980005815 A KR 19980005815A KR 100486234 B1 KR100486234 B1 KR 100486234B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 텅스텐 플럭을 이용하여 하부 도전층과 상부 도전층을 연결시키는 반도체 소자의 층간접속방법에 관한 것이다. 텅스텐을 플럭시키기 위한 비아홀은 하부 도전층이 부분적으로 노출되도록 층간절연막에 형성한다. 암모니아 플라즈마 처리는 장벽금속층 형성 전 및/또는 후에 행한다. 텅스텐은 비아홀을 완전히 채우도록 결과물 기판 전면에 증착된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an interlayer connection method of a semiconductor device connecting a lower conductive layer and an upper conductive layer using tungsten flocs. Via holes for flocculating tungsten are formed in the interlayer insulating film so that the lower conductive layer is partially exposed. The ammonia plasma treatment is performed before and / or after the formation of the barrier metal layer. Tungsten is deposited on the entire surface of the resulting substrate to completely fill the via holes.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 텅스텐 플럭(W-plug)을 이용하여 하부 도전층과 상부 도전층을 연결시키는 반도체 소자의 층간접속방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an interlayer connection method of a semiconductor device connecting a lower conductive layer and an upper conductive layer using tungsten plugs.
현재 개발중인 거의 모든 반도체 소자는 다층배선을 채용하고 있으며, 고집적화로 인하여 접촉창의 어스펙트 비(aspect ratio)는 증가하는 추세에 있다. 상, 하부 알루미늄층을 텅스텐으로 연결하는 구조(Al-W-Al 구조)는 현재 가장 많이 이용하고 있는 다층배선 구조이다.Almost all semiconductor devices under development employ multilayer wiring, and the aspect ratio of contact windows is increasing due to high integration. The structure of connecting the upper and lower aluminum layers with tungsten (Al-W-Al structure) is the most commonly used multilayer wiring structure.
텅스텐을 비아홀(Via hole)에 플럭(plug)하여 상,하부 알류미늄층을 연결하는 상기 Al-W-Al 구조의 경우, 블랙 비아(black via), 말뚝 결함(defect) 및 비아홀에 텅스텐이 완전히 채워지지 않는(W-not fill) 것과 같은 손상에 취약한 특성을 지니고 있다. 또한, 텅스텐 증착 시, WF6나 SiH4 가스등에 의해 티타늄/티타늄 나이트라이드(Ti/TiN)로 된 장벽금속층(barrier metal)이 손상되는 경우가 증가하고 있다.In the Al-W-Al structure in which tungsten is plugged into a via hole to connect upper and lower aluminum layers, black vias, pile defects, and via holes are completely filled with tungsten. It is vulnerable to damage such as W-not fill. In addition, during tungsten deposition, barrier metal layers made of titanium / titanium nitride (Ti / TiN) are damaged by WF 6 or SiH 4 gas.
도 1a 내지 도 1e는 고온 RTN(Rapid Thermal Nitride) 처리로 장벽금속층의 특성을 강화하고자 한 종래의 반도체 소자의 층간접속방법을 공정순서별로 도시한 단면도들이다.1A to 1E are cross-sectional views illustrating a method of connecting an interlayer of a conventional semiconductor device to enhance the characteristics of a barrier metal layer by high temperature Rapid Thermal Nitride (RTN) treatment.
반도체 기판(10) 상에 하부 알루미늄층(12)을 형성하고 (도 1a), 이를 완전히 덮도록 층간절연막(14)를 형성한 후 (도 1b), 상기 하부 알루미늄층(12)이 부분적으로 노출되도록 상기 층간절연막(14)을 식각하여 비아홀(16)을 형성한다 (도 1c). 이어서, 비아홀(16)이 형성되어 있는 결과물 기판 전면에 티타늄/ 티타늄 나이트라이드(Ti/TiN)으로 된 장벽금속층(18)을 형성한 후, 상기 장벽금속층(18)이 형성되어 있는 결과물 기판을 고온 RTN 처리한다 (도 1d). 계속해서, 상기 고온 RTN 처리가 완료된 결과물 기판 전면에 텅스텐을 증착하여 텅스텐층(20)을 형성한다(도 1e).After forming the lower aluminum layer 12 on the semiconductor substrate 10 (FIG. 1A) and forming the interlayer insulating film 14 to completely cover it (FIG. 1B), the lower aluminum layer 12 is partially exposed. The interlayer insulating film 14 is etched to form a via hole 16 (FIG. 1C). Subsequently, after forming the barrier metal layer 18 made of titanium / titanium nitride (Ti / TiN) on the entire surface of the result substrate having the via holes 16 formed thereon, the resultant substrate having the barrier metal layer 18 formed thereon is subjected to high temperature. RTN treatment (FIG. 1D). Subsequently, the tungsten layer 20 is formed by depositing tungsten on the entire surface of the resultant substrate after the high temperature RTN treatment is completed (FIG. 1E).
일반적으로 Ti/TiN 장벽금속층의 경우, TiN막에서 N의 함량이 증가할수록 장벽 특성이 양호해지는 것으로 알려져 있으며, 상기 고온 RTN 처리는 장벽금속층 내의 N 함량을 증가시켜 그 특성을 향상시키기 위하여 진행한다.In general, in the case of the Ti / TiN barrier metal layer, the barrier property is known to be good as the N content increases in the TiN film. The high temperature RTN treatment proceeds to increase the N content in the barrier metal layer to improve its properties.
그러나, 상술한 종래의 층간접속방법에 의하면, 고온 RTN 처리시, 하부 알루미늄층 및 층간절연막의 열적 스트레스(thermal stress) 등에 의해 말뚝 손상(defect)이 발생할 우려가 있고, 공정 시간이 지연된다는 단점이 있다.However, according to the conventional interlayer connection method described above, during the high temperature RTN treatment, there is a possibility that pile damage may occur due to thermal stress of the lower aluminum layer and the interlayer insulating film, and the process time is delayed. have.
본 발명의 목적은 장벽금속층의 특성을 강화하고, 비아홀의 접촉특성을 향상시킬 수 있는 반도체 소자의 층간접속방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an interlayer connection method of a semiconductor device capable of enhancing the characteristics of the barrier metal layer and improving the contact characteristics of the via holes.
상기 목적을 달성하기 위한, 본 발명에 의한 반도체 소자의 층간접속방법은, 하부 도전층이 부분적으로 노출되도록 층간절연막에 텅스텐을 플럭시키기 위한 비아홀을 형성하는 공정, 장벽금속층 형성 전 및/또는 후에 결과물 기판을 암모니아(NH3) 플라즈마 처리하는 공정 및 상기 비아홀을 완전히 채우도록 결과물 기판 전면에 텅스텐을 증착하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, an interlayer connection method of a semiconductor device according to the present invention includes a step of forming a via hole for flocculating tungsten in an interlayer insulating film so that a lower conductive layer is partially exposed, and before and / or after forming a barrier metal layer. and a substrate characterized in that it comprises a step of depositing tungsten on the resultant substrate surface to completely fill the via hole and the process of plasma treatment of ammonia (NH 3).
이때, 상기 암모니아 플라즈마는 질소(N2)와 암모니아(NH3) 가스를 사용하며, 챔버 내의 압력을 1 - 4 Torr, 온도를 450℃ 이하로 하고, RF 파워 또는 마이크로웨이브를 사용하여 형성한다.At this time, the ammonia plasma uses nitrogen (N 2 ) and ammonia (NH 3 ) gas, the pressure in the chamber is 1 to 4 Torr, the temperature is 450 ℃ or less, and is formed using RF power or microwave.
따라서, 본 발명에 의하면, 장벽금속층의 특성을 강화할 수 있고, 비아홀의 접촉특성을 향상시킬 수 있다.Therefore, according to the present invention, the characteristics of the barrier metal layer can be enhanced, and the contact characteristics of the via holes can be improved.
이하, 첨부한 도면을 참조하여, 본 발명에 의한 반도체 소자의 층간접속방법을 더욱 상세하게 설명하고자 한다.Hereinafter, an interlayer connection method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 장벽금속층 형성 전 및/또는 후에 기판을 암모니아 플라즈마로 처리하는 본 발명의 일 실시예에 의한 반도체 소자의 층간접속방법을 공정 순서별로 도시한 단면도들이다.2A to 2G are cross-sectional views illustrating an interlayer connection method of a semiconductor device according to an exemplary embodiment of the present invention in which a substrate is treated with ammonia plasma before and / or after formation of a barrier metal layer.
반도체 기판(30) 상에, 예컨대 알루미늄(Al)과 같은 도전물질을 증착한 후 이를 패터닝하여 하부 도전층(32)을 형성하고 (도 2a), 상기 하부 도전층(32)이 완전히 덮히도록 절연물질을 도포하여 층간절연막(34)을 형성한다 (도 2b). 이어서, 상기 하부 도전층(32)이 부분적으로 노출되도록 층간절연막(34)을 식각하여 비아홀(36)을 형성한 후 (도 2c), 결과물 기판을 암모니아(NH3) 플라즈마로 1차 처리(38)한다 (도 2d). 이때, 상기 1차 처리는 비아홀(36) 형성을 위한 식각 공정 후 상기 비아홀 내에 남아있을지도 모를 플루오린(F)을 제거하기 위하여 진행한다.A conductive material such as aluminum (Al) is deposited on the semiconductor substrate 30 and then patterned to form a lower conductive layer 32 (FIG. 2A), and insulated so that the lower conductive layer 32 is completely covered. The material is applied to form an interlayer insulating film 34 (FIG. 2B). Subsequently, the interlayer insulating layer 34 is etched to partially expose the lower conductive layer 32 to form a via hole 36 (FIG. 2C), and then the resulting substrate is first treated with ammonia (NH 3 ) plasma (38). (FIG. 2D). In this case, the primary treatment is performed to remove fluorine (F) that may remain in the via hole after the etching process for forming the via hole 36.
계속해서, 상기 1차 처리가 행해진 결과물 기판 전면에, 예컨대 티타늄과 티타늄 나이트라이드가 적층된 구조의 장벽금속층(40)을 형성한 후 (도 2e), 상기 장벽금속층(40)이 형성되어 있는 결과물 기판을 암모니아 플라즈마로 2차 처리(42)한다 (도 2f). 이때, 상기 2차 처리는, 이후에 진행될 텅스텐 증착 공정 시 WF6 또는 SiH4 가스에 의해 상기 장벽금속층(40)이 손상되는 것을 방지하기 위해, 상기 장벽금속층(40) 내부에 질소의 함량을 증가시켜 그 특성을 강화하고자 행한다.Subsequently, after forming the barrier metal layer 40 having a structure in which titanium and titanium nitride are stacked on the entire surface of the resultant substrate subjected to the primary treatment (FIG. 2E), the resultant product of which the barrier metal layer 40 is formed. The substrate is subjected to secondary treatment 42 with ammonia plasma (FIG. 2F). At this time, the secondary treatment, in order to prevent the barrier metal layer 40 from being damaged by the WF 6 or SiH 4 gas during the subsequent tungsten deposition process, the content of nitrogen in the barrier metal layer 40 is increased To strengthen its characteristics.
이 후, 상기 2차 처리까지 행해진 결과물 기판 전면에, 예컨대 WF6과 SiH4 혼합 가스를 사용하여 텅스텐을 증착함으로써 텅스텐층(44)를 형성한다 (도 2g). 계속해서 도시되지는 않았지만, 상기 텅스텐층을 화학 물리적 폴리슁(CMP) 또는 다른 식각 방법으로 식각하여 상기 비아홀 내부에만 남도록하여 텅스텐 플럭층을 형성한 후, 상기 텅스텐 플럭층을 통해 하부 도전층과 연결되도록 상부 도전층을 형성함으로써 다층 배선을 완성하는 공정을 진행한다.Thereafter, the tungsten layer 44 is formed on the entire surface of the resultant substrate subjected to the secondary treatment, for example, by depositing tungsten using a mixed gas of WF 6 and SiH 4 (FIG. 2G). Although not shown continuously, the tungsten layer is etched by chemical physical polysilicon (CMP) or other etching method so as to remain only inside the via hole to form a tungsten floc layer, which is then connected to the lower conductive layer through the tungsten floc layer. The process of completing a multilayer wiring is performed by forming an upper conductive layer as much as possible.
상술한 본 발명의 일 실시예에서는, 장벽금속층 형성 전 및 후 모두에 암모니아 플라즈마 처리를 행하여 본 발명의 효과를 극대화 하였지만, 이러한 처리를 장벽금속층 형성 전에만 행하고 장벽금속층 형성 후에는 행하지 않거나, 장벽금속층 형성 전에는 행하지 않고 장벽금속층 형성 후에는 행하거나 하더라도 본 발명의 효과를 어느 정도 달성할 수 있음은 물론이다. 이때, 상기 암모니아 플라즈마 처리에 사용되는 암모니아 플라지마는 질소(N2)와 암모니아(NH3) 가스를 사용하여 형성하는데, 챔버 내의 압력을 1 - 4 Torr, 온도를 450℃ 이하로 하고, RF 파워 또는 마이크로 웨이브를 사용하여 형성한다.In the above-described embodiment of the present invention, the effect of the present invention is maximized by performing ammonia plasma treatment both before and after the formation of the barrier metal layer, but the treatment is performed only before the formation of the barrier metal layer and not after the formation of the barrier metal layer, or the barrier metal layer. It is a matter of course that the effect of the present invention can be achieved to some extent even if it is not performed before the formation and after the formation of the barrier metal layer. At this time, the ammonia plasma used in the ammonia plasma treatment is formed by using nitrogen (N 2 ) and ammonia (NH 3 ) gas, the pressure in the chamber 1 to 4 Torr, the temperature to 450 ℃ or less, RF power or Form using microwave.
본 발명에서는 기존의 고온 RTN 처리 대신에 암모니아 플라즈마를 사용하여 장벽금속층 형성 전,후의 기판을 처리함으로써 장벽금속층의 질소 함유량을 증가시켜 그 특성을 강화시키고, 비아홀 식각 공정에 의해 비아홀 내부에 잔존하게 되는 플루오린 성분을 제거하여 비아홀의 접촉 특성을 향상시킨다.In the present invention, by treating the substrate before and after the formation of the barrier metal layer by using ammonia plasma instead of the existing high temperature RTN treatment, the nitrogen content of the barrier metal layer is increased to enhance its characteristics, and remains in the via hole by the via hole etching process. The fluorine component is removed to improve the contact properties of the via holes.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by one of ordinary skill in the art within the technical idea of the present invention.
본 발명에 의한 반도체 소자의 층간접속방법에 의하면, 장벽금속층 형성 전 및/ 또는 후에 기판을 암모니아 플라즈마 처리함으로써 장벽금속층의 특성을 강화시켜 이후에 진행될 텅스텐 증착 공정시에 사용되는 가스에 의해 장벽금속층이 손상되는 것을 방지할 수 있으며, 비아홀 식각 공정 시 바아홀 내부에 잔존하게 되는 플루오린 성분을 제거하여 비아홀의 접촉 특성을 향상시킬 수 있다.According to the interlayer interconnection method of a semiconductor device according to the present invention, a barrier metal layer is formed by a gas used in a tungsten deposition process to be performed by enhancing the properties of the barrier metal layer by ammonia plasma treatment of the substrate before and / or after formation of the barrier metal layer. It is possible to prevent damage and to improve the contact characteristics of the via holes by removing fluorine components remaining in the bar holes during the via hole etching process.
도 1a 내지 도 1e는 고온 RTN(Rapid Thermal Nitride) 처리로 장벽금속층의 특성을 강화하고자 한 종래의 반도체 소자의 층간접속방법을 공정순서별로 도시한 단면도들이다.1A to 1E are cross-sectional views illustrating a method of connecting an interlayer of a conventional semiconductor device to enhance the characteristics of a barrier metal layer by high temperature Rapid Thermal Nitride (RTN) treatment.
도 2a 내지 도 2g는 장벽금속층 형성 전 및/또는 후에 기판을 암모니아 플라즈마로 처리하는 본 발명의 일 실시예에 의한 반도체 소자의 층간접속방법을 공정순서별로 도시한 단면도들이다.2A through 2G are cross-sectional views illustrating a method of connecting layers of semiconductor devices according to an embodiment of the present invention in which a substrate is treated with ammonia plasma before and / or after barrier metal layer formation.
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