KR100485161B1 - Formation method of contact hole in semiconductor device - Google Patents
Formation method of contact hole in semiconductor device Download PDFInfo
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- KR100485161B1 KR100485161B1 KR10-2003-0006415A KR20030006415A KR100485161B1 KR 100485161 B1 KR100485161 B1 KR 100485161B1 KR 20030006415 A KR20030006415 A KR 20030006415A KR 100485161 B1 KR100485161 B1 KR 100485161B1
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- film
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 125000005842 heteroatom Chemical group 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자의 접속홀을 형성하는 방법에 관한 것으로, 그 목적은 컨택홀 또는 비아홀의 내부에 보이드가 형성되는 것을 방지하는 것이다. 이를 위해 본 발명에서는, 반도체 기판의 구조물 상에 형성된 금속전절연막 또는 층간절연막 상에 금속전절연막 또는 층간절연막을 이루는 물질보다 식각속도가 느린 물질로 이루어진 이종막을 형성하는 단계; 이종막을 선택적으로 식각하여 소정폭의 접속홀구를 형성하는 단계; 접속홀구를 통해 노출된 금속전절연막 또는 층간절연막과, 이종막 상에, 금속전절연막 또는 층간절연막을 이루는 물질로 이루어진 추가막을 형성하는 단계; 금속전절연막 또는 층간절연막을 식각하여 컨택홀 또는 비아홀을 형성하되, 추가막을 식각하여 제거한 후 이종막을 마스크로 하여 금속전절연막 또는 층간절연막을 식각하는 단계; 금속전절연막 또는 층간절연막 상에 잔존하는 이종막을 제거하는 단계를 포함하여 반도체 소자의 접속홀을 형성한다.The present invention relates to a method of forming a connection hole of a semiconductor device, and an object thereof is to prevent voids from being formed in a contact hole or a via hole. To this end, in the present invention, forming a hetero film made of a material having a slower etching rate than the material of the metal pre-insulation layer or interlayer insulating film formed on the structure of the semiconductor substrate; Selectively etching the hetero film to form a connection hole having a predetermined width; Forming an additional film made of a material forming a metal pre-insulating film or an interlayer insulating film on the hetero-layer and the pre-insulating film or interlayer insulating film exposed through the connection hole; Forming a contact hole or a via hole by etching the pre-insulating layer or the interlayer insulating layer, and removing the additional layer by etching and etching the pre-insulating layer or the interlayer insulating layer using the heterogeneous layer as a mask; Forming a connection hole of the semiconductor device, including removing the remaining hetero film on the metal pre-insulating film or the interlayer insulating film.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속전절연막 또는 층간절연막을 선택적으로 식각하여 컨택홀 또는 비아홀을 형성하는 방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole or a via hole by selectively etching the pre-metal insulating film or the interlayer insulating film.
반도체 소자의 고집적화 추세에 따라 컨택홀 또는 비아홀의 폭 치수도 작아지고 있으며, 따라서 컨택홀 또는 비아홀의 종횡비가 증가하고 있다.In accordance with the trend toward higher integration of semiconductor devices, the width dimensions of the contact holes or via holes are also decreasing, and thus the aspect ratio of the contact holes or via holes is increasing.
이와 같이 컨택홀 또는 비아홀의 종횡비가 커지면서 컨택홀 또는 비아홀 내에 금속물질을 매립함에 있어서, 보이드 없이 완전히 매립하는 것이 어려워지고 있다.As the aspect ratio of the contact hole or the via hole increases as described above, the filling of the metal material in the contact hole or the via hole becomes difficult to completely fill the void.
도 1은 종래 반도체 소자의 접속홀 형성 방법을 도시된 단면도로서, 이에 도시한 바와 같이, 먼저, 소자의 활성영역으로 정의된 실리콘웨이퍼(1) 상에 소정폭의 게이트(2)를 형성하는 등의 통상적인 모스 트랜지스터 제조 공정을 진행하고, 게이트(2) 및 활성영역의 실리콘웨이퍼(1) 상면에 실리사이드(3)를 형성한다.1 is a cross-sectional view illustrating a method for forming a connection hole of a conventional semiconductor device. As shown in the drawing, first, a gate 2 having a predetermined width is formed on a silicon wafer 1 defined as an active region of a device. The conventional MOS transistor fabrication process is performed, and the silicide 3 is formed on the gate 2 and the upper surface of the silicon wafer 1 in the active region.
다음, 실리콘웨이퍼(1)의 상부 전면에 금속전절연막(4)을 두껍게 형성한 후, 화학기계적 연마하여 상면을 평탄화시킨다.Next, a thick metal pre-insulating film 4 is formed on the entire upper surface of the silicon wafer 1, and then the upper surface is planarized by chemical mechanical polishing.
다음, 금속전절연막(4)을 선택적으로 식각하여 컨택홀(100)을 형성한 후, 컨택홀(100)의 내벽에 베리어금속막(5)을 형성하고, 베리어금속막(5) 상에 금속물질(6)을 형성하여 컨택홀(100)의 내부를 매립한다.Next, after forming the contact hole 100 by selectively etching the metal pre-insulating film 4, the barrier metal film 5 is formed on the inner wall of the contact hole 100, and the metal is formed on the barrier metal film 5. A material 6 is formed to fill the inside of the contact hole 100.
이 때, 금속전절연막(4)을 종래의 통상적인 방법으로 식각하면 형성되는 컨택홀(100)의 상부 모서리가 직각에 가까운 모양을 가진다.At this time, the upper edge of the contact hole 100 formed when the metal pre-insulation film 4 is etched by a conventional method has a shape close to a right angle.
그런데 컨택홀(100)의 종횡비가 커지면서 베리어금속막(5)이 컨택홀(100)의 내벽 상에 균일한 두께로 증착되지 못하고 컨택홀(100)의 깊은 부분에 비해 입구부분에 더 두껍게 증착되는 오버행이 발생한다.However, as the aspect ratio of the contact hole 100 increases, the barrier metal film 5 is not deposited to a uniform thickness on the inner wall of the contact hole 100 and is deposited thicker at the inlet than the deep part of the contact hole 100. Overhang occurs.
이러한 오버행으로 인해 컨택홀(100)의 내부를 매립하도록 금속물질(6)을 형성할 때 컨택홀(100)의 깊은 부분을 미처 다 매립하기 전에 입구 부분이 막혀버려 결과적으로 컨택홀(100) 내에 금속물질이 완전히 매립되지 못한 빈 공간인 보이드(200)이 남아 있게 된다.Due to this overhang, when the metal material 6 is formed to fill the inside of the contact hole 100, the inlet part is blocked before the deep part of the contact hole 100 is completely buried, and as a result, the contact hole 100 is closed. The void 200, which is an empty space in which the metal material is not completely embedded, remains.
이러한 보이드(200)에는 후속 공정 진행 중에 이물질이 들어가 반도체 소자 작동에 치명적인 오류를 초래하는 등의 문제점이 있다.These voids 200 have a problem such that foreign matter enters during the subsequent process, causing a fatal error in the operation of the semiconductor device.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 컨택홀 또는 비아홀의 내부에 보이드가 형성되는 것을 방지하는 것이다. The present invention is to solve the above problems, the object is to prevent the voids are formed in the contact hole or via hole.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 컨택홀 또는 비아홀 형성을 위해 금속전절연막 또는 층간절연막을 식각할 때, 금속전절연막 또는 층간절연막 상에 이종막 및 산화막을 형성한 후 식각하여 컨택홀 또는 비아홀의 상부 모서리 부분을 라운딩시키는 효과가 있다.In order to achieve the above object, in the present invention, when etching the pre-insulation layer or interlayer insulating layer to form a contact hole or via hole, forming a hetero film and an oxide layer on the pre-insulation layer or interlayer insulating layer and then etching the contact There is an effect of rounding the upper edge portion of the hole or via hole.
즉, 본 발명에 따른 반도체 소자의 접속홀 형성 방법은, 반도체 기판의 구조물 상에 형성된 금속전절연막 또는 층간절연막 상에 금속전절연막 또는 층간절연막을 이루는 물질보다 식각속도가 느린 물질로 이루어진 이종막을 형성하는 단계; 이종막을 선택적으로 식각하여 소정폭의 접속홀구를 형성하는 단계; 접속홀구를 통해 노출된 금속전절연막 또는 층간절연막과, 이종막 상에, 금속전절연막 또는 층간절연막을 이루는 물질로 이루어진 추가막을 형성하는 단계; 금속전절연막 또는 층간절연막을 식각하여 컨택홀 또는 비아홀을 형성하되, 추가막을 식각하여 제거한 후 이종막을 마스크로 하여 금속전절연막 또는 층간절연막을 식각하는 단계; 금속전절연막 또는 층간절연막 상에 잔존하는 이종막을 제거하는 단계를 포함하여 이루어진다.That is, in the method for forming a connection hole of a semiconductor device according to the present invention, a heterogeneous film made of a material having a slower etching rate than a material forming a pre-insulating or interlayer insulating film is formed on the pre-insulating or interlayer insulating film formed on the structure of the semiconductor substrate. Doing; Selectively etching the hetero film to form a connection hole having a predetermined width; Forming an additional film made of a material forming a metal pre-insulating film or an interlayer insulating film on the hetero-layer and the pre-insulating film or interlayer insulating film exposed through the connection hole; Forming a contact hole or a via hole by etching the pre-insulating layer or the interlayer insulating layer, and removing the additional layer by etching and etching the pre-insulating layer or the interlayer insulating layer using the heterogeneous layer as a mask; And removing the remaining hetero film on the metal pre-insulating film or the interlayer insulating film.
이하, 본 발명에 따른 반도체 소자의 접속홀 형성 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a connection hole of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명의 일 실시예에 따른 반도체 소자의 접속홀 형성 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a connection hole in a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이, 소자의 활성영역으로 정의된 실리콘웨이퍼(11) 상에 소정폭의 게이트(12)를 형성하는 등의 통상적인 모스 트랜지스터 제조 공정을 진행하고, 게이트(12) 및 활성영역의 실리콘웨이퍼(11) 상면에 실리사이드(13)를 형성한다.First, as shown in FIG. 2A, a typical MOS transistor manufacturing process such as forming a gate 12 having a predetermined width on a silicon wafer 11 defined as an active region of a device is performed. And silicide 13 is formed on the upper surface of the silicon wafer 11 in the active region.
이어서, 실리콘웨이퍼(11)의 상부 전면에 금속전절연막(14)을 두껍게 형성한 후, 화학기계적 연마하여 상면을 평탄화시킨다.Subsequently, a thick metal pre-insulating film 14 is formed on the entire upper surface of the silicon wafer 11, and then the upper surface is planarized by chemical mechanical polishing.
다음, 도 2b에 도시된 바와 같이, 금속전절연막(14) 상에 이종막(15)을 형성하고, 이종막(15)을 선택적으로 식각하여 소정폭의 컨택홀구를 형성한다.Next, as shown in FIG. 2B, the hetero film 15 is formed on the metal pre-insulating layer 14, and the hetero film 15 is selectively etched to form contact hole holes having a predetermined width.
이 때 이종막(15)은 이후 컨택홀 형성을 위한 금속전절연막(14) 식각 시 하드마스크로서 사용하기 위해 형성한 것으로서, 하드마스크로 사용할 때 함께 식각되어 손실되는 양을 고려하여 두께를 조절하면 된다.At this time, the hetero film 15 is formed to be used as a hard mask when etching the metal pre-insulation layer 14 for forming a contact hole, and when the thickness is adjusted in consideration of the amount lost by etching together with the hard mask. do.
또한, 이종막(15)으로는 금속전절연막(14)을 이루는 물질인 산화막과는 식각선택비가 큰 물질을 선택하여 형성한다. In addition, the hetero film 15 is formed by selecting a material having a large etching selectivity from an oxide film, which is a material forming the pre-insulation film 14.
바람직하게는 이종막(15)으로서 질화막을 2000-4000Å의 두께로 형성한다.Preferably, the nitride film is formed as a hetero film 15 with a thickness of 2000-4000 mm 3.
이어서, 컨택홀구의 내벽 및 이종막(15) 상에 산화막(16)을 얇게 형성한다. 산화막(16)은 콘택홀의 상부 모서리를 라운딩시키기 위해 형성하는 것으로서 50-150Å 정도의 두께로 형성한다.Subsequently, a thin oxide film 16 is formed on the inner wall of the contact hole and the hetero film 15. The oxide film 16 is formed to round the upper edge of the contact hole and is formed to a thickness of about 50-150 Å.
다음, 도 2c에 도시된 바와 같이, 식각공정을 진행하여 산화막(16)을 제거한 후 이종막(15)을 하드마스크로 사용하여 컨택홀구 하부의 금속전절연막(14)을 소정폭으로 식각하여 컨택홀(100)을 형성한다.Next, as shown in FIG. 2C, after the etching process is performed to remove the oxide layer 16, the pre-insulating layer 14 under the contact hole is etched to a predetermined width by using the dissimilar layer 15 as a hard mask. The hole 100 is formed.
이 때 컨택홀구의 측벽에는 산화막(16)이 두껍게 형성되어 있으므로 컨택홀구 바닥면 상의 산화막이 식각되어 제거된 후에도 컨택홀구의 측벽에는 산화막이 남아 있다가 금속전절연막이 식각되는 동안 측벽에 남아있던 산화막도 함께 식각되며, 금속전절연막의 식각이 어느 정도 진행된 다음에 측벽 하부의 금속전절연막을 식각하게 된다.At this time, since the oxide film 16 is formed on the sidewall of the contact hole, the oxide film remains on the sidewall of the contact hole even after the oxide film on the bottom surface of the contact hole is etched and removed. Also, the metal pre-insulation layer under the sidewall is etched after etching the metal pre-insulation layer to some extent.
여기서 측벽 하부의 금속전절연막이란 형성되는 컨택홀(100)의 상부 모서리 부분에 해당하며, 따라서 컨택홀의 상부 모서리로 갈수록 얕게 식각되며, 결과적으로 컨택홀의 상부 모서리가 라운딩된다.In this case, the metal pre-insulation layer below the sidewall corresponds to the upper edge portion of the contact hole 100 to be formed. Therefore, the upper edge portion of the contact hole is etched shallowly, and as a result, the upper edge of the contact hole is rounded.
또한, 금속전절연막(14)이 식각되는 동안에 이종막(15)도 식각되어 손실되기도 하나, 식각속도가 충분히 낮아서 손실되는 두께가 매우 작으며, 이 때 손실되는 두께를 미리 고려하여 형성한 바 있다.In addition, the hetero film 15 may also be etched and lost while the pre-insulating film 14 is etched, but the thickness of the dissimilar film 15 is sufficiently low because the etching rate is sufficiently low. .
다음, 도 2d에 도시된 바와 같이, 잔존하는 이종막(15)을 제거한 후, 컨택홀(100)의 내벽을 포함하여 금속전절연막(14)의 상부 전면에 베리어막(17)을 형성하고, 베리어막(17) 상에 금속물질(18)을 형성하여 컨택홀(100)의 내부를 매립한다.Next, as shown in FIG. 2D, after removing the remaining dissimilar layer 15, the barrier layer 17 is formed on the entire upper surface of the pre-metal insulating layer 14 including the inner wall of the contact hole 100. A metal material 18 is formed on the barrier layer 17 to fill the inside of the contact hole 100.
이 때 컨택홀(100)의 상부 모서리가 라운딩되어 있으므로 컨택홀(100)의 입구부분이 넓어진 효과를 보이며, 따라서 베리어금속막(17) 형성 시 오버행이 발생하지 않는다. 따라서, 보이드의 발생없이 컨택홀(100)의 내부가 금속물질(18)로 완전히 매립된다.At this time, since the upper edge of the contact hole 100 is rounded, the inlet portion of the contact hole 100 is widened, and thus, an overhang does not occur when the barrier metal film 17 is formed. Therefore, the inside of the contact hole 100 is completely filled with the metal material 18 without generation of voids.
상술한 바와 같이, 본 발명의 일 실시예에서는 금속전절연막을 선택적으로 식각하여 컨택홀을 형성하는 경우를 예로 들었으나, 이에 한정될 필요는 없다. 즉, 본 발명의 다른 실시예로서 층간절연막을 선택적으로 식각하여 비아홀을 형성하는 경우에도 적용할 수 있다.As described above, in the embodiment of the present invention, the case where the contact hole is formed by selectively etching the pre-insulation layer is not limited thereto. That is, as another embodiment of the present invention, it is also applicable to the case where the via hole is formed by selectively etching the interlayer insulating film.
상술한 바와 같이, 본 발명에서는 컨택홀 또는 비아홀 형성을 위해 금속전절연막 또는 층간절연막을 식각할 때, 금속전절연막 또는 층간절연막 상에 이종막 및 산화막을 형성한 후 식각하여 컨택홀 또는 비아홀의 상부 모서리 부분을 라운딩시키기 때문에, 컨택홀의 입구부분이 넓어진 효과를 보이며, 따라서 베리어금속막 형성 시 오버행이 발생하지 않고, 보이드의 발생없이 컨택홀의 내부가 금속물질로 완전히 매립되는 효과가 있다.As described above, in the present invention, when etching the pre-insulation layer or interlayer insulating layer to form contact holes or via-holes, the dissimilar layer and the oxide layer are formed on the pre-insulation layer or interlayer insulating layer and then etched to form an upper portion of the contact hole or via hole. Since the corner portion is rounded, the inlet portion of the contact hole is widened, and thus, an overhang does not occur when the barrier metal film is formed, and the inside of the contact hole is completely filled with a metal material without the occurrence of voids.
따라서, 보이드로 인해 유발되는 불량을 미연에 방지하여 소자의 신뢰성을 향상시킨다.Therefore, defects caused by voids are prevented in advance, thereby improving reliability of the device.
도 1은 종래 반도체 소자의 접속홀 형성 방법을 도시한 단면도이고,1 is a cross-sectional view showing a connection hole forming method of a conventional semiconductor device,
도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체 소자의 접속홀 형성 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a connection hole in a semiconductor device according to an embodiment of the present invention.
Claims (7)
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