KR100481988B1 - Method for fabricating of mask ROM - Google Patents

Abstract

The present invention relates to a method for manufacturing a mask rom to form a salicide layer in all of the ferry region, the logic core region, and the cell region to prevent short circuit of the bit line, and to isolate the cell region from the ferry / logic region. Forming a device isolation layer and forming a bit line in the mask ROM memory cell region by an ion implantation process; forming a memory cell channel, a BN junction, and depositing and selectively patterning a gate oxide layer and a polysilicon layer in turn to form a word of a cell region Forming a gate of the line and logic regions; forming LDD junctions in the logic and cell regions and forming sidewall spacers and S / D junctions; forming silicides over word lines and BN junctions in the memory cell region; And depositing an interlayer insulating layer on the entire surface to form a wiring layer.

Description

Manufacturing method of mask ROM {Method for fabricating of mask ROM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a method of manufacturing a mask ROM in which a salicide layer is formed in all of a ferry region, a logic core region, and a cell region to prevent a short line of a bit line.

The mask ROM is coded using a mask having data desired by the user during the manufacturing process to store the data, after which the stored data cannot be changed and only the stored data can be read. Maskrom can code data by implanting impurities to make a transistor different from other transistors.

The mask rom is divided into a NAND cell structure and a flat NOR cell structure according to the cell structure. The NAND type cell structure is separated into field oxide using a device isolation process such as LOCOS to separate between the cell string and the cell string. The flat cell structure separates the cell string and the cell string into a buried n + impurity layer.

Therefore, in the flat cell structure, since the area and the step due to the field oxide film can be eliminated, the cell density can be increased as compared with the NAND cell structure.

However, since the flat cell structure separates the cell from the cell into the buried n + impurity layer, in the case of formation of the buried n + impurity layer, in the case of an open defect in which ions are not implanted by the particles generated by the previous step in the ion implantation process, Since the electrical separation between the cell and the cell is not made, a failure occurs.

Hereinafter, a mask ROM according to the related art will be described with reference to the accompanying drawings.

1 is a layout diagram of a general mask ROM.

2A-2K are cross-sectional views of a process for forming a mask ROM of the prior art.

In view of the prior art configuration, several attempts have been made to lower the wordline resistance mentioned above.

2A to 2K have been widely used in ROMs having a size of 0.35 μm or more as a technique of adopting a polycide gate structure in a word line to lower word line resistance.

1 is a layout of a typical mask ROM NOR array cell, where BN (Buried N +) is used as a bit line and poly of the cell is used as a word line.

The unit cell is composed of a BN and a gate, and then stores data of "0" and "1" through a coding process.

First, as shown in FIG. 2A, after forming the cell region 1 and the ferry or logic region 2, a device isolation process is performed to isolate the two regions.

Normally LOCOS and modified LOCOS are used and STI (3) (Sallow Trench Isolation) is used for devices below 0.25 microns.

Subsequently, as shown in FIG. 2B, the BN junction 5 is formed through photo and ion implantation. It serves as a source / drain of the cell and is used as a bit line.

In case of adopting NMOS cell transistor, ion is implanted into 5-50KeV, Dose 1E14 ~ 1E16 with As and P, and in case of adopting PMOS cell transistor, B and BF2 is ion implanted in 5-50KeV, Dose 1E14 ~ 1E16.

After the ion implantation, annealing or oxidation is performed to improve junction properties.

2C, the gate oxide film 6, the poly 7, the silicide 8, and the capping layer 9 are sequentially deposited.

Here, the poly 7 is usually made of polysilicon doped with n-type impurities, and the silicide 8 may be made of W.

The capping layer 9 also serves as a gate hard mask and ARC (Anti Reflected Coating) and is formed of an oxide film or nitride and a combination thereof.

Subsequently, as shown in FIGS. 2D and 2E, the word line 11 of the cell and the gate 10 of the logic are patterned.

Usually a photoresist is used to etch a capacitor and then the capacitor is used as a mask to etch a polycide.

After the gate and word line patterning, the LDD junction 12 of the logic region is formed.

By cell layout, the word lines remain in the X1-X1 'cross section, and the poly (7), silicide (8), and capping layer (9) are removed in the X2-X2' cross section.

As shown in FIG. 2F, side well spacers 13 and S / D junctions 14 are formed.

Here, the spacer is formed by etching and then etching back the oxide film, nitride, and a combination thereof. In the cross section X1-X1 'of FIG. 1, a spacer is formed outside the cell region. In the cross section X2-X2', as shown in FIG. 2G, the insulating film for forming a spacer is etched and completely removed.

2H and 2I, after the salicide blocking layer 15 is deposited, a photoside and etching process is performed to remove the salicide blocking layer 15 in a region other than the cell.

Here, the blocking layer is composed of an oxide film and nitride or a combination thereof.

After depositing Ti, Ni, Co, Ta and the like, a heat treatment is performed to form silicide and to remove the unreacted layer.

The salicide 16 is formed in the active region where the salicide blocking layer 15 is removed, and no silicide is formed in the other regions.

It can be seen that no part of the salicide is formed in the memory cell region. The silicide prevention layer remains in the memory cell active region, so that no silicide is formed, and thus a short circuit between bit lines does not occur.

2J and 2K, after the interlayer insulating layer 17 is deposited, a wiring layer is formed.

Hereinafter, another process for manufacturing a mask ROM of the prior art will be described.

3A-3B are cross-sectional views of another process for forming a mask ROM of the prior art.

In the cell configuration, a bit line short circuit caused by the silicide bridge between the bit line and the bit line that appears when silicide is formed in the mask ROM cell is shown.

The cross section X1-X1 'shows that silicide is formed in the mask ROM word line, and the cross section X2-X2' shows that the bit line is shorted by the active silicide.

Hereinafter, another process for manufacturing a mask ROM of the prior art will be described.

4A-4H are yet another process cross-sectional view for forming a mask ROM of the prior art.

BN (Buried N +) is used as a bit line and the poly of a cell is used as a word line.

The unit cell is composed of a BN and a gate, and then stores data of "0" and "1" through a coding process.

First, as shown in FIG. 4A, after forming the cell region 1 and the ferry or logic region 2, the device isolation process is performed to isolate the two regions.

Normally LOCOS and variant LOCOS are used and STI (3) (Sallow Trench Isolation) is used in sub-quarter micron devices.

As shown in FIG. 4B, after the gate oxide film 4 and the first polysilicon layer 5 are deposited, photo / poly etching is performed.

The photoresist 6 and the first polysilicon layer 5 serve as an ion implantation mask in the BN region 7 through ion implantation.

The BN junction serves as a source / drain of the cell and is used as a bit line. After ion implantation, annealing or oxidation is performed to improve junction properties.

Here, when etching the polysilicon layer, the gate oxide film should remain without being recessed.

As shown in FIG. 4C, a second polysilicon layer 8 is deposited.

The second polysilicon layer may be doped by depositing doped poly or by ion implantation, annealing or the like after undoped poly deposition.

Subsequently, as shown in FIG. 4D, the word line of the cell and the gate of logic are patterned. Usually the photoresist is used as the masking layer to etch the poly.

At this time, between the word line and the word line of the cell, the silicon substrate is recessed in the BN region 7 in which there is no first polysilicon layer, and the active region in which the first polysilicon layer remains remains as a salicide blocking layer due to the remaining gate oxide layer. Should be.

As shown in FIG. 4E, the LDD junction 9, the spacer 10, and the S / D junction 11 of the logic region are formed.

Here, the spacer 10 is formed by etching back after deposition with an oxide film, nitride, and combinations thereof.

Subsequently, as shown in FIG. 4F, after depositing Ti, Ni, Co, Ta and the like, a silicide is formed through heat treatment, and an unreacted layer is removed to form a salicide layer.

Silicide is then formed on the second polysilicon layer and at the BN junction site of the cell.

As shown in FIGS. 4G and 4H, the wiring layer is formed after the interlayer insulating film 13 is deposited.

In cross section X1-X1 ', silicide is formed on the second polysilicon layer and becomes a word line, and in the cross section X2-X2', the remaining gate insulating layer serves as a silicide prevention layer so that no silicide is formed in the active between the bit lines. This does not cause bit line short circuits.

However, such a conventional mask ROM manufacturing method has the following problems.

First, if a polyside gate structure is used in the prior art and salicide is applied only to a logic region and a ferry active, it is difficult to adopt a dual poly structure, resulting in poor pMOS characteristics of a logic circuit.

Devices less than 0.25µm should use surface channel n / pMOS, which requires embedded channel pMOS.

Second, it can be seen that it is difficult to avoid a short circuit between bit lines that appears when the cell structure of the prior art described in FIG. 3 is applied to a deep submicron process.

If the silicide structure is not adopted in the word line of the cell region, the line resistance is increased, resulting in deterioration of device characteristics, high-speed operation, and reduction in integration.

Third, in the case of the technique of FIG. 4, first, the gate oxide film under the first polysilicon layer should not be recessed at all during gate patterning, which is practically impossible.

Also, even if it is not etched at all, the thickness is too thin to be used as the salicide blocking layer. If the remaining oxide is used as the salicide blocking layer, it remains as a salicide blocking in the active region of the logic or ferry circuit and becomes a salicide only on the gate and the BN junction.

Fourth, the flat cell type is adopted to implement the NOR array in the mask ROM, and the mask ROM of the flat cell array uses buried N + (BN) as the bit line. Therefore, if the salicide prevention process is not applied to the cell region, the bit line is used. And adjacent bit lines are shorted by salicide.

The present invention has been made to solve the problem of the mask ROM of the prior art, and the saliva layer is formed in all of the ferry region, the logic core region, and the cell region to prevent the short circuit of the bit line. It is an object to provide a manufacturing method.

In order to achieve the above object, a method of manufacturing a mask ROM according to the present invention includes forming a device isolation layer by isolating a cell region and a ferry / logic region, and forming a bit line by an ion implantation process in a mask ROM memory cell region. Forming a memory cell channel, a BN junction, and depositing and selectively patterning a gate oxide layer and a polysilicon layer in order to form a gate of a word line and a logic region of the cell region; forming an LDD junction in the logic and cell region and forming a side Forming a wall spacer and an S / D junction; forming silicide on the word line and the BN junction in the memory cell region; and forming a wiring layer after depositing an interlayer insulating layer on the front surface.

Referring to the accompanying drawings, a preferred embodiment of a method for manufacturing a mask rom according to the present invention will be described in detail as follows.

5 is a layout diagram of a mask ROM according to the present invention, and FIGS. 6A to 6J are cross-sectional views of a process for forming the mask ROM according to the present invention.

According to the present invention, in the fabrication of read only memory (ROM) of the memory semiconductor, a self-aligned silicide may be formed in the cell region to lower the resistance of the word line, thereby rapidly reducing the signal delay and simultaneously increasing the number of shared word lines. This is to increase the degree of integration.

The present invention implements salicide in both the ferry region, the logic core region, and the cell region, and allows the word line of the memory cell to be salicided while preventing the bit line from shortening without additional processing and maintaining the minimum cell size. do.

When the present invention is applied, various problems such as the puncturing and Vt of the memory cell transistor and the leakage current increase due to the channel length reduction due to the lateral diffusion of the BN junction can be prevented.

In addition, the ROM can be mounted when the performance of logic is degraded when manufacturing embedded mask ROM logic (ERL) as well as a single mask ROM memory.

FIG. 5 illustrates a mask ROM cell layout according to the present invention, in which a BN pattern is shown in the opposite direction as before, indicating that a region opened during BN patterning is a portion where a BN junction is not formed.

BN (buried N +) is used as a bit line and the poly of a cell is used as a word line. The unit cell is composed of a BN and a gate, and then stores data of "0" and "1" through a coding process.

First, as shown in FIG. 6A, a cell region 61 and a ferry or logic region 62 are formed, and a device isolation process is performed to isolate the two regions, thereby forming an STI isolation layer 63 (Sallow Trench Isolation). To form.

As shown in FIG. 6B, ion implantation is performed in the mask ROM memory region through photo and ion implantation.

In the ferry and logic circuits, ion implantation is prevented by the first photoresist pattern 64, and the entire memory cell region 61 is exposed to implant ions. Implanted ions serve as the source / drain of the cell and serve as bit lines.

NMOS cell transistors employed when As, 5 ~ 50KeV, Dose 1E14 ~ 1E16atoms / cm 2 , so the ion implantation and, PMOS cell transistors employed when B, BF _2, such as a 5 ~ 50KeV, Dose 1E14 ~ 1E16atoms / cm 2 so ions P etc. Proceed with the injection process.

6C, a memory cell channel is formed through a photo / etch process.

Here, the second photoresist pattern 65 serves as a protective film to prevent etching of the portion where the BN junction is to be formed, and the substrate of the channel region is etched.

The etching amount can be increased in proportion to the ion implantation energy, and is etched to a depth of about 50 to 100% of the BN junction.

It is also possible to etch by applying the boiling method and the inclined etching by dry etching, and it is also possible to perform the isoetching by wet etching.

Subsequently, as shown in FIG. 6D, the BN junction 66 is formed through annealing or an oxidation process after etching and post-treatment, and the gate oxide layer 67 and the polysilicon layer 68 are sequentially deposited.

Here, in the case of using the dual poly gate, a gate oxide film may be formed to contain NO or N ₂ O to suppress boron penetration in the P + gate.

The polysilicon layer 68 is then doped after depositing the doped polysilicon layer or depositing the undoped polysilicon layer.

6E and 6F, the word line 70 of the cell region and the gate 69 of the logic region are patterned.

Due to the cell layout, the word lines remain in the X1-X1 'cross section, and the polysilicon layer 68 layer is removed in the X2-X2' cross section.

At this time, the gate oxide film is not completely removed when the poly-etch is formed next to the BN junction 66, and remains in the form of the side wall spacer 71.

After the gate and word line formation, the LDD junction 72 is formed in the logic and cell regions.

6G and 6H, side wall spacers 73 and S / D junctions 74 are then formed.

The spacer is formed by etching and then etching back the oxide film, nitride, and a combination thereof.

In the X1-X1 'cross section, spacers are formed outside the cell region. In the X2-X2' cross section, the spacer material is not completely removed during the etching of the spacer due to the bending of the BN junction 66, and the gate oxide spacer formed during the gate etching next to the BN junction. A spacer 73 is formed next to 71 to form a double spacer.

As such, after forming the side well spacers, the source / drain junction 74 of N / PMOS is formed.

6I and 6J, after depositing Ti, Ni, Co, Ta, and the like, silicide is formed through heat treatment to remove the unreacted layer.

Silicide 75 is formed over the word line and the BN junction in the memory cell region.

It can be seen that the word line is silicided in the cross section X1-X1 ', and the BN junction is silicided in the cross section X2-X2'.

Here, it can be seen that the short circuit between the bit lines is not caused by the double spacers 71 and 73.

As described above, when the mask ROM manufacturing method according to the present invention is applied, the salicide bridge between BNs can be prevented without an additional protection layer of a memory cell. Thereafter, the interlayer insulating layer 76 is deposited to form a wiring layer.

In the present invention, silicide is formed on the mask ROM word line, so that the line resistance is reduced, the high speed operation is easy, and the silicide prevention process is eliminated, thereby simplifying the process.

If the silicide is formed by the present invention is the entire chip, such as the gate and junction of the ferry and logic, the word line of the cell, the bit line of the cell and if there is a portion that does not need silicide, do.

The greatest advantage in the process according to the invention is that there is no further process to prevent short-to-bit short-circuits when manufacturing maskroms with the prior art.

When the present invention is applied, various problems such as punch-through and Vt reduction and leakage current increase of the memory cell transistor due to the channel length reduction due to the side diffusion of the BN junction can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The manufacturing method of the mask ROM according to the present invention described above has the following effects.

When applying the process according to the invention it is possible to produce a sub-quarter micron (mask) of the class.

This enables high performance of the ferry circuit and the use of surface channel pMOS, and the salicide process can be used to reduce the resistance of the logic and ferry circuits and reduce the cell wordline resistance.

In addition, since there is no need for a region for preventing a short circuit between BN and BN in the cell region, a mask ROM cell can be formed with a minimum size.

In addition, cell transistors can maintain a more stable and uniform characteristic distribution, and are particularly suitable for implementing embedded ROM logic, and can sufficiently ensure the performance of logic devices.

1 is a layout diagram of a typical mask ROM

2A-2K are cross-sectional views of a process for forming a mask ROM of the prior art.

3A-3B are cross-sectional views of another process for forming a mask ROM of the prior art.

4A-4H are cross-sectional views of another process for forming a mask ROM of the prior art.

5 is a layout diagram of a mask ROM according to the present invention.

6A-6J are cross-sectional views of a process for forming a mask ROM according to the present invention.

-Explanation of symbols for the main parts of the drawing-

61. Cell area 62. Logic area

63. STI isolation layer 64.65. 1,2 photoresist pattern

66. BN junction 67. Gate oxide

68. Polysilicon Layer 69. Logic Gate

70. Cell word line 71. Spacer

72.LDD Junction 73.Sidewall spacer

74. Source / drain junction 75. Silicide

75. Interlayer Insulation

Claims (7)

Forming a device isolation layer to isolate the cell region and the ferry / logic region and forming a bit line in the mask ROM memory cell region by an ion implantation process; Forming a memory cell channel, a BN junction, and depositing and selectively patterning a gate oxide film and a polysilicon layer in order to form a word line of a cell region and a gate of a logic region; Forming LDD junctions in the logic and cell regions and forming sidewall spacers and S / D junctions; Forming silicide on word lines and BN junctions in the memory cell region; And depositing an interlayer insulating layer on the entire surface to form a wiring layer. The method of claim 1, wherein in the ion implantation process for forming a bit line, As and P impurities are implanted at 5 to 50 KeV and Dose 1E14 to 1E16 atoms / cm ² in the case of an NMOS cell transistor, and B is used in a PMOS cell transistor. And ion implantation of BF ₂ impurities at 5 to 50 KeV and Dose 1E14 to 1E16 atoms / cm ² . The method of claim 1, wherein the etching depth is etched to a depth of about 50 to 100% of the BN junction during the etching process for forming the memory cell channel. The method of claim 3, wherein the etching process for forming the memory channel is performed by anisotropic etching or oblique etching by dry etching or isotropic etching through wet etching. The method of claim 1, wherein the BN junction is formed by an annealing or an oxidation process. The method of manufacturing a mask ROM according to claim 1, wherein the gate oxide film is formed on the side of the BN junction at the time of forming the LDD junction, but is not completely removed during poly etching, but remains in the form of a side well spacer. The method of claim 1, wherein the silicide forming process is performed by depositing Ti, Ni, Co, Ta, or the like, followed by heat treatment to form silicide, and to remove an unreacted layer.