KR20040058942A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent permeation of dopant into a semiconductor substrate by forming a gate electrode for MOS transistor and a gate electrode for MOS capacitor with a silicon germanium layer and a conductive layer including the silicon germanium layer. CONSTITUTION: An isolation layer(12) is formed on a semiconductor substrate(10). An insulating layer used as a gate insulating layer(14) of a MOS transistor and a dielectric layer of a MOS capacitor is formed on the semiconductor substrate. A polysilicon germanium layer(16) or a conductive layer including the polysilicon germanium layer is formed on the insulating layer. A first gate electrode(20) for MOS transistor and a second gate electrode(22) for MOS capacitor are formed by patterning the conductive layer.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode for a MOS transistor and a MOS capacitor capable of preventing boron infiltration into a semiconductor substrate under the gate electrode.

As the size of the semiconductor device decreases (0.1 μm tech or less), the thickness of the gate oxide film should be about 15 μs or less. The ions doped by the thin gate oxide through the gate doping process penetrate the gate oxide and penetrate the lower semiconductor substrate, affecting the threshold voltage of the cell transistor, and changing the doping profile of the gate electrode to deteriorate the reliability of the device. A problem occurs.

Therefore, in order to solve the above problem, the present invention forms a gate electrode including a polysilicon germanium film, thereby preventing a dopant injected into the gate electrode from penetrating into a lower semiconductor substrate. The purpose is to provide.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 12 device isolation film

14 gate insulating film 16 polysilicon germanium film

18: polysilicon film 20, 22: gate electrode

24 junction area 26 silicide film

28: interlayer insulation film 30: contact plug

32: bit line

Providing a semiconductor substrate having a device isolation film according to the present invention, forming an insulating film to be used as a gate insulating film of a MOS transistor and a dielectric film of a MOS capacitor on the semiconductor substrate, a polysilicon germanium film or Forming a conductive film including a polysilicon germanium film and patterning the conductive film to form a first gate electrode for a MOS transistor and a second gate electrode for a MOS capacitor. do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

As semiconductor memory devices are becoming more integrated, so-called silicon on chips, in which different devices with different functions are implemented on one chip, allowing two or more devices to operate organically on one chip. Chip; SoC). Therefore, the manufacturing process of SoC becomes more complicated and difficult. The manufacturing process for implementing one device having different functions on one chip may be a process that satisfies the characteristics of only one device, but each device may have two or more devices having different functions on one chip. Processes that meet all the required properties become very complex and in some cases additional processes are added. An embedded memory device, which is one of SOC devices, implements a memory device and a logic device on a single chip, and computes a cell area in which a plurality of memory cells are located and information stored in the cell area. It is composed of logic areas that generate information.

In order to manufacture such a device, a planar DRAM device, in which a unit cell is formed of one MOS transistor and one MOS capacitor, is manufactured. In this embodiment, the planar DRAM device will be described.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 10. After the photoresist is deposited on the entire structure, a photolithography process using a photoresist mask is performed to form a photoresist pattern (not shown). A trench (not shown) is formed by using a STI (Sallow Trench Isolation) etching process using the photoresist pattern and the pad nitride layer as an etching mask, and the device isolation layer 12 is formed by filling the trench using an insulating layer. The semiconductor substrate 10 is separated into an active region and an inactive region (ie, an isolation region) by the isolation layer 10. The device isolation layer 12 may be formed by various processes. For example, the device isolation film may be formed using only the photoresist pattern without depositing the above-described pad oxide film and pad nitride film, and the wells may be first formed on the semiconductor substrate, and then the device isolation film may be formed.

Referring to FIG. 1B, a gate insulating film of a MOS transistor constituting a cell and an insulating film 14 to be used as a dielectric film of a MOS capacitor are formed on the semiconductor substrate 10 on which the device isolation film 12 is formed. The gate insulating film 14 is formed using at least one of a SiO 2 film, a Si 3 N 4 film, and a silicon oxynitride film.

Referring to FIG. 1C, a conductive film including a polysilicon germanium film 16 or a multilayer film including a polysilicon germanium film is formed on the gate insulating film 14. The conductive film is patterned to form the first gate electrode 20 for the MOS transistor and the second gate electrode 22 for the MOS capacitor.

Specifically, the multilayer conductive film including the polysilicon germanium film 16 further includes at least one of a polysilicon film, a SiGe film, a WSi ₂ film, a TiSi ₂ film, a TiN film, a tungsten film (W), and a TaN film. Form to include. The conductive film is deposited using various types of chemical vapor deposition or sputtering. In this embodiment, a conductive film composed of two layers of the polysilicon germanium film 16 and the polysilicon film 18 will be described. A conductive film is formed by sequentially depositing the polysilicon germanium film 16 and the polysilicon film 18 on the gate insulating film 14.

After the photoresist is coated on the conductive film, a photodevelopment process using a gate mask is performed to form a photoresist pattern. An etching process using the photoresist pattern as an etching mask is performed to form gate electrodes 20 and 22 of the MOS transistor and the MOS capacitor of the planar DRAM cell.

The first and second gate electrodes 20 and 22 formed by the above-described process are formed to include the polysilicon germanium film 16 or the polysilicon germanium film 16, thereby being injected into the gate electrode by a subsequent process. It is possible to prevent a phenomenon in which ions (dopants) are excessively diffused by heat and penetrate the semiconductor substrate through the lower gate insulating layer 14. In other words, it is possible to solve the problem of the dopant penetrating the semiconductor substrate to perform a stable cell operation.

Referring to FIG. 1D, ion implantation is performed to form a junction region (source and drain) 20. The silicide layer 26 is formed on the first gate electrode 20, the second gate electrode 22, and the junction region 24 by a salicide (Self-Aligned Silicide; Salicide) process. In this embodiment, since the silicide film is formed on the polysilicon film 18 formed on the silicon germanium film 16, it is possible to prevent the loss of germanium atoms during the salicide process. In this case, the silicide layer 26 may be formed only on the first and second gate electrodes 20 and 22. In addition, the process may be simplified by not performing the salicide process described above. The interlayer insulating film 28 is deposited on the entire structure, and then patterned to form a plug contact hole for electrically connecting the junction region 24. The contact hole is filled with a metal film to form the contact plug 30, and then the bit line 32 is formed on the contact plug 30.

Specifically, the ion implantation for forming the junction region 24 implants Arsenic (As) or Phosphorus (P) ions into the N + region, and the P + region is boron according to the PMOS or NMOS to be operated as a cell transistor. (Bron; B) ions are implanted to form a junction region 24 for NMOS or PMOS. The junction region 24 is formed by implanting a high concentration of ions into the semiconductor substrate 10 on both sides of the first gate electrode 20. At this time, ions are also injected into the exposed first and second gate electrodes 20 and 22.

A metal film (not shown) using cobalt (Co) and a capping film (not shown) using TiN are formed on the entire structure. A first heat treatment process is performed to induce a reaction between silicon on the first and second gate electrodes 20 and 22 and the junction region 24 to form a mono silicide (CoSi). The second heat treatment process is performed to form a final cobalt silicide layer (CoSi ₂ ).

An interlayer insulating film 28 of an oxide film and a nitride film series is deposited. A photosensitive film is coated on the interlayer insulating film 24 and then a photodevelopment process is performed using a contact hole mask to form a photosensitive film pattern (not shown). An etching process using the photoresist pattern as an etching mask is performed to remove the interlayer insulating film 28 and the insulating film 14 to form a plug contact hole. A contact plug 30 is formed by filling the plug contact hole with a metal material. A metal film is deposited on the entire structure, and then a bit line patterning process is performed to form the bit line 32 on the contact plug 30.

As described above, the present invention forms a conductive film including a silicon germanium film and a silicon germanium film as a gate electrode of a MOS transistor and a MOS capacitor, thereby preventing a dopant from penetrating into a semiconductor substrate and reducing leakage current. In addition, the capacitance of the MOS capacitor can be improved.

Claims (3)

Providing a semiconductor substrate on which an isolation layer is formed; Forming an insulating film to be used as a gate insulating film of a MOS transistor and a dielectric film of a MOS capacitor on the semiconductor substrate; Forming a conductive film including a polysilicon germanium film or a polysilicon germanium film on the insulating film; And Patterning the conductive film to form a first gate electrode for a MOS transistor and a second gate electrode for a MOS capacitor. The method of claim 1, The conductive film further comprises at least one of polysilicon film, SiGe film, WSi ₂ film, TiSi ₂ film, TiN film, tungsten film (W) and TaN film. The method of claim 1, After forming the first gate electrode for the MOS transistor and the second gate electrode for the MOS capacitor on the insulating film, Performing ion implantation to form junction regions on both sides of the first gate electrode; Forming an interlayer insulating film on the entire structure; Forming a contact plug in the interlayer insulating film to electrically connect the junction region; And And forming a bit line on the contact plug.