KR100480920B1 - Method for forming element isolating film of semiconductor device - Google Patents
Method for forming element isolating film of semiconductor device Download PDFInfo
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- KR100480920B1 KR100480920B1 KR10-2003-0043888A KR20030043888A KR100480920B1 KR 100480920 B1 KR100480920 B1 KR 100480920B1 KR 20030043888 A KR20030043888 A KR 20030043888A KR 100480920 B1 KR100480920 B1 KR 100480920B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Abstract
본 발명은 반도체소자의 소자분리막 형성방법을 개시한다. 개시된 발명은, 반도체기판상에 패드산화막과 패드질화막을 적층하는 단계; 상기 패드질화막과 패드산화막 및 반도체기판의 일부를 순차적으로 제거하여 상기 반도체기판내에 트렌치를 형성하는 단계; 상기 트렌치를 포함한 전체 구조의 상면에 측벽산화막을 형성하는 단계; 상기 질소와 산소를 포함하는 혼합가스를 이용한 아닐링공정을 진행하여 상기 측벽산화막과 반도체기판의 계면에 질화막을 형성하는 단계; 및 전체 구조의 상면에 HDP산화막을 형성하여 상기 트렌치를 갭매립시키는 단계를 포함 하여 구성되어, 라이너산화막 증착공정 및 조밀화공정을 생략하므로써 공정단순화에 따른 원가절감을 꾀할 수 있으며, 산화막과 실리콘기판의 계면에 질화막을 형성시켜 주므로써 셀과 셀간 리키지를 방지할 수 있는 것이다.The present invention discloses a device isolation film forming method of a semiconductor device. The disclosed invention comprises the steps of laminating a pad oxide film and a pad nitride film on a semiconductor substrate; Sequentially removing a portion of the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench in the semiconductor substrate; Forming a sidewall oxide film on an upper surface of the entire structure including the trench; Performing a annealing process using the mixed gas containing nitrogen and oxygen to form a nitride film at an interface between the sidewall oxide film and the semiconductor substrate; And gap filling the trench by forming an HDP oxide film on the upper surface of the entire structure, thereby reducing cost due to the process simplification by omitting the liner oxide film deposition process and the densification process. By forming a nitride film at the interface, it is possible to prevent cell-to-cell leakage.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로서, 보다 상세하게는 질소와 산소를 함유한 혼합가스를 이용한 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly to a method for forming a device isolation film of a semiconductor device using a mixed gas containing nitrogen and oxygen.
현재 256M SD램 등 0.18μm 이하의 반도체소자 분리막으로는 종래의 LOCOS 구조가 아닌 STI(shallow trench isolation) 구조가 널리 이용되고 있다.Currently, a shallow trench isolation (STI) structure, rather than a conventional LOCOS structure, is widely used as a semiconductor device isolation film having a thickness of 0.18 μm or less, such as a 256M SD RAM.
이러한 STI 구조의 기존 소자분리막을 형성방법에 대해 도 1a 내지 도 1e를참조하여 설명하면 다음과 같다.A method of forming an existing device isolation film having an STI structure will be described below with reference to FIGS. 1A to 1E.
도 1a 내지 도 1e는 기존 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.1A through 1E are cross-sectional views illustrating a method of forming an isolation layer of a conventional semiconductor device.
기존의 소자분리막 형성방법은, 도 1a에 도시된 바와같이, 반도체기판(11)상에 패드산화막(13)과 패드질화막(15)을 순차적으로 적층한다음 그 위에 소자분리막 형성지역을 한정하는 감광막패턴(17)을 형성한다.In the conventional method of forming a device isolation film, as shown in FIG. 1A, a pad oxide film 13 and a pad nitride film 15 are sequentially stacked on a semiconductor substrate 11, and then a photoresist film defining a device isolation film formation region thereon. The pattern 17 is formed.
그다음, 도 1b에 도시된 바와같이, 상기 감광막패턴(17)을 마스크로 상기 패드질화막(15)과 패드산화막(13) 및 반도체기판(11) 일부를 순차적으로 식각하여 상기 반도체기판(11)내에 소자분리용 트렌치(19)를 형성한다.Subsequently, as shown in FIG. 1B, the pad nitride layer 15, the pad oxide layer 13, and a portion of the semiconductor substrate 11 are sequentially etched using the photoresist pattern 17 as a mask, and then into the semiconductor substrate 11. A device isolation trench 19 is formed.
이어서, 도 1c에 도시된 바와같이, 상기 감광막패턴(17)을 제거한후 트렌치 식각 데미지층의 제거를 위해 제1 희생산화공정을 진행하여 상기 트렌치(19)를 포함한 전체 구조의 노출된 상면에 희생산화막(21)을 얇게 형성한다.Subsequently, as illustrated in FIG. 1C, after the photoresist pattern 17 is removed, a first sacrificial oxidation process is performed to remove the trench etch damage layer, thereby sacrificing the exposed top surface of the entire structure including the trench 19. The oxide film 21 is formed thin.
그다음, 도 1d에 도시된 바와같이, 세정공정을 통해 상기 희생산화막(21)을 제거한후 제2 측벽산화공정을 진행하여 측벽산화막(23)을 형성한다.Next, as shown in FIG. 1D, the sacrificial oxide film 21 is removed through a cleaning process and a second sidewall oxidation process is performed to form a sidewall oxide film 23.
이어서, 도 1e에 도시된 바와같이, 셀과 셀간 리키지(leakage)를 방지하기 위하여 상기 측벽산화막(23)상에 라이너질화막(25)을 형성한다.Subsequently, as shown in FIG. 1E, a liner nitride film 25 is formed on the sidewall oxide layer 23 to prevent cell-to-cell leakage.
그다음, 그 위에 갭매립시 적용되는 HDP와의 응력 완화를 위하여 라이너산화막(27)을 형성하고 이어 라이너산화막(27)의 조밀화공정(densification)을 실시한다음 마지막으로 전체 구조의 상면에 HDP산화막(29)을 증착하여 갭매립을 실시한다.Next, a liner oxide film 27 is formed thereon to relieve stress with the HDP applied to the gap filling, and then a densification of the liner oxide film 27 is performed. Finally, the HDP oxide film 29 is formed on the upper surface of the entire structure. Is deposited to carry out gap filling.
그러나, 상기와 같은 종래기술에 의하면, 기존의 STI 공정은 그 과정이 복잡하고, 이로 인한 여러 가지 문제를 야기하고 있다. 그중 중요한 몇가지를 예를 들면 첫째 측벽희생산화공정과 측벽산화공정에 의해 활성영역의 일부가 손실되고, 둘째 CVD 질화막 라이너의 사용에 의한 응력이 증가하며, 셋째 진행공정이 많아짐에 따라 생산단가가 증가하는 등의 문제가 발생하고 있다.However, according to the prior art as described above, the existing STI process is a complicated process, causing a number of problems. Some of the important ones, for example, part of the active area is lost by the first sidewall dilution process and sidewall oxidation process, secondly, the stress caused by the use of CVD nitride film liner increases, and thirdly, the production cost increases as the number of process steps increases. There is a problem such as.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 라이너산화막 증착공정 및 조밀화공정을 생략하므로써 공정단순화에 따른 원가절감을 꾀할 수 있는 반도체소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, by providing a method for forming a device isolation film of a semiconductor device that can reduce the cost of the process by eliminating the liner oxide film deposition process and densification process. There is this.
또한, 본 발명의 다른 목적은 산화막과 실리콘기판의 계면에 질화막을 형성시켜 주므로써 셀과 셀간 리키지를 방지할 수 있는 반도체소자의 소자분리막 형성방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device that can prevent the cell and the cell between the cell by forming a nitride film at the interface between the oxide film and the silicon substrate.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 반도체기판상에 패드산화막과 패드질화막을 적층하는 단계;A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of: laminating a pad oxide film and a pad nitride film on a semiconductor substrate;
상기 패드질화막과 패드산화막 및 반도체기판의 일부를 순차적으로 제거하여 상기 반도체기판내에 트렌치를 형성하는 단계;Sequentially removing a portion of the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench in the semiconductor substrate;
상기 트렌치를 포함한 전체 구조의 상면에 측벽산화막을 형성하는 단계;Forming a sidewall oxide film on an upper surface of the entire structure including the trench;
상기 질소와 산소를 포함하는 혼합가스를 이용한 아닐링공정을 진행하여 상기 측벽산화막과 반도체기판의 계면에 질화막을 형성하는 단계; 및Performing a annealing process using the mixed gas containing nitrogen and oxygen to form a nitride film at an interface between the sidewall oxide film and the semiconductor substrate; And
전체 구조의 상면에 HDP산화막을 형성하여 상기 트렌치를 갭매립시키는 단계를 포함하여 구성되는 것을 특징으로한다.And forming gaps in the trench by forming an HDP oxide film on an upper surface of the entire structure.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 소자분리막 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2F are cross-sectional views of processes for describing a method of forming a device isolation film of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체소자의 소자분리막 형성방법에 있어서, 식각깊이에 따른 강도를 도시한 그래프이다. 3 is a graph showing the strength according to the etching depth in the method of forming a device isolation film of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 소자분리막 형성방법은, 도 2a에 도시된 바와 같이, 반도체기판(31)상에 패드산화막(33)과 패드질화막(35)을 순차적으로 적층한 다음 그 위에 소자분리막 형성지역을 한정하는 감광막패턴(37)을 형성한다.In the method of forming a device isolation film of a semiconductor device according to the present invention, as illustrated in FIG. 2A, a pad oxide film 33 and a pad nitride film 35 are sequentially stacked on a semiconductor substrate 31, and then a device isolation film is formed thereon. A photosensitive film pattern 37 defining an area is formed.
그다음, 도 2b에 도시된 바와같이, 상기 감광막패턴(37)을 마스크로 상기 패드질화막(35)과 패드산화막(33) 및 반도체기판(31) 일부를 순차적으로 식각하여 상기 반도체기판(31)내에 소자분리용 트렌치(39)를 형성한다.Next, as shown in FIG. 2B, the pad nitride layer 35, the pad oxide layer 33, and a portion of the semiconductor substrate 31 are sequentially etched using the photoresist pattern 37 as a mask, and then into the semiconductor substrate 31. A device isolation trench 39 is formed.
이어서, 도 2c에 도시된 바와같이, 상기 감광막패턴(37)을 제거한후 트렌치 식각 데미지층의 제거를 위해 제1 측벽희생산화공정을 진행하여 상기 트렌치(39)를 포함한 전체 구조의 노출된 상면에 희생산화막(41)을 얇게 형성한다. 이때, 상기 희생산화막(41) 형성시의 공정조건으로는 900∼1100℃ 의 온도범위내에서 30∼150 Å 두께를 가지는 건식산화를 진행하거나 700∼900℃의 온도범위내에서 이루어지는 습식산화를 진행한다. Subsequently, as shown in FIG. 2C, after the photoresist pattern 37 is removed, a first sidewall dilution process is performed to remove the trench etch damage layer, and the exposed upper surface of the entire structure including the trench 39 is formed. The sacrificial oxide film 41 is formed thin. At this time, as the process conditions when the sacrificial oxide film 41 is formed, dry oxidation having a thickness of 30 to 150 kPa is performed in a temperature range of 900 to 1100 ° C., or wet oxidation is performed in a temperature range of 700 to 900 ° C. do.
그다음, 도 2d에 도시된 바와같이, 세정공정을 통해 상기 희생산화막 (41)을 제거한후 제2 측벽산화공정을 진행하여 측벽산화막(43)을 형성한다.Next, as shown in FIG. 2D, the sacrificial oxide film 41 is removed through a cleaning process and a second sidewall oxidation process is performed to form a sidewall oxide film 43.
이어서, 도 2e에 도시된 바와같이, 측벽산화막(43) 질소와 산소를 함유한 혼합가스, 예를들어 NO 또는 N2O 등을 이용한 아닐링공정을 진행하여 상기 측벽산화막 (43)과 반도체기판(31)사이에 질화막(45)을 형성한다. 특히 아닐링공정에 이용하는 가스로는 NO가스가 바람직하다. 이때, 상기 질소와 산소를 함유한 혼합가스를 이용한 아닐링공정을 통해 질소가 확산되면서 질화막(45)이 형성된다. 또한, 상기 아닐링공정은 측벽산화공정을 진행한후 동일한 장비내에서 이루어지는 인시튜(in-냐셔)공정으로 진행한다. 그리고, 상기 아닐링공정시에 이용하는 질소와 산소를 함유한 혼합가스로는 NO 가스를 포함한다. 또한, 상기 NO 아닐링공정은 750∼1100℃ 온도의 범위, 바람직하게는 800∼950℃온도에서 200∼500 torr 의 높은 압력으로 진행하며, NO 가스를 1 slm ∼ 20 slm 으로 유입시키고, 아닐링시간은 5∼100분동안 유지한다.Subsequently, as shown in FIG. 2E, the annealing process using a mixed gas containing nitrogen and oxygen, for example, NO or N 2 O, is performed as shown in FIG. 2E to form the sidewall oxide film 43 and the semiconductor substrate. The nitride film 45 is formed between the 31. In particular, the gas used for the annealing process is preferably NO gas. At this time, as the nitrogen is diffused through an annealing process using the mixed gas containing nitrogen and oxygen, the nitride film 45 is formed. In addition, the annealing process proceeds to an in-situ process performed in the same equipment after the sidewall oxidation process. The mixed gas containing nitrogen and oxygen used in the annealing step includes NO gas. In addition, the NO annealing process is carried out at a high pressure of 200 to 500 torr at a temperature in the range of 750 to 1100 ° C., preferably at 800 to 950 ° C., injecting NO gas into 1 slm to 20 slm, and annealing. The time is maintained for 5 to 100 minutes.
한편, 상기 아닐링공정후 산화막내에서의 질소농도는 1∼20 원자 %를 포함하며, 상기 아닐링공정후 산화막내에서의 질소 분포는 산화막과 반도체기판의 계면에서 최고의 농도를 가지며, 가우시안 분포를 가진다.On the other hand, the nitrogen concentration in the oxide film after the annealing process contains 1 to 20 atomic%, and the nitrogen distribution in the oxide film after the annealing process has the highest concentration at the interface between the oxide film and the semiconductor substrate and has a Gaussian distribution. Have
그다음, 도 2f에 도시된 바와같이, 전체 구조의 상면에 HDP산화막(47)을 증착하여 트렌치를 갭매립시킨다.Then, as shown in Fig. 2f, the trench is filled by depositing the HDP oxide film 47 on the upper surface of the entire structure.
이어서, 도면에서 도시하지 않았지만, 최종적으로 상기 HDP산화막(47)과 측벽산화막(43) 및 질화막(45), 패드질화막(35)을 평탄화공정과 습식 딥공정 등을 통해 선택적으로 제거하여 소자분리막(미도시)을 형성한다.Subsequently, although not shown in the drawing, the HDP oxide layer 47, the sidewall oxide layer 43, the nitride layer 45, and the pad nitride layer 35 are selectively removed through a planarization process and a wet dip process. Not shown).
위에서와 같이, 본 발명에서는 기존의 방법보다 공정이 간단하면서 그 효과는 동일한 STI를 형성하게 된다. 즉, STI를 형성함에 있어 트렌치 식각을 진행하고, 측벽희생산화공정과 측벽산화공정을 진행한후에 질소와 산소를 함유한 혼합가스를 이용하여 아닐링을 진행해 주므로써 라이너질화막 형성공정과 라이너산화막 형성공정 및 조밀화 공정을 생략할 수 있다.As described above, in the present invention, the process is simpler than the existing method, and the effect is to form the same STI. That is, in forming the STI, the trench is etched, the sidewall dilution process and the sidewall oxidation process are performed, and then annealing is performed using a mixed gas containing nitrogen and oxygen, thereby forming the liner nitride film forming process and the liner oxide film forming process. And the densification step can be omitted.
이렇게 질소와 산소를 함유한 혼합가스를 이용한 아닐링공정을 적용하는 이유는, 도 3의 나이트로겐분포(SIMS)에서 보는 바와같이, 산소필름에 나이트로겐 (nitrogen) 아닐링을 적용할 경우 나이트로겐이 산화막의 내부로 확산하여 침투한후 반도체기판과 결합하므로써 질화막을 형성하기 때문이다. 즉, 측벽산화공정이 진행된 상태에서 나이트로겐 아닐링공정을 진행하므로써 산화막 아래에서 질화막을 형성하여 주므로써 식각에 의한 데미지 층을 회복시켜 주는 역할을 할 뿐만 아니라, 셀 대 셀간 리키지를 방지해 주는 라이너질화막의 역할을 하게 된다. The reason for applying the annealing process using a mixed gas containing nitrogen and oxygen, as shown in the Nitrogen Distribution (SIMS) of FIG. 3, is that when Nitrogen (Nitrogen) is applied to the oxygen film, Nitrogen is applied. This is because the nitride film is formed by diffusion into the oxide film and penetration into the semiconductor substrate. In other words, by performing the nitrogen annealing process in the sidewall oxidation process, a nitride film is formed under the oxide film to restore the damage layer due to etching, and also prevents cell-to-cell leakage. It will act as a nitride film.
그리고, 질화막이 산화막하부에 형성되므로 기존의 방법과 같이 질화막위에 라이너산화막을 일부러 증착해 주지 않아도 된다.Since the nitride film is formed under the oxide film, it is not necessary to intentionally deposit a liner oxide film on the nitride film as in the conventional method.
또한, 나이트로겐 아닐링을 이용한 산화막하부의 질화공정은 기존의 방법처럼 별도로 조밀화과정이 필요없이 아닐링과정에서 산화막의 조밀화는 이루어지게 된다. 그리고, 나이트로겐(NO)을 이용하는 경우에, N2O 등의 가스를 사용하는 경우보다 분해온도가 낮으므로 공정온도와 시간의 조절이 용이하다.In addition, in the nitriding process of the lower oxide layer using nitrogen annealing, the densification of the oxide layer is performed in the annealing process without the need for a separate densification process as in the conventional method. In the case of using nitrogen (NO), since the decomposition temperature is lower than in the case of using a gas such as N 2 O, it is easy to adjust the process temperature and time.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 소자분리막 형성방법에 의하면, 기존의 CVD 질화막대신에 질화공정을 적용하므로써 응력(stress)을 감소시킬 수 있다.As described above, according to the device isolation film forming method of the semiconductor device according to the present invention, the stress can be reduced by applying the nitriding process instead of the conventional CVD nitride film.
또한, 측벽 산화공정이후에 나이트로겐 아닐링을 적용하므로써 라이너산화막증착과 조밀화공정을 생략하므로써 공정단순화에 따른 원가절감을 꾀할 수 있다.In addition, by applying nitrogen annealing after the sidewall oxidation process, cost reduction due to process simplification can be achieved by omitting the liner oxide film deposition and densification process.
그리고, 산화막과 반도체기판의 계면에 질화막을 형성시켜 주므로써 셀 대 셀간의 리키지를 방지할 수 있다. By forming a nitride film at the interface between the oxide film and the semiconductor substrate, it is possible to prevent the cell-to-cell leakage.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도,1A through 1E are cross-sectional views of processes for describing a method of forming a device isolation film of a semiconductor device according to the prior art;
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도.2A through 2F are cross-sectional views of processes for describing a method of forming a device isolation film of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체소자의 소자분리막 형성방법에 있어서, 식각깊이에 따른 강도를 도시한 그래프. 3 is a graph showing the strength according to the etching depth in the method of forming a device isolation film of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 반도체기판 33 : 패드산화막31 semiconductor substrate 33 pad oxide film
35 : 패드질화막 37 : 감광막패턴35 pad nitride film 37 photosensitive film pattern
39 : 트렌치 41 : 측벽희생산화막39: trench 41: sidewall dimming film
43 : 측벽산화막 45 : 질화막43: sidewall oxide film 45: nitride film
47 : HDP산화막47: HDP oxide film
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