KR100473409B1 - 얕은 트렌치 분리 구조의 에지에서의 게이트 산화물의 품질을 향상시키기 위한 이온 주입 공정 - Google Patents

얕은 트렌치 분리 구조의 에지에서의 게이트 산화물의 품질을 향상시키기 위한 이온 주입 공정 Download PDF

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KR100473409B1
KR100473409B1 KR10-2000-7005714A KR20007005714A KR100473409B1 KR 100473409 B1 KR100473409 B1 KR 100473409B1 KR 20007005714 A KR20007005714 A KR 20007005714A KR 100473409 B1 KR100473409 B1 KR 100473409B1
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silicon substrate
silicon
isolation
trench
corners
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KR20010040280A (ko
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풀포드에이치.짐
메이찰스이.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
KR10-2000-7005714A 1997-11-25 1998-05-18 얕은 트렌치 분리 구조의 에지에서의 게이트 산화물의 품질을 향상시키기 위한 이온 주입 공정 Expired - Fee Related KR100473409B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/977,795 US5915195A (en) 1997-11-25 1997-11-25 Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure
US08/977,795 1997-11-25

Publications (2)

Publication Number Publication Date
KR20010040280A KR20010040280A (ko) 2001-05-15
KR100473409B1 true KR100473409B1 (ko) 2005-03-08

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KR10-2000-7005714A Expired - Fee Related KR100473409B1 (ko) 1997-11-25 1998-05-18 얕은 트렌치 분리 구조의 에지에서의 게이트 산화물의 품질을 향상시키기 위한 이온 주입 공정

Country Status (5)

Country Link
US (1) US5915195A (enExample)
EP (1) EP1034565A1 (enExample)
JP (1) JP2001524752A (enExample)
KR (1) KR100473409B1 (enExample)
WO (1) WO1999027578A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101392540B1 (ko) * 2006-10-17 2014-05-07 옴니비전 테크놀러지즈 인코포레이티드 패시베이션층 형성 방법

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9723468D0 (en) * 1997-11-07 1998-01-07 Zetex Plc Method of semiconductor device fabrication
US6040607A (en) * 1998-02-23 2000-03-21 Advanced Micro Devices, Inc. Self aligned method for differential oxidation rate at shallow trench isolation edge
EP0971415B1 (en) * 1998-06-30 2001-11-14 STMicroelectronics S.r.l. Process for the fabrication of a semiconductor non-volatile memory device with Shallow Trench Isolation (STI)
JP3409134B2 (ja) 1999-02-22 2003-05-26 沖電気工業株式会社 半導体装置の製造方法
US6287970B1 (en) 1999-08-06 2001-09-11 Agere Systems Inc. Method of making a semiconductor with copper passivating film
US6344415B1 (en) * 1999-09-15 2002-02-05 United Microelectronics Corp. Method for forming a shallow trench isolation structure
US6277697B1 (en) * 1999-11-12 2001-08-21 United Microelectronics Corp. Method to reduce inverse-narrow-width effect
US6174787B1 (en) * 1999-12-30 2001-01-16 White Oak Semiconductor Partnership Silicon corner rounding by ion implantation for shallow trench isolation
US6372567B1 (en) * 2000-04-20 2002-04-16 Infineon Technologies Ag Control of oxide thickness in vertical transistor structures
TW521377B (en) * 2000-08-29 2003-02-21 Agere Syst Guardian Corp Trench structure and method of corner rounding
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
KR20020037420A (ko) * 2000-11-14 2002-05-21 박종섭 반도체 소자의 소자분리막 형성방법
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
KR20030001928A (ko) * 2001-06-28 2003-01-08 동부전자 주식회사 반도체 장치의 에스티아이 형성 방법
DE10131705B4 (de) 2001-06-29 2010-03-18 Atmel Automotive Gmbh Verfahren zur Herstellung eines DMOS-Transistors
DE10131704A1 (de) * 2001-06-29 2003-01-16 Atmel Germany Gmbh Verfahren zur Dotierung eines Halbleiterkörpers
DE10131707B4 (de) * 2001-06-29 2009-12-03 Atmel Automotive Gmbh Verfahren zur Herstellung eines DMOS-Transistors und dessen Verwendung zur Herstellung einer integrierten Schaltung
DE10131706B4 (de) * 2001-06-29 2005-10-06 Atmel Germany Gmbh Verfahren zur Herstellung eines DMOS-Transistors
US6489223B1 (en) 2001-07-03 2002-12-03 International Business Machines Corporation Angled implant process
KR100753667B1 (ko) * 2001-12-29 2007-08-31 매그나칩 반도체 유한회사 반도체 제조 공정에서의 질소 플라즈마 소스를 이용한실리콘 질화막 증착 방법
JP2003347399A (ja) * 2002-05-23 2003-12-05 Sharp Corp 半導体基板の製造方法
US6806163B2 (en) * 2002-07-05 2004-10-19 Taiwan Semiconductor Manufacturing Co., Ltd Ion implant method for topographic feature corner rounding
KR20040008519A (ko) * 2002-07-18 2004-01-31 주식회사 하이닉스반도체 반도체 소자의 소자분리막 형성 방법
KR100529667B1 (ko) * 2003-01-09 2005-11-17 동부아남반도체 주식회사 반도체 소자의 트렌치 형성 방법
KR100950749B1 (ko) * 2003-07-09 2010-04-05 매그나칩 반도체 유한회사 반도체소자의 소자분리막 형성방법
DE10345347A1 (de) * 2003-09-19 2005-04-14 Atmel Germany Gmbh Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil
US7482252B1 (en) 2003-12-22 2009-01-27 Advanced Micro Devices, Inc. Method for reducing floating body effects in SOI semiconductor device without degrading mobility
US7160782B2 (en) * 2004-06-17 2007-01-09 Texas Instruments Incorporated Method of manufacture for a trench isolation structure having an implanted buffer layer
US7737009B2 (en) * 2007-08-08 2010-06-15 Infineon Technologies Ag Method of implanting a non-dopant atom into a semiconductor device
US20120181600A1 (en) * 2007-08-17 2012-07-19 Masahiko Higashi Sonos flash memory device
EP2073256A1 (en) 2007-12-20 2009-06-24 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for fabricating a semiconductor device and the semiconductor device made thereof
US9530674B2 (en) 2013-10-02 2016-12-27 Applied Materials, Inc. Method and system for three-dimensional (3D) structure fill
CN104157557A (zh) * 2014-08-15 2014-11-19 上海华力微电子有限公司 改善热载流子注入损伤的离子注入方法
CN114551244B (zh) * 2022-03-11 2025-08-12 上海华虹宏力半导体制造有限公司 一种垂直mos晶体管的制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666178A (en) * 1985-05-31 1987-05-19 Matthews Donald R Ski climber
NL8502765A (nl) * 1985-10-10 1987-05-04 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
JPS62142318A (ja) * 1985-12-17 1987-06-25 Mitsubishi Electric Corp 半導体装置の製造方法
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process
JPH01125935A (ja) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd 半導体装置の製造方法
JPH022116A (ja) * 1988-06-15 1990-01-08 Toshiba Corp 半導体装置の製造方法
US5057446A (en) * 1990-08-06 1991-10-15 Texas Instruments Incorporated Method of making an EEPROM with improved capacitive coupling between control gate and floating gate
US5112762A (en) * 1990-12-05 1992-05-12 Anderson Dirk N High angle implant around top of trench to reduce gated diode leakage
JPH05343515A (ja) * 1992-03-04 1993-12-24 Kawasaki Steel Corp 半導体装置及びその製造方法
JP3102223B2 (ja) * 1993-09-24 2000-10-23 住友金属工業株式会社 シリコン基板の酸化方法
US5406111A (en) * 1994-03-04 1995-04-11 Motorola Inc. Protection device for an intergrated circuit and method of formation
US5643822A (en) * 1995-01-10 1997-07-01 International Business Machines Corporation Method for forming trench-isolated FET devices
KR100197648B1 (ko) * 1995-08-26 1999-06-15 김영환 반도체소자의 소자분리 절연막 형성방법
US5780353A (en) * 1996-03-28 1998-07-14 Advanced Micro Devices, Inc. Method of doping trench sidewalls before trench etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101392540B1 (ko) * 2006-10-17 2014-05-07 옴니비전 테크놀러지즈 인코포레이티드 패시베이션층 형성 방법

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JP2001524752A (ja) 2001-12-04
KR20010040280A (ko) 2001-05-15
EP1034565A1 (en) 2000-09-13
WO1999027578A1 (en) 1999-06-03
US5915195A (en) 1999-06-22

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