KR100473303B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a method of manufacturing a semiconductor memory device, in which a short circuit between conductive layers is prevented due to salicide of a substrate surface during formation of a salicide structured gate electrode, thereby improving yield and reliability. In the manufacturing method of the semiconductor device which has the salicide process of forming the insulating film 207 formed by laminating | stacking a 1st oxide film, a nitride film, and a 2nd oxide film on a board | substrate, and forming the gate electrode of a salicide structure on this insulating film. In the salicide step, silicide reaction between the substrate 201 and the N + diffusion layer 213 is prevented by remaining the insulating film 207 in a region other than just below the gate electrode on the substrate.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a nonvolatile semiconductor memory device having a salicide structure and a method for manufacturing the same.

In a semiconductor memory device having an impurity conductive region in which a bit line of a memory cell array is formed on a substrate surface, the memory cell size can be reduced without the separation region between transistors separating the memory cells, thereby increasing the memory capacity. Suitable for However, since the bit line is formed of an impurity conductive region provided on the silicon substrate, the bit line cannot be adapted to the high speed operation due to the resistance value of the bit line, the parasitic capacitance, etc., and the bit line lengthens due to the increase in the memory capacity, making the high speed operation difficult. Become. Further, there is a problem such as a decrease in the write voltage applied to the memory cell due to the resistance of the bit line due to the increase in the bit line length. The applicant of this application proposes the semiconductor device for solving such a problem by patent application 2001-394216 (it is unpublished at the time of this application).

Hereinafter, as one of the background arts of the present invention, a rewritable nonvolatile semiconductor device having an ONO two-layer structure as a gate and a dielectric structure will be described with reference to FIG. 4. On the channel between the N + diffusion layers 124 of the P-type silicon substrate 121, a silicon oxide film is formed, a silicon nitride film serving as an electron trapping film is formed on the silicon oxide film, and a silicon oxide film is formed thereon. The ONO film 122 is comprised, and the conductive gate electrode 125 is formed on this. In FIG. 4, a configuration in which two bits are stored in one memory cell is schematically illustrated.

However, since the polysilicon used as the gate electrode has a relatively high specific resistance, a gate film is formed by laminating a high melting point metal or a quasi-noble silicide (MoSi ₂ , WSi ₂ , TiSi ₂ , CoSi _2, etc.) on the gate polysilicon. The resistance reduction is aimed at.

In addition, in order to suppress the gate resistance, the drain, and the source resistance due to miniaturization, the gate electrode is reduced in resistance and the source and drain resistance is reduced. In one process, the source and drain are silicided together with the gate electrode. Self-Align Silicide (Self-Align Silicide) structure has been important.

When the salicide technology is applied to a nonvolatile semiconductor memory device having an ONO film as a gate dielectric film by forming a bit line with an impurity conductive region (N + diffusion layer) provided on a silicon substrate, impurity conductivity other than the gate electrode formation region The surface of the silicon substrate between the regions reacts with the high melting point metal together with the gate polysilicon to be silicided, and there is a problem that the device separation by the PN junction does not function and the N + diffusion layers are short-circuited. This problem is described in detail later.

Accordingly, a problem to be solved by the present invention is to prevent occurrence of a short circuit between conductive layers due to suicide of the surface of a substrate in the formation of a gate electrode having a salicide structure in a semiconductor device using a conductive layer of impurities. The present invention provides a semiconductor memory device and a method of manufacturing the same that improve yield and reliability.

A method according to one aspect of the present invention for solving at least one of the above problems is a step of forming an insulating film formed by laminating in order of a first oxide film, a nitride film, and a second oxide film on a substrate, and on the insulating film, In the method of manufacturing a semiconductor device having a salicide step of forming a salicide-structured gate electrode, silicide is formed in the salicide step by remaining the insulating film in a region other than directly below the gate electrode on the substrate. This is to prevent the silicide reaction of the surface of the substrate in a region other than the target.

In the method according to another aspect of the present invention, the insulating film formed on the surface of the substrate forming the memory cell region and the first step of forming an insulating film formed by laminating the first oxide film, the nitride film, and the second oxide film on the substrate Is selectively removed, a second step of forming a conductive region made of an impurity extending in a plurality of parallelities in a region where the insulating film is removed, and a memory cell having the two adjacent parallel conductive regions as sources and drains; A third step of forming a salicide-structured gate electrode on the insulating film as a gate electrode of the transistor, wherein the insulating film remains in a region other than the channel region immediately below the gate electrode of the memory cell transistor, In the third step, the group in the region other than the suicided object To prevent the silicide reaction with the surface.

In the present invention, the first oxide film is formed by oxidizing with an In-Situ Steam Generation (ISSG) method. In the present invention, the second oxide film is formed by oxidizing the nitride film or by oxidizing with an In-Situ Steam Generation (ISSG) method.

In an apparatus according to another aspect of the present invention, a gate electrode having a salicide structure having an insulating film including first and second oxide films and a nitride film interposed between the first and second oxide films on a substrate and covering the insulating film. In the semiconductor device forming the semiconductor device, the insulating film is provided in a region other than directly below the gate electrode on the substrate.

According to another aspect of the present invention, there is provided a memory cell transistor including conductive regions made of impurities extending in parallel in a plurality of surfaces on a substrate constituting a memory cell array region, and having two adjacent conductive regions serving as a source and a drain. A dielectric film directly below the gate electrode, the insulating film including on the substrate surface a first and a second oxide film and a nitride film sandwiched by the first and second oxide films; In the semiconductor device provided, the insulating film is provided in a region other than the channel region immediately below the gate electrode of the memory cell transistor.

In the present invention, the insulating film is left at portions other than the channel region and the formation region of the conductive region of the memory cell array. In the present invention, preferably, the insulating film is left in a region between the conductive regions of the surface of the substrate at least in the memory cell array.

In the present invention, the remaining insulating film includes at least the first oxide film and the nitride film among three stacked films.

Embodiment of this invention is described. In a preferred embodiment of the present invention, a semiconductor device having an ONO film formed by laminating a first oxide film, a nitride film, and a second oxide film on a substrate in order to form a salicide-structured gate electrode, is provided on the substrate. The ONO film (122 in FIG. 1) is provided in a region other than just below the gate electrode (110 in FIG. 1). In the present invention, a memory cell including a conductive region (104 in FIG. 1) comprising an impurity diffusion layer formed in a plurality of parallel lines on a surface of a substrate forming a memory cell array region, and having two adjacent conductive regions as a source and a drain. A semiconductor device in which a dielectric film directly under a gate electrode of a transistor is formed on the substrate surface, and an insulating film 122 formed by laminating a first oxide film, a nitride film, and a second oxide film is formed, and a gate electrode having a salicide structure is formed on the insulating film. In the manufacturing method of the present invention, the insulating film 122 remains in a region other than the channel region immediately below the gate electrode of the memory cell transistor, so that the silicide reaction of the surface of the substrate in the region other than the silicidation target in the salicide process is performed. To prevent the occurrence of a short circuit between the conductive regions 104. Avoiding.

More specifically, a conductive region 104 made of impurities is formed on the substrate surface constituting the memory cell array region in parallel, and the wiring 105 on the upper substrate layer is formed by pairing the two conductive regions. Or it connects by the electrically-conductive area | region (104A of FIG. 11) of a board | substrate surface, and comprises a set of sub bit line. Further, a plurality of gate electrodes 110 are formed in a direction orthogonal to the longitudinal direction of the sub bit line to form a word line. One set of sub bit lines is connected to the main bit line 101 through the corresponding selection transistor 102. A plurality of selection transistors 102 are disposed opposite to both sides of the memory cell array, and a plurality of sets of negative bit lines connected to a plurality of selection transistors on one side of the memory cell array, and a plurality of selections on the other side of the memory cell array. A plurality of sets of sub bit lines respectively connected to the transistors are alternately arranged. As a gate dielectric film of a memory cell transistor, an insulating film (ONO film) 122 formed by stacking a first oxide film, a nitride film, and a second oxide film is formed on a substrate surface, and a gate electrode having a salicide structure is formed on the insulating film. . In the programmable nonvolatile semiconductor memory device having such a configuration, the insulating film 122 remains in a region other than just under the gate electrode of the memory cell array, so that in the salicide process, the conductive region 104 can be separated. The suicide of the surface of a board | substrate is prevented and the occurrence of a short circuit is avoided.

In the embodiment of the present invention, the insulating film 122 is left at a location other than the channel region and the formation region of the conductive region 104 of the memory cell array. In the present invention, preferably, the insulating film 122 is left in the region between the conductive regions 104 of the surface of the substrate in at least the memory cell array.

In the manufacturing method which concerns on this invention, in the preferable one Embodiment, the insulating film (207 of FIG. 5 (D)) formed by laminating | stacking a 1st oxide film, a nitride film, and a 2nd oxide film in this order on a board | substrate is formed. And selectively removing the insulating film formed on the surface of the substrate constituting the memory cell region, and forming a conductive region (213 in FIG. 6A) formed of impurities extending in parallel in a plurality of regions where the insulating film is removed. And a gate electrode of a salicide structure (212 in FIG. 10A) on the insulating film, as a gate electrode of a memory cell transistor having a source and a drain as the conductive regions which are two parallel to each other. Including a salicide process, the insulating film remains in a region other than the channel region immediately below the gate electrode of the memory cell transistor, In the salicide step, the silicide reaction between the metal constituting the gate electrode and the surface of the substrate in a region other than the silicidation target is prevented.

In this embodiment, at the time of film production of the 2nd and 1st oxide film which comprises an ONO film | membrane, you may oxidize and form by ISSG (In-Situ Steam Generation) method. By using the ISSG oxidation method, the repetitive life of writing / erasing peculiar to the semiconductor memory device of the MONOS structure can be particularly improved.

In the present invention, the remaining insulating film includes at least a lower silicon oxide film and a silicon nitride film thereon among three stacked films.

EMBODIMENT OF THE INVENTION In order to demonstrate further embodiment of this invention mentioned above, the Example of this invention is described with reference to drawings. FIG. 1 is a diagram schematically showing an example of a layout configuration of a semiconductor memory device according to the present invention, wherein a part (block) of a memory cell array when the present invention is implemented in a rewritable nonvolatile semiconductor memory device is shown in FIG. Is shown. According to one embodiment of the present invention, as shown in FIG. 1, the ONO film 122 remains in a region other than the channel region immediately under the gate electrode 110 of the memory cell MC. I'm making it. Hereinafter, with reference to FIG. 1, the structure of this Example is demonstrated.

Referring to FIG. 1, a memory cell array in which a plurality of memory cells MC are arranged in an array shape has a hierarchical bit line structure consisting of a main bit line and a sub bit line, of which a sub bit line is, for example, a P type. A plurality of conductive regions (also referred to as "N + buried lines") 104 formed of N + diffusion layers formed on the surface of the silicon substrate are extended in parallel. The main bit line 101 made of aluminum wiring or the like is pattern-formed in the second wiring layer 2Al, for example, and is selected from a selection transistor ("block selector transistor") which is controlled on / off by inputting a selection control line to a gate. And a negative bit line through the " block select transistor "

More specifically, the first group of conductive regions 104 (for example, a, b, e, etc.) formed on the memory cell array region of the substrate surface from the one side of the memory cell array to the side facing the plurality thereof in parallel. And a second group of conductive regions 104 (for example, c, d, ...) extending in parallel from the other side of the memory cell array to the one side. .

In the direction orthogonal to the extending direction of these conductive regions 104, a plurality of (N) gate electrodes 110 extending in parallel with each other are formed on the ONO film 122.

In the conductive region 104, the selection transistor 102 in which two conductive regions belonging to the same group form a negative bit line in one set, and one of the two conductive regions forming the negative bit line is connected to a gate. Is connected to the diffusion layer 108, and the main bit line 101 of the second wiring layer is connected to the other diffusion layer 107 of the selection transistor 102 by a through hole 109 and a contact (not shown).

In each of the pair of conductive regions 104 spaced apart from each other and forming one negative bit line, one end of each of the first wiring layers 1Al is formed by the contacts 111 having end portions positioned on the side of the selection transistor 102. Is connected to the wiring 105.

Between two conductive regions a and a of the first group constituting a set of sub bit lines, a set of sub bit lines is selected to two main bit lines located on both sides of the main bit line connected through the selection transistor. Two main bit lines adjacent to each other through a select transistor on the opposite side to the select transistor to which each of the pairs of conductive regions constituting two sub bit lines connected through the transistors, respectively, b and e Four systems of one c and d each of the conductive region pairs constituting two sub-bit lines, each connected to the second sub-bit line, are arranged.

On the substrate, through the ONO film 122, a plurality of (N) gates of the salicide structure in which metal silicide is formed on the polysilicon gate (not shown) and both of the diffusion layer serving as the source / drain are self-aligned. The electrodes 110 are arranged parallel to each other across the conductive regions 104. These gate electrodes 110 become word lines, and a predetermined voltage is selectively given to a row designated by a row decoder (not shown).

On both sides of the N gate electrodes 110 (upper and lower sides of the memory cell array in FIG. 1), a gate electrode 103 (referred to as a "selective gate electrode") extends over the diffusion layer 107 and the diffusion layer 108. To be arranged respectively. The select transistor 102 is formed using the select gate electrode 103 as a gate and the drain layer 107/108 as a drain / source. The selection gate electrode 103 has a salicide structure in which a metal silicide is formed on a polysilicon gate (not shown).

In one embodiment of the present invention, device isolation between the select transistors 102 is performed with the field oxide film 106. With such a configuration, the select transistor 102 can be made higher withstand voltage compared to element isolation by impurity regions formed by ion implantation or the like, and the voltage drop supplied to the conductive region of the memory cell to be written during writing can be reduced. It can be suppressed.

In the transistors constituting the memory cell MC, the gate electrodes 110 arranged in common for each row (row) form a word line, and the word line is selectively activated by a row decoder (not shown). In the selection transistor 102, each selection gate electrode 103 is common to both sides of the memory cell array, and the selection gate electrode 103 forms a selection control line.

The main bit line 101 is formed on the second aluminum wiring layer 2Al, and is selectively activated by receiving a column selection signal based on a column decoder (not shown). That is, corresponding to the address data, for example, two main bit lines are designated to apply a power supply potential and a ground potential to each of them, and the selection transistor 102 connected to the designated main bit line 101 is turned on. The conductive region 104 constituting the negative bit line is connected to the main bit line 101, so that the two adjacent conductive regions 104 are selectively activated.

The main bit line 101 provided in the second aluminum wiring layer 2Al on the upper substrate layer is connected to the first aluminum wiring layer 1Al through the through hole TH 109, and is selected through a contact (not shown). It is connected to the diffusion layer 107 of 102, and the diffusion layer 108 of the selection transistor 102 extends in the substrate surface as it is, and forms one side of the conductive region 104 forming a negative bit line pair. The conductive region 104 is formed on the substrate surface together with the diffusion layers 107 and 108.

In the memory cell MC, an oxide-nitride-oxide (ONO) film formed by overlapping a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in a channel region of a gap between adjacent conductive regions 104. Has (122). The ONO film 122 directly under the gate electrode of the memory cell MC acts as an electron trap film to form a memory node. On the second silicon oxide film of the ONO film 122, a gate electrode 110 is formed in common in a direction orthogonal to the longitudinal direction of the conductive region 104 in a plurality of memory cells in a row to form a word line. .

As described above, in the MONOS type memory cell, when the gate electrode having the Co salicide structure is formed, the surface of the substrate between the source / drain diffusion layer reacts with Co and silicides, causing a PN junction to be shorted. .

Therefore, in this embodiment, the ONO film is also left in a region other than directly under the gate electrode to prevent suicide of the substrate surface. In this embodiment, the ONO film 122 remains in a region other than the conductive region 104 made of the N + diffusion layer on the substrate surface.

FIG. 3 is a diagram showing the circuit configuration of the memory cell array of one embodiment of the present invention, showing an example of the layout in FIG. In Fig. 3, reference numeral 101 denotes a main bit line, 102 denotes a selection transistor, 103 denotes a selection control line SL, 104 denotes a negative bit line (conductive area), 105 denotes a wiring connecting a conductive region of a negative bit line, 110 denotes a word line WL. to be. In the N + diffusion layer forming the negative bit line, the unit resistance value R is shown between the memory cells. When the selection control line SL is at the high level, the selection transistor 102 is turned on, and the main bit line is connected to the sub bit line. A pair of conductive regions constituting a set of sub bit lines connected to the main bit line A through the selection transistor TrA forming one of the selection transistors of the first group of one side of the memory cell array in which the plurality of memory cells MC are arranged in an array shape a In the region between a, the right conductive region b of the pair of conductive regions constituting two sets of main bit lines B connected to both side selection transistors TrB and TrE of the selection transistor TrA and two negative bit lines connected to E, Each one of the left conductive regions e is provided inside the conductive region pairs a and a, and the two main bit lines C are formed through the selection transistors TrC and TrD which constitute the second group of selection transistors located on the other side of the memory cell array. , One of the left conductive region c and the right conductive region d among the conductive region pairs forming two sets of negative bit lines connected to D is provided inside the conductive region pairs b and e.

Also for each of the conductive region pairs b and e connected to the other selection transistors TrB and TrE arranged on one side of the memory cell array, four conductive regions connected to the other selection transistor are connected between each of the selection transistors on one side of the memory cell array. Each of the conductive region pairs and each of the conductive region pairs connected to the selection transistors on the other side) are arranged, and the layout configuration in which four sets of sub-bit lines are replaced is repeated along the word line direction. do. For example, when the memory cell MC1 including the word line WL8 and the conductive regions a and b is selected, the selection gate electrode SL is set at a high level, the corresponding block is selected, and the word line WL8 is selected to have a predetermined constant voltage Vg. The predetermined constant voltage H or ground potential L is supplied to the main bit lines A and B. As shown in FIG.

As described above, according to the present embodiment, a pair of negative bit lines are composed of two conductive regions 104 connected to each other by a wiring 105, and a plurality of pairs of negative bit lines are alternately arranged to thereby select a selection transistor ( The increase in the chip area can be suppressed with respect to the increase in the memory capacity while reducing the resistance value of the conductive region from 102 to the far end. Further, according to the present invention, by performing element isolation of the selection transistor in the field oxide film, high breakdown voltage of the selection transistor is realized, and it is possible to suppress a decrease in the write current (write voltage) to the memory cell during writing.

4 is a diagram schematically showing the configuration of a MONOS type memory cell MC. An N + diffusion layer 124 serving as a source or a drain is provided on the P-type silicon substrate 121, and an insulating oxide film 123 is formed thereon, and the side edges of the substrate 121 exposed surface and the insulating oxide film 123 are formed. The ONO film 122 is formed over the part, and the gate electrode 125 of the salicide structure which extends along the direction orthogonal to the longitudinal direction of the N + diffused layer 124 is arrange | positioned on the ONO film 122. . Each N + diffusion layer 124 end of the ONO film becomes a storage node 126 that traps electrons, and two bits of information are stored in one cell. The ONO film 122 is composed of an oxide film (for example, silicon oxide film) of the first layer, a nitride film (for example, silicon nitride film) of the second layer, and an oxide film (for example, silicon oxide film) of the third layer. . For details of writing and reading of a memory cell provided with an ONO film, reference is made to, for example, Japanese Patent Application Laid-Open No. 2001-512290 or Patent Application 2001-394216.

2B is a direction orthogonal to the longitudinal direction of the conductive region 104 of the substrate between the conductive regions 104 in the regions (regions other than the memory cell region) indicated in FIG. 1A. It is a figure which shows typically the cross section along. That is, in FIG. 2B, reference numeral 124 corresponds to the conductive region 104 of FIG. 1. In this embodiment, the ONO film 122 is provided between the two conductive regions 124 in addition to the channel region immediately below the gate electrode 110 (see FIG. 1).

As a comparative example, as shown in FIG. 2A, when the ONO film is not provided in a region other than the channel region between the two conductive regions 124 directly below the gate electrode 110, Co salli At the time of forming the gate electrode of the side structure, Co silicide (salicide) is formed on the surface of the substrate between the two conductive regions 124, and PN separation is not performed, resulting in a short circuit and a defect.

As described above, in the present embodiment, the ONO film 122 formed in the panel formation region immediately below the gate electrode between the N + diffusion layers 124 is left between the N + diffusion layers 124 which are separated from each other. It may be left in arbitrary areas other than the formation area of an N + diffused layer on a board | substrate.

Next, with reference to FIGS. 5-10, an example of the manufacturing method of the semiconductor memory device which concerns on one Embodiment of this invention is demonstrated. 5 to 10 schematically show the cross-sections of the main manufacturing steps of the manufacturing method according to the embodiment of the present invention in the order of the processes. 5 to 10 simply divide the drawings for convenience of drawing creation. 5 to 10, the memory cell represents an element region (memory cell array) of the memory cell, and HV is also referred to as a high breakdown voltage ("HV type" or "Vpp type") of the peripheral circuit of the memory. Vcc denotes a device region of a power supply system (also referred to as a "Vcc system"), and p and n of HVp, HVn, Vccp, and Vccn denote p-channel transistors and n-channel transistor device regions, respectively. The selection transistor is arranged at the end of the memory cell region.

As shown in Fig. 5A, in order to form an inactive region on the P-type silicon semiconductor substrate 201, for example, the field oxide film 202 is selectively formed by a LOCOS (Local 0xidation of Silicon) method. Form. The film thickness of the field oxide film 202 is, for example, 200-400 nm (nanometer). The element region separated by the field oxide film 202 is divided into, for example, each part of the memory cell and the high breakdown voltage transistor (HV system) and the normal power supply transistor (Vcc system) of the peripheral circuit.

Next, a well is formed in the P-type silicon semiconductor substrate 201 by ion implantation and annealing. In this embodiment, twin wells of N wells and P wells are formed.

First, as shown in Fig. 5B, the sacrificial oxide film 203 is formed in the exposed region of the P-type silicon semiconductor substrate 201 with a film thickness of, for example, 10-30 nm. The film formation of the sacrificial oxide film 203 is performed by normal dry oxidation or steam oxidation. Thereafter, regions other than the p-channel transistor formation region on the substrate are selectively covered with the photoresist 204, and P (phosphorus) ions are implanted in the region where the photomask is not formed, and the dose amount is 700-500 Kev. It is implanted at 1E13 cm ² (where EX represents an X power of 10 and 1EX represents 1 × 10 ^X ) to form an N-well 205. At this time, the energy of the ion implantation is set to pass through the field oxide film 202 without passing through the photoresist 204.

Then, in order to control the threshold value of the p-channel transistor to a desired value, ion implantation of P (phosphorus) or B (boron) is performed on the surface of the region of the N well 205. This is because the threshold value of the MOS transistor in the well depends on the profile of the impurity concentration in the well, thereby controlling the surface concentration.

Next, as shown in Fig. 5C, regions other than the n-channel transistor formation region are selectively covered with the photoresist 204, whereby B ions are formed in the n-channel transistor formation region where the photoresist is not formed. Is injected, for example, with an injection energy of 300-200 Kev and a dose amount of 1E13 cm ² to form a P-well 206. At this time, the implanted energy is set to pass through the field oxide film 202 without passing through the photoresist 204.

Then, in order to control the threshold value of the n-channel transistor to a desired value, implantation of B or P ions is performed on the surface of the region of the P well 206. Moreover, you may heat-process N well and P well collectively.

Subsequently, the photoresist 204 is removed by, for example, ashing in plasma, and the sacrificial oxide film 203 on the silicon semiconductor substrate 201 is removed using, for example, buffered hydrofluoric acid. In the following description, the photoresist is removed by ashing or the like in plasma.

Next, as shown in FIG. 5D, an ONO film 207 (a silicon oxide film, a silicon nitride film, and a silicon oxide film) is formed on the silicon semiconductor substrate 201. The ONO film shown at 207 has a laminated structure of three layers of a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film.

The lower silicon oxide film is formed, for example, at a film thickness of 6-10 nm in an oxidizing atmosphere at 750-850 ° C. Alternatively, the underlying silicon oxide film may be formed by an In-Situ Steam Generation SiO ₂ (ISSG) method. For this ISSG oxidation method, reference is made, for example, to the description of IEEE Electron Device Lett. Vol. 21, No. 9 p430-432, 2000. By using the ISSG oxidation method, it is expected that the repetition life of writing / erasing peculiar to the semiconductor memory device of the MONOS structure is particularly improved. This is because the electron trap decreases due to the ISSG oxidation, so that the amount of electrons trapped in the memory node of the ONO film during the repetitive operation decreases, thereby reducing the characteristic variation.

In the ONO film 207, the silicon nitride film of the lower silicon oxide film is formed by CVD (Chemical Vapor Depositin) method. As the film thickness of the silicon nitride film, in consideration of the amount to be oxidized at the time of forming the silicon oxide film formed on the upper layer, the film thickness of the final silicon nitride film is adjusted to be 2-10 nm, for example.

The silicon oxide film on the upper layer of the ONO film 207 is formed by oxidizing the silicon nitride film. At this time, the silicon nitride film is formed by oxidizing, for example, in an oxidizing atmosphere at 1000-1150 占 폚. As another coating method of the silicon oxide film on the upper layer of the ONO film 207, of course, it may be oxidized by the ISSG oxidation method. The film thickness of the upper silicon oxide film becomes like this. Preferably it is 3-10 nm.

Next, as shown in Fig. 6A, the ONO film 207 in the region serving as the N + diffusion layer is removed in the memory cell region in the future. At that time, in the memory cell region, the ONO film 207 other than the region serving as the N + diffusion layer is covered with the photoresist 204 and is left as it is. In addition, the regions of the high withstand voltage and the normal power supply transistor on the peripheral circuit side are covered with the photoresist 204. In the memory cell region, in the future, the removal of the ONO film 207 on the region serving as the N + diffusion layer is performed by plasma etching in a gas atmosphere of CF ₄ or CHF ₃ + O ₂ system.

Thereafter, As (arsenic) ions are implanted into the silicon substrate 201 with an implantation energy of 30-60 Kev and a dose amount of 1E15 cm ² to form an N + diffusion layer 213.

The N + diffusion layer 213 in the memory cell region corresponds to the diffusion layers 107 and 108 of the selection transistor 102 in FIG. 1 in addition to the conductive region 104 of the memory cell MC shown in FIG. 1. . 1, the longitudinal cross sections (cross sections along the longitudinal direction of the main bit line 101) of the diffusion layers 107 and 108 of the selection transistor 102 and the two conductive regions 10 of the memory cell MC are shown. The cross section in the horizontal direction (cross section along the longitudinal direction of the gate electrode 110) of Fig. 1 is orthogonal to each other, but in Figs. 6 to 10, these are typically shown in the same drawing.

Next, a photoresist 204 is provided so as to expose the ONO film in the region of the transistor of the high breakdown voltage (HV system) and the normal power supply system (Vcc system) on the peripheral circuit side, and the region in which the selection transistor is formed in the future.

As shown in Fig. 6B, the photoresist 204 is used as a mask, and the ONO film on the diffusion layer 213 in the region in which the selection transistor (selector portion) is formed in the future and the transistors in the peripheral circuit portion are formed. The ONO film in the region to be formed is etched and removed in a plasma atmosphere.

Subsequently, the photoresist 204 is removed. As shown in FIG. 6C, the surface of the silicon semiconductor substrate 201 is oxidized using the remaining ONO film 207 and the field oxide film 202 as a mask, for example, a film of 10-20 nm. A silicon oxide film (called a "first gate oxide film") 208 having a thickness is formed.

Next, as shown in Fig. 6D, the photoresist 204 is selectively provided on the n and p-channel transistor regions of the memory cell region, the selection transistor, and the high withstand voltage meter (HV system). Using the resist 204 as a mask, the first gate oxide film 208 in the region where the transistor of the power supply system (Vcc system) is normally formed is etched away.

Next, as shown in Fig. 7A, the silicon semiconductor substrate 201 in the region in which the Vcc-based transistors are formed is oxidized, for example, in a silicon oxide film having a thickness of 3-10 nm ("second Gate oxide film ”(209). At this time, since the first gate oxide film 208 formed earlier is not removed from the gate oxide film (high-voltage transistor gate oxide film) in the formation region of the transistor of the high withstand voltage (HV system), the second gate oxide film 209 As a result, the film thickness of the first gate oxide film 208 becomes thicker than that of the silicon oxide film. The film thickness of the gate insulating film of the Vcc system and the film thickness of the gate insulating film of the HV system are respectively set in accordance with the operating voltage of the transistor.

Next, on the substrate, phosphorus doped polysilicon is deposited using the CVD method. The film thickness becomes 100-200 nm, for example. Next, using a photoresist (not shown) as a mask, etching is performed in a plasma atmosphere to form a gate electrode (polysilicon gate electrode) 210 as shown in FIG. At this time, at least the silicon nitride film and the lower silicon oxide film of the ONO film 207 are left in the memory cell region. In FIG. 7B, the region enclosed by A1 represents two gate electrodes 110 (polysilicon gate 210 of A1) as seen from the selection transistor 102 side of FIG. 1, for example. This is seen from the end face of the arrow line X direction.

Next, as shown in Fig. 7C, the peripheral circuit portion is covered with the photoresist 204, and B (boron) ions are implanted for the purpose of device isolation between the N + diffusion layers 213 of the memory cell. do. At this time, the injection energy that does not penetrate the polysilicon gate electrode 210 or the field oxide film 202 is selected. As for the implantation energy of B ion, 15 Kev and the dose amount are about 5E12-5E13cm <2>, for example.

Next, the photoresist 204 is applied, exposed and developed to remove the photoresist in the n-channel transistor region of the high breakdown voltage (HV system) and the normal voltmeter (Vcc system). As shown, the low concentration region (also called "LDD region" or "extension region") of LDD (Lightly Doped Drain) structure of n-channel transistor of high breakdown voltage (HV system) and normal power supply system (Vcc system) is shown. In order to form, P (phosphorus) is inject | poured, for example about 30Kev of implantation energy and 5E13cm < ² > of dose amounts.

Subsequently, as shown in FIG. 8B, B (boron) is used to form a low concentration region of the LDD structure of the p-channel transistor of the high breakdown voltage (HV system) and the normal power supply system (Vcc system). For example, 15Kev of injection energy and 5E13cm < ² > of dose amounts are injected. It may also be used in combination with the implantation B (see (C) of FIG. 7) of the N + diffusion layer of the memory cell.

After removing the photoresist, as shown in FIG. 8C, the sidewall (sidewall) spacer 211 of the gate polysilicon electrode 210 is formed by a known method. That is, as an example, a silicon oxide film having an isotropic (conformal) step coverage is deposited by CVD or the like, and is anisotropically etched to leave sidewall portions. The film thickness of the sidewall spacers 211 determines the width of the low concentration region forming the electrical junction with the channel of the source / drain diffusion layer. In this embodiment, the thickness is, for example, about 50-200 nm.

Next, as shown in FIG. 9A, the photoresist 204 covers the memory cell region and the n-channel transistor region, and the source and drain diffusion layers 214 (collect region of the LDD structure) of the p-channel transistor are covered. Form. In that case, Preferably, BF2 (boron difluoride) ion is implanted, for example, about 15Kev of implantation energy and about 1E15-1E16cm < ² > of dose amounts.

Next, as shown in FIG. 9B, the photoresist 204 covers the memory cell region and the p-channel transistor region to form the source and drain diffusion layers 215 (also referred to as contact regions) of the n-channel transistor. do. In that case, As (arsenic) is inject | poured, for example about 50Kev of implantation energy and 1E15-1E16cm < ² > of dose amounts. Thereafter, if necessary, after the heat treatment, the silicon oxide film or the like present on the surface of the salicideized portion is removed.

Subsequently, as shown in Fig. 10A, Co is formed on the surface of the substrate by, for example, a film thickness of about 8-20 nm by the sputtering method. That is, this Co sputtering film is formed in the whole substrate. Then, for salicide formation, by performing annealing (lamp annealing), CoSi ₂ is formed at the portion in contact with Co, silicon, and polysilicon. On the other hand, nothing occurs in a region where the silicon oxide film (SiO ₂ ) and the Co sputtering film are in contact with each other, such as the sidewall spacer 211. In general, lamp annealing is performed at 650-720 ° C. for 11-60 seconds, for example. As a result, the surface of the polysilicon 210 of the gate electrode is silicided simultaneously with the diffusion layers (collect regions) 214 and 215 of the source / drain to form Co salicide 212.

Next, a process of removing unsalided Co on the substrate such as the surface of the sidewall spacer 211 in contact with SiO ₂ is performed. The Co sputtering film on the sidewall spacers 211 is removed by wet processing or the like.

In this embodiment, in the salicide step, Co cannot react with the silicon substrate at the location where the ONO film 207 is left, and short-circuiting between the diffusion layers N + is avoided.

Next, as shown in FIG. 10B, an interlayer BPSG (Boro-Phospho Silicate Glass) film 216 is formed, and the contact hole 217 is opened.

The W plug 218 is filled in the contact hole 217, a metal film is deposited on the entire surface of the substrate, and a pattern is formed by a photoresist and etching process to form a metal wiring layer 219.

11 is a diagram showing the layout of a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 11, this embodiment differs from the configuration shown in FIG. 1, and ends of the pair of conductive regions 104 constituting the negative bit line are connected in the conductive region 104A, and the main bit The line 101 is provided in the first aluminum wiring layer 1Al and is connected to the diffusion layer of the selection transistor 102 by contact.

Also in this embodiment, the ONO film 122 is provided remaining in any region except for the N + diffusion layer in addition to the channel region immediately under the gate electrode 110. Referring to FIG. 11, the semiconductor device of this embodiment includes a plurality of conductive regions 104 which are separated from each other and extend in parallel in one direction on the substrate surface, and pair the two conductive regions 104. (E.g., a and a), one end of the pair of conductive regions is connected to the substrate surface in a conductive region 104A provided in a direction orthogonal to the conductive region 104 to form a set of negative bit lines. have. Both the conductive region 104 and the conductive region 104A are formed of an N + diffusion layer formed on the surface of a P-type silicon semiconductor substrate, and a pair of negative bit lines have a U-shaped pattern in two-dimensional shape. Select transistors 102 for connecting a set of sub bit lines to corresponding main bit lines 101 are respectively disposed on both sides of the memory cell array and connected to the select transistor 102 disposed on one side of the memory cell array. A plurality of sets of sub bit lines that are used and a plurality of sets of sub bit lines that are connected to the selection transistor 102 arranged on the other side of the memory cell array are alternately arranged. Also in this embodiment, the gate electrode of the transistor of the peripheral circuit (not shown) and the gate electrode 103 of the selection transistor 102 have a Co salicide structure, and the gate electrode of the memory cell whose ONO film is the gate dielectric film ( 110 also has a Co silicide structure.

Even in the structure of this embodiment, in the salicide process of the gate electrode 110, since the surface of the silicon substrate between the two conductive regions 104 is covered with the ONO film, Co silicide is not formed and the conductive region 104 is Short circuits are avoided.

As mentioned above, although this invention was demonstrated based on the said Example, this invention is not limited only to the structure of the said Example, The various deformation | transformation and correction which a person skilled in the art can make within the scope of the invention of each claim of the claim of this application. Of course it includes. For example, the program and readable nonvolatile semiconductor memory device has been described as an example, but the present invention can be applied to a read-only semiconductor memory device. Moreover, although the memory cell provided with the ONO film | membrane which has two electron trap areas which store two bits independently in one cell was demonstrated, this invention is not limited to this structure, The structure which stores one bit in one cell is explained. This may also be applied to any MONOS transistor. In addition, the wiring provided in the upper layer of a board | substrate is not limited to aluminum wiring, Of course, arbitrary metal wiring of low resistance is applicable.

And it is not limited to Co salicide, It is applicable to the salicide structure of arbitrary high melting metals or quasi-noble metals which can aim at low resistance, such as Ti salicide.

As described above, according to the present invention, in the semiconductor device having the ONO film, since the ONO film is left in a region other than the channel region, the reaction between the metal and the silicon substrate in the salicide step does not occur in the region, and the impurities The silicidation of the substrate surface between the two conductive regions made of the diffusion layer is avoided, and as a result, the reliability of the device and the product yield can be improved.

According to the present invention, since the ONO film serving as the electron trapping film is used as the silicide protection film of the substrate as it is in the memory cell, the salicide step is not added to the manufacturing process. It is possible to reliably prevent silicide formation of the surface of the substrate between the conductive regions formed of the impurity diffusion layer, and to improve the reliability of the device while suppressing an increase in the manufacturing process and cost.

According to the present invention, by using the ISSG oxidation method for the first and second oxide films of the ONO film, the repetitive life of writing / erasing peculiar to the semiconductor memory device of the MONOS structure can be particularly improved.

In addition to the above effects, according to the present invention, a pair of negative bit lines are formed of two conductive regions which are connected to each other, and a plurality of sets of negative bit lines are alternately arranged so that a plurality of negative bit lines are alternately arranged. While reducing the resistance value, it is possible to suppress the increase in the chip area with respect to the increase in the memory capacity. In addition, according to the present invention, by performing element isolation of the selection transistor in the field oxide film, high breakdown voltage of the selection transistor is realized, and a decrease in the write current (write voltage) to the memory cell during writing can be suppressed. The practical value is quite high.

1 is a diagram showing a layout configuration of one embodiment of the present invention.

FIG. 2 is a diagram schematically showing a cross section of the region A in FIG. 1, (B) is a comparative example, and (A) is a diagram for explaining an embodiment of the present invention. FIG.

3 shows an equivalent circuit of FIG. 1. FIG.

4 is a diagram schematically showing a configuration of a memory cell having an ONO film and having a 2-bit memory node.

5 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 1).

6 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 2).

7 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 3).

8 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 4).

9 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 5).

10 is a cross-sectional view schematically illustrating the main parts of the manufacturing process of the embodiment of the present invention in the order of the process (No. 6).

11 shows a layout of another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: main bit line

102: selection transistor (block selection transistor)

103: gate electrode (block selection line SL)

104: conductive region (sub bit line)

105: wiring

106: field oxide film

107, 108: diffusion layer

109: through hole (TH)

110: gate electrode (word line WL)

111: Contact

112: wiring

113: wiring

121: semiconductor substrate

122: ONO film

123: insulating oxide film

124: N + diffusion layer

125: gate electrode

126: memory node

201: P-type silicon substrate

202: field oxide film

203: sacrificial oxide film

204 photoresist

205: N well

206: P well

207: ONO film

208: first gate oxide film

209: second gate oxide film

210: gate polysilicon

211 sidewall spacers

213: N + diffusion layer

214: diffusion layer (source / drain)

215: diffusion layer (source / drain)

216: interlayer BPSG membrane

217: contact hole

218: contact W plug

219 metal wiring

Claims (24)

Forming an insulating film formed by laminating a first oxide film, a nitride film, and a second oxide film in this order on a substrate; A salicide process of forming a salicide-structured gate electrode on the insulating film, By remaining the insulating film in a region other than the region immediately below the gate electrode on the substrate, in the salicide step, silicide reaction of the surface of the substrate in a region other than the silicide target is prevented. Manufacturing method. Forming an insulating film formed on the substrate by laminating the first oxide film, the nitride film, and the second oxide film in this order; Selectively removing the insulating film formed on the surface of the substrate forming the memory cell region; A second step of forming a conductive region made of impurity formed in a plurality of parallel directions in a region where the insulating film is removed; A third step of forming a gate electrode of a memory cell transistor having the adjacent conductive regions as a source and a drain, adjacent to each other, on the insulating film, In the step of forming the gate electrode of the memory cell transistor by remaining the insulating film in a region other than the channel region immediately below the gate electrode of the memory cell transistor, the silicide reaction of the surface of the substrate in a region other than a silicide target is performed. The manufacturing method of the semiconductor device characterized by the above-mentioned. A conductive region made of impurities is formed on the surface of the substrate constituting the memory cell array region and extends in parallel; Pairing the two conductive regions, the wirings on the upper layer of the substrate or the conductive regions on the substrate surface are connected to form a set of negative bit lines. A plurality of gate electrodes are formed in a direction orthogonal to the longitudinal direction of the sub bit line to form a word line, The one set of sub bit lines is connected to the main bit line through a selection transistor, A plurality of the selection transistors are arranged opposite to both sides of the memory cell array, A plurality of sub bit lines connected to a plurality of select transistors on one side of the memory cell array and a plurality of sub bit lines connected to a plurality of select transistors on the other side of the memory cell array are arranged alternately, The gate electrode formed on the gate dielectric film of the memory cell transistor has a salicide configuration, Forming an insulating film formed by laminating in order of a first oxide film, a nitride film, and a second oxide film on the substrate surface as the gate dielectric film; A salicide process of forming a salicide-structured gate electrode on said insulating film, The insulating film remains in a region other than the channel region immediately below the gate electrode of the memory cell transistor to prevent the silicide reaction of the surface of the substrate in a region other than the silicide target in the salicide process of the gate electrode. The manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 1, The first oxide film and / or the second oxide film are formed by oxidizing with an in-situ steam generation (ISSG) method. The method of claim 2, The first oxide film and / or the second oxide film are formed by oxidizing with an in-situ steam generation (ISSG) method. The method of claim 3, The first oxide film and / or the second oxide film are formed by oxidizing with an in-situ steam generation (ISSG) method. The method of claim 1, And the second oxide film is formed by oxidizing the nitride film. The method of claim 2, And the second oxide film is formed by oxidizing the nitride film. The method of claim 3, And the second oxide film is formed by oxidizing the nitride film. The method of claim 3, And the insulating film is left at a location other than the channel region and the formation region of the conductive region of the memory cell array. The method of claim 3, And the insulating film is left in a region between at least the conductive regions of the surface of the substrate of the memory cell array. The method of claim 1, The remaining insulating film includes at least the first oxide film and the nitride film among three stacked films. The method of claim 2, The remaining insulating film includes at least the first oxide film and the nitride film among three stacked films. The method of claim 3, The remaining insulating film includes at least the first oxide film and the nitride film among three stacked films. An insulating film comprising a first and a second oxide film on the substrate and a nitride film sandwiched between the first and second oxide films, the gate electrode having a salicide composition on the insulating film; The semiconductor device is also formed in a region other than directly below the gate electrode on the substrate. A conductive region made of an impurity extending in parallel in a plurality on the surface of the substrate constituting the memory cell array region, A memory cell transistor having two adjacent conductive regions as a source and a drain is a dielectric film directly under the gate electrode, and includes a first and a second oxide film and a nitride film sandwiched with the first and second oxide films on the substrate surface. Comprising an insulating film comprising a, including a gate electrode of the salicide configuration on the insulating film, And the insulating film is also included in a region other than the channel region immediately below the gate electrode of the memory cell transistor. A surface of the substrate constituting the memory cell array region, comprising a conductive region made of impurities, which extends in plurality in parallel, The two conductive regions are paired and connected in the wiring of the upper layer of the substrate or the conductive region of the substrate surface to form a set of negative bit lines. A plurality of gate electrodes are arranged in a direction orthogonal to the longitudinal direction of the sub bit line to form a word line, The one set of sub bit lines is connected to the main bit line through a selection transistor, A plurality of the selection transistors are arranged opposite to both sides of the memory cell array, A plurality of sub bit lines connected to a plurality of select transistors on one side of the memory cell array and a plurality of sub bit lines connected to a plurality of select transistors on the other side of the memory cell array are arranged alternately, The memory cell transistor includes an insulating film including first and second oxide films and a nitride film interposed between the first and second oxide films on a substrate surface, and a gate electrode having a salicide structure is formed on the insulating film. Lose, And the insulating film is also included in a region other than the channel region immediately below the gate electrode of the memory cell array. The method of claim 16, And the insulating film is left at a location other than the channel region and the formation region of the conductive region of the memory cell array. The method of claim 17, And the insulating film is left at a location other than the channel region and the formation region of the conductive region of the memory cell array. The method of claim 15, And the insulating film is left between at least the conductive region of the substrate surface of the memory cell array. The method of claim 16, And the insulating film is left between at least the conductive region of the substrate surface of the memory cell array. The method of claim 15, And wherein the remaining insulating film includes at least the first oxide film and the nitride film among three stacked films. The method of claim 16, And wherein the remaining insulating film includes at least the first oxide film and the nitride film among three stacked films. The method of claim 17, And wherein the remaining insulating film includes at least the first oxide film and the nitride film among three stacked films.