JP2002289792A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a fine transistor wherein not only a vicinity region of a source-drain diffusion layer but also entire source-drain region are formed with a high concentration, and obtaining an ohmic characteristic of a contact to a gate electrode of a first layer. SOLUTION: The method for manufacturing the semiconductor device comprises the steps of, covering a portion 11 where contacts are formed out of a region where a gate electrode 6 formed on a semiconductor substrate by a shield means, forming the source-drain diffusion layer 10 by implanting impurity ions in the semiconductor substrate using the gate electrode as a mask, removing the shielding means, forming an insulation film 12 on the semiconductor substrate, and exposing a contact forming region 14 of the gate electrode and a contact forming region 13 in the source-drain diffusion layer in the insulation film to form the contact.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a step of forming a source / drain diffusion layer and a gate contact.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory, for example, EEPROM (Ele-
ctrically Erasable Programmable Read-Only Memory)
It has been known. In this EEPROM, memory cells are arranged at intersections of row lines and column lines that intersect each other to form a memory cell array. Usually, a MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is used as a memory cell.

[0003] Among EEPROMs, a NAND type EEPROM is known as a system suitable for a large-capacity memory.
The transistor of the peripheral circuit has a general MOSF structure.
It functions similarly to ET, and its stacked gate structure is similar to that of a memory cell transistor.

FIG. 6 and FIG. 7 show a conventional NAND type E.
A method for forming a P-channel transistor in a peripheral circuit of an EPROM will be described.

First, as shown in FIG. 6A, an element region 52 surrounded by an element isolation region 51 is formed on a P-type semiconductor substrate 50 made of silicon.
A mold well region 53 is formed.

Next, a gate insulating film 5 is formed on the well region 53.
4 is formed.

Next, a floating gate electrode material 55 serving as a first-layer gate electrode made of, for example, polysilicon is deposited on the gate insulating film 54. The floating gate electrode material 55 contains a low concentration of N-type impurities in advance, for example, about 4E20 using phosphorus or the like to secure cell reliability.

Further, a floating gate / control gate insulating film 56 is formed thereon, and a control gate electrode material 57 serving as a second-layer gate electrode made of, for example, polysilicon is deposited thereon.

Further, the control gate electrode material 57, the floating gate / control gate insulating film 56, and the floating gate electrode material 55 are etched to form a gate electrode 58.

Next, although not shown, a gate side wall insulating film is formed around the gate electrode 58.

Next, a control gate electrode 57 and a floating gate electrode are formed at a desired location on the element isolation region 51 distant from the element region 52 by using RIE (Reactive Ion Etching) or the like to form a gate contact. The control gate inter-gate insulating film 56 is peeled off to form a gate contact formation region 59.
To expose.

Next, as shown in FIG. 6B, ion implantation of a P-type impurity such as boron or BF ₂ for forming a diffusion layer is performed as shown by an arrow in the figure, and the gate electrode is formed. A source / drain diffusion layer 60 is formed in the well 53 using the mask 58 and the gate sidewall insulating film as a mask. Here, ions are implanted at a P-type impurity concentration of the source / drain diffusion layer 60 in the order of 10 18 per unit cubic cm. Here, P-type impurities are implanted into the entire element region 52 and the gate portion.

Next, as shown in FIG. 7, an interlayer insulating film 61 made of a silicon oxide film or the like is deposited on the semiconductor substrate 50.

Next, a source / drain contact hole 62 for contacting the source / drain diffusion layer 60 is formed by exposing a source / drain contact formation region 63 which is a part of the source / drain diffusion layer 60. I do. This source / drain contact hole 62
Simultaneously with the formation, the contact hole 6 for the gate contact
4 is formed by exposing a part of the gate contact portion 65 in the gate contact formation region 59.

Next, in order to form a contact with the diffusion layer, a P-type impurity concentration immediately below the contact hole is required to be on the order of 10 to the 20th power per unit cubic cm in order to obtain a good low resistance. Additional ion implantation is performed on the portion.

Here, the inside of the interlayer insulating film 61 is shown in perspective.

Next, a metal such as aluminum or tungsten or a low-resistance semiconductor is buried in the source / drain contact hole 62 and the gate contact contact hole 64 to form a source / drain contact 62 and a gate contact 64, respectively. .

After these contacts 62 and 64 are formed, a metal wiring or the like is formed on the interlayer insulating film 61 so that a source / drain wiring layer (not shown) connected to the source / drain contact 62 and a gate are formed. A gate wiring (not shown) connected to the contact 64 is formed.

[0019]

The following problems arise in the conventional method of manufacturing a semiconductor device as described above.

P-type impurities ion-implanted for the source / drain diffusion layers of the P-channel transistor are implanted in the exposed gate electrode contact formation region. Here, if the concentration of the implanted P-type impurity is on the order of 10 18, the effect is not remarkable, but for the purpose of reducing the number of steps, the order of 10 20 on the order required for source / drain contacts. When the ion implantation is performed, the N-type impurity previously doped is canceled out, depleted, and electrical contact cannot be obtained. As a result, an ohmic contact cannot be obtained. I will.

FIG. 8 shows current-voltage characteristics in the case of an ohmic contact. The horizontal axis is voltage (V),
The vertical axis corresponds to the current (I). FIG. 8A shows current-voltage characteristics in the case of ohmic contact characteristics. In this case, the current increases linearly as the voltage increases. In FIG. 8B, the non-ohmic contact
The current-voltage characteristics in the case of (not ohmic) are shown. In this case, the current changes irregularly due to the increase in the voltage. Such characteristics make the contact unsuitable.

In the step of forming the source / drain diffusion layers while exposing the lower gate (floating gate) electrode material, the P-type impurity is added to the lower gate (floating gate) electrode material controlled to have a relatively low concentration. Diffusion may cause problems such as depletion of the gate electrode and deterioration of transistor characteristics.

An object of the present invention is to solve the above-mentioned problems of the prior art.

In particular, an object of the present invention is to form the source / drain diffusion layer not only near the source / drain contact but also at a high concentration over the whole and to improve the ohmic characteristics of the contact to the first layer gate electrode. An object of the present invention is to provide a method for manufacturing a semiconductor device having the obtained fine transistor.

[0025]

In order to achieve the above object, the present invention is characterized in that a gate electrode is formed on a semiconductor substrate, and a portion of the gate electrode where a contact is formed is shielded by a shielding means. Using the gate electrode as a mask, ion-implanting impurities into the semiconductor substrate to form source / drain diffusion layers, removing the shielding means, and insulating the semiconductor substrate. Forming a film; exposing a contact formation region of the gate electrode and a contact formation region in the source / drain diffusion layer in the insulating film;
Forming a contact in a contact formation region in a drain diffusion layer.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, the drawings include portions having different dimensional relationships and ratios.

(First Embodiment) A method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

Here, a method of manufacturing a P-channel transistor in a peripheral circuit of a NAND type EEPROM will be described. First, as shown in FIG.
An element region 3 surrounded by an element isolation region 2 is formed on a type semiconductor substrate 1, and an N-type well region 4 is formed in the element region 3. STI (Shallow TrenchIso)
lation), but LOCOS (Local Oxidation
Other element isolation methods such as Silicon of Silicon) are also applicable.

Next, a gate insulating film 5 is formed on the well region 4. If necessary, channel ion implantation for implanting a low-concentration P-type impurity is performed in the vicinity of the surface of the semiconductor substrate below the region where the gate electrode is to be formed for controlling the threshold value of the transistor.

Next, a floating gate electrode material 6 serving as a first layer gate electrode made of, for example, polysilicon is deposited on the gate insulating film 5. This floating gate electrode material 6 is N
The low-concentration impurities of the mold are contained at a low concentration, for example, about 4E20, using phosphorus or the like to secure cell reliability.

Further, a floating gate / control gate insulating film 7 made of, for example, an ONO film is formed thereon, and a control gate electrode material 8 to be a second-layer gate electrode made of, for example, polysilicon is deposited thereon.

Further, a gate mask material (not shown) serving as a mask at the time of gate etching is deposited. Subsequently, the gate is patterned by photolithography, and the gate mask material is etched. Subsequently, the control gate electrode material 8, the floating gate / control gate insulating film 7, and the floating gate electrode material 6 are etched in a self-aligned manner with respect to the gate mask material to form the gate electrode 9. The gate width is about 0.2 μm and the height is about 0.6 μm.

Next, although not shown, post-oxidation may be performed to recover damage during gate processing, and a post-oxide film may be formed around the gate electrode 9 having a laminated structure.

Next, although not shown, a gate sidewall insulating film is formed around the gate electrode 9.

Next, while the floating gate electrode 6 is covered with the control gate electrode 8, boron or B for forming a diffusion layer is formed.
Ion implantation of a P-type impurity such as F ₂ is performed as shown by the arrow in the figure, and a source / drain diffusion layer 10 is formed in the well 4 using the gate electrode 9 and the gate sidewall insulating film as a mask. Here, P of the source / drain diffusion layer 10
The mold impurity concentration is formed on the order of 10 to the power of 20 per cubic cm.

Next, as shown in FIG. 1B, a control gate electrode is formed at a desired position on the element isolation region 2 distant from the element region 3 by using RIE or the like to form a gate contact. 8 and insulating film 7 between floating gate and control gate
Is removed to expose the gate contact formation region 11. Here, the size of the contact formation region 11 where the floating gate electrode 6 is exposed is, for example, about 0.5 μm
It is about. The size of this contact region is formed in consideration of the allowance for the formation of the contact and the removal of the control gate electrode 8 and the insulating film 7 between the floating gate and the control gate.

Next, as shown in FIG. 2, an interlayer insulating film 12 made of a silicon oxide film or the like is deposited on the semiconductor substrate 1.

Next, a source / drain contact hole 13 for making contact with the source / drain diffusion layer 10 is formed by exposing a source / drain contact formation region which is a part of the source / drain diffusion layer 10. . At the same time as the formation of the source / drain contact holes 13, the gate contact contact holes 14 are formed by exposing a part of the gate contact formation region 11. The size of each contact hole is, for example, about 0.18 μm.

Here, the inside of the interlayer insulating film 12 is seen through.

Next, a metal such as aluminum or tungsten or a low-resistance semiconductor is buried in the source / drain contact hole 13 and the gate contact contact hole 14 to form a source / drain contact 13 and a gate contact 14, respectively. .

After these contacts 13 and 14 are formed, a metal wiring or the like is formed on the interlayer insulating film 12 so that a source / drain wiring layer (not shown) connected to the source / drain contact 13 and a gate are formed. A gate wiring (not shown) connected to the contact 14 is formed.

The contact resistance can be reduced by forming a plurality of contacts on each of the source / drain diffusion layer 10 and the floating gate electrode 6.

The step of exposing a region where a contact electrode is to be formed to the first-layer gate electrode provided by peeling off a part of the second-layer gate electrode, which constitutes the peripheral transistor, comprises a source / drain diffusion layer. This is performed after the step of introducing impurities for formation.

In this case, when implanting P-type impurity ions, the first
Since the second-layer gate electrode is covered with the second-layer gate electrode, a contact failure caused by insufficient concentration right below the gate contact and a depletion of the gate electrode due to diffusion of P-type impurities do not occur. As described above, in the step before the formation of the gate contact, the second-layer gate electrode is used as a mask material when forming the source / drain diffusion layers.

The material of the second polysilicon electrode is not necessarily required to be polysilicon, but may be formed of a metal material such as tungsten silicide, which is a low-resistance conductive material.

Further, another conductive layer or insulating layer may be formed on the second polysilicon electrode.

By manufacturing as described above, a source / drain diffusion layer can be formed without implanting a P-type impurity into the first-layer gate electrode. And the first layer gate electrode can be prevented from being depleted. Thus, the P-channel MO
In the S transistor, the ohmic gate contact can be formed in the same step as the diffusion layer contact.

FIG. 3 shows a cross-sectional structure of an N-channel transistor and a P-channel transistor showing the structure around the gate electrode of the semiconductor device shown in FIG. 2 in more detail. As shown on the right side of FIG. 3, in the P-channel transistor, a gate side wall insulating film 15 is formed around the gate electrode 9. A source / drain diffusion layer 10 is formed from below the gate sidewall insulating film 15 in the semiconductor substrate 1 around the gate sidewall insulating film 15. On the control gate electrode 8, a mask layer 16 made of an insulator such as a silicon nitride film is formed.

As shown on the left side of FIG. 3, in the N-channel transistor, a gate sidewall insulating film 15 is formed around the gate electrode 9 as in the P-channel transistor. A low-concentration N-type diffusion layer 17 is formed in the semiconductor substrate 1 under the gate sidewall insulating film 15, and a high-concentration N-type diffusion layer 18 is formed in the surrounding semiconductor substrate 1.

In the N-channel transistor, a low-concentration N-type impurity region is formed below the gate side wall insulating film 15 and a high-concentration N-type impurity region is formed outside the region.
It has a D (Lightly Doped Drain) structure.

Here, FIG. 3 shows a P-channel transistor,
Each of the N-channel transistors corresponds to a cross-sectional view taken along line “AB” in FIG. 4 which is a plan view.

In an N-channel transistor, an N-type impurity is generally doped in a gate electrode in advance, and even if an N-type impurity is implanted into a gate contact region in an impurity implantation step for forming a source / drain diffusion layer. Since the ohmic property is not impaired, it may be formed by changing only the conductivity type in the same manner as in the P-channel transistor as in this embodiment, or may be formed as in the prior art.

According to the manufacturing method of the present embodiment, the contact region of the lower first-layer gate electrode does not contain the high-concentration P-type impurities of the source / drain diffusion layers, but contains the N-type low-concentration impurities. Being diffused, an ohmic contact is realized at the gate contact.
In the upper-layer second-layer gate electrode, when a mask layer or the like is not formed thereon, high-concentration P-type impurities in the source / drain diffusion layers are diffused.

The second-layer gate electrode may have a conductive layer or an insulating layer formed thereon, and may be formed of metal silicide or the like instead of polysilicon. No high concentration P-type impurity is introduced.

When the gate contact and the source / drain diffusion layer contact are formed in the same step, an ohmic contact can be formed for both the gate and the diffusion layer contact.

As described above, according to the present embodiment, the source / drain diffusion layer is formed not only near the source / drain contacts but also at a high concentration over the whole, and the contact between the source / drain diffusion layers and the first layer gate electrode is formed. A fine transistor having ohmic characteristics can be formed.

(Second Embodiment) FIG.
This will be described with reference to FIG. As in the first embodiment, an element region 3 surrounded by an element isolation region 2 is formed on a P-type semiconductor substrate 1 made of silicon, and an N-type well region 4 is formed in the element region 3.

Next, a floating gate electrode material 6 serving as a first layer gate electrode made of, for example, polysilicon is deposited on the gate insulating film 5. This floating gate electrode material 6 is N
Low concentration impurities.

Further, an insulating film 7 between the floating gate and the control gate is formed thereon, and a control gate electrode material 8 serving as a second-layer gate electrode made of, for example, polysilicon is deposited thereon.

Further, a gate mask material (not shown) serving as a mask at the time of gate etching is deposited. Subsequently, the gate is patterned by photolithography, and the gate mask material is etched. Subsequently, the control gate electrode material 8, eg, ON, is self-aligned with the gate mask material.
The gate electrode 9 is formed by etching the floating-gate / control-gate insulating film 7 made of an O film and the floating gate electrode material 6. The gate width is about 0.2 μm and the height is about 0.1 μm.
It is about 6 μm.

Next, although not shown, a gate sidewall insulating film is formed around the gate electrode 9.

Next, as shown in FIG. 5, a control gate electrode 8 and a floating gate are formed at a desired place on the element isolation region 2 distant from the element region 3 by using RIE or the like to form a gate contact. The gate / control gate insulating film 7 is peeled off to expose the gate contact formation region 11.

Here, the size of the gate contact formation region 11 where the floating gate electrode 6 is exposed is, for example, about 0.5 μm on the left and right in the figure. The size of this contact region is formed in consideration of the allowance for the formation of the contact and the removal of the control gate electrode 8 and the insulating film 7 between the floating gate and the control gate.

Next, the gate contact formation region 11 is covered with a resist 20. The resist 20 used here is usually a resist used as a mask when performing ion implantation. However, the gate contact formation region 11
Therefore, the width and the length of the gate contact formation region 11 must be larger than the gate contact formation region 11 while securing a margin for mask alignment. The resist used here has a height of about 1 μm.
Formed in the degree.

Next, while the gate / contact formation region 11 of the floating gate electrode 6 is covered with the resist, ion implantation of a P-type impurity such as boron or BF ₂ for forming a diffusion layer is performed in the figure. The operation is performed as indicated by arrows, and the source / drain diffusion layers 10 are formed in the wells using the gate electrode 9 and the gate side wall insulating film as a mask.

Next, the resist 20 is removed by wet etching or the like. Subsequent steps are the same as those of the first embodiment shown in FIGS.

The contact resistance can be reduced by forming a plurality of contacts on each of the source / drain diffusion layer 10 and the floating gate electrode 6.

The step of exposing a region where a contact is to be formed to the first-layer gate electrode provided by peeling off a part of the second-layer gate electrode, which constitutes the peripheral transistor, comprises a source / drain diffusion layer. The same effect as in the first embodiment can be obtained by using a resist even before the impurity introduction step for formation.

Each embodiment can be implemented in combination.

In each of the above embodiments, an example is shown in which the present invention is applied to a P-channel transistor. Then, the present invention can be applied to, for example, an N-channel transistor having a gate electrode into which boron as a P-type impurity is implanted. Further, the present invention can be applied to a P-channel transistor in the same semiconductor device into which the N-type impurity such as phosphorus is implanted as described above.

Each embodiment is directed to a NAND type EEPROM.
The above description has been made by taking the semiconductor memory as an example.
The present invention can be similarly applied to an iNOR type semiconductor memory and a semiconductor device having a transistor requiring high integration.

[0072]

According to the present invention, the source / drain diffusion layer is formed not only in the vicinity of the source / drain contact but also in a high concentration over the whole, and the ohmic characteristics of the contact to the first-layer gate electrode are improved. A semiconductor device having the obtained fine transistor can be manufactured.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view showing one step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 2 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a plan view showing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a sectional view showing one step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6A is a cross-sectional view illustrating one step of a conventional method of manufacturing a semiconductor device, and FIG. 6B is a cross-sectional view illustrating one step of a conventional method of manufacturing a semiconductor device.

FIG. 7 is a sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 8A is a graph showing the current and current of an ohmic contact.
It is a figure which shows a voltage characteristic, and (B) is a figure which shows the current / voltage characteristic of a non-ohmic contact.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Element region 4 Well 5 Gate insulating film 6 Floating gate electrode (material) 7 Floating gate-control gate insulating film 8 Control electrode (material) 9 Gate electrode 10 Source / drain diffusion layer 11 Gate contact Forming region 12 Interlayer insulating film 13 Source / drain contact (hole) 14 Gate contact (hole) 15 Gate electrode sidewall insulating film 16 Gate mask material 17 Low concentration N-type impurity region 18 High concentration N-type impurity region 20 Resist

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme Court ゛ (Reference) H01L 29/788 29/792 (72) Inventor Norihisa Arai 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba My F-term (reference) in Kuroelectronics Co., Ltd. BD21 BD34 BD35 BD37 BD45 BH09 BH21

Claims (4)

[Claims] A step of forming a gate electrode on a semiconductor substrate; a step of covering a portion of the gate electrode where a contact is to be formed with shielding means; and an impurity in the semiconductor substrate using the gate electrode as a mask. Forming a source / drain diffusion layer by implanting ions; removing the shielding means; forming an insulating film on the semiconductor substrate; and forming a contact of the gate electrode in the insulating film. Exposing a region and a contact formation region in the source / drain diffusion layer; and forming a contact in the exposed contact formation region of the gate electrode and the contact formation region in the source / drain diffusion layer. A method for manufacturing a semiconductor device. 2. In the step of forming the gate electrode,
2. The method according to claim 1, wherein in the step of forming a first-layer gate electrode and forming the shielding means, the shielding means is one of a second-layer gate electrode and a resist. 3. The step of forming the gate electrode,
3. The method according to claim 1, wherein the gate electrode is doped with a first conductivity type, and the step of forming the source / drain diffusion layer includes doping the source / drain diffusion layer with a second conductivity type. The manufacturing method of the semiconductor device described in the above. 4. The step of forming the contact,
The impurity concentration of the source / drain diffusion layer to which the contact is connected depends on the source / drain to which the contact is not connected.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity concentration is equal to the impurity concentration of the drain diffusion layer.