KR100464382B1 - Isolation method for manufacturing semiconductor device - Google Patents

Isolation method for manufacturing semiconductor device Download PDF

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KR100464382B1
KR100464382B1 KR1019970019551A KR19970019551A KR100464382B1 KR 100464382 B1 KR100464382 B1 KR 100464382B1 KR 1019970019551 A KR1019970019551 A KR 1019970019551A KR 19970019551 A KR19970019551 A KR 19970019551A KR 100464382 B1 KR100464382 B1 KR 100464382B1
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semiconductor substrate
ion implantation
oxide film
impurity ions
conductivity type
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KR19980083995A (en
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김세표
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

PURPOSE: An isolation method of a semiconductor device is provided to reduce a junction leakage and improve a refresh characteristic of a DRAM(dynamic random access memory) by distributing high density impurity ions to a region far away from an interface between a field oxide layer and a source/drain region. CONSTITUTION: A pad oxide layer(2) is formed on a semiconductor substrate(200) of the first conductivity type. An oxide preventing layer pattern for defining an inactive region is formed on the pad oxide layer. The semiconductor substrate of the first conductivity type in the inactive region is oxidized to form a field oxide layer(6). The oxide preventing layer pattern is eliminated. Impurity ions of the first conductivity type are firstly implanted into the front surface of the semiconductor substrate at an angle of 10-60 degrees with respect to a virtual line vertical to the semiconductor substrate. Impurity ions of the first conductivity type are secondly implanted into the semiconductor substrate at an angle of 10-60 degrees with respect to the virtual line in a direction opposite to the first ion implantation direction.

Description

반도체 장치의 소자 분리 방법{Isolation method for manufacturing semiconductor device}Isolation method for manufacturing semiconductor device

본 발명은 반도체 장치의 소자 분리 방법에 관한 것으로, 특히 실리콘의 국부산화(LOCal Oxidation of Silicon; 이하 LOCOS 라 한다)법에 의하여 필드산화막을 형성한 후 불순물 이온을 주입하여 소자분리를 강화하는 반도체 장치의 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device. In particular, a semiconductor device for enhancing device isolation by implanting impurity ions after forming a field oxide film by a LOCal Oxidation of Silicon (LOCOS) method. It relates to a device isolation method of.

DRAM 소자는 스위치의 역할을 하는 트랜지스터를 이용하여 커패시터에 전하를 축적하거나 커패시터로부터 전하를 방출하여 그 기억상태를 표시하는 소자이다. DRAM을 사용하는 시스템에서는 커패시터의 스토리지 전극과 플레이트 전극사이의 유전막의 불완전성에 따른 전하의 누설(leakage) 및 소오스/ 드레인 영역과 반도체 기판 사이에서의 접합(junction) 형성 등에 의한 전하의 누설때문에, DRAM에 저장된 데이터를 계속 유지하기 위하여 반드시 일정한 주기마다 DRAM을 리프레쉬(refresh)시켜야 한다. A DRAM device uses a transistor serving as a switch to accumulate charge in a capacitor or to discharge charge from a capacitor to display a memory state thereof. In a system using a DRAM, the DRAM is leaked due to the leakage of charge due to the incompleteness of the dielectric film between the storage electrode and the plate electrode of the capacitor and the formation of a junction between the source / drain region and the semiconductor substrate. The DRAM must be refreshed at regular intervals to maintain the data stored in the memory.

그런데, DRAM을 포함한 반도체 소자의 집적도가 증가함에 따라 인접한 기본 셀 사이의 전기적 절연성을 확실히 보장하여야 할 필요가 있다. 이러한 필요성을 만족시키기 위하여, 반도체기판 상에 반도체 소자를 형성하기 전에 반도체기판 상에 반도체 소자가 형성되는 활성영역과 반도체 소자가 형성되지 않는 비활성영역을 구분한 후, 비활성영역에 소자분리용 필드산화막을 형성한다.However, as the degree of integration of semiconductor devices including DRAMs increases, there is a need to ensure electrical insulation between adjacent basic cells. In order to satisfy this necessity, before forming a semiconductor device on a semiconductor substrate, an active region where a semiconductor device is formed on a semiconductor substrate and an inactive region where a semiconductor device is not formed are divided, and then a field oxide film for device isolation in the inactive region. To form.

예를 들면, LOCOS법에 의하여 필드산화막을 형성한 후 그 아래에 소오스/ 드레인 영역의 도핑 타잎과 반대되는 불순물 이온을 주입하여 소자분리를 강화하는 방식이 대표적이다. 그러나, 이러한 소자분리 강화를 위한 이온주입 공정은, 도핑된 고농도의 불순물 이온과 커패시터와 접속된 소오스/ 드레인 영역과의 사이에 접합을 형성함과 아울러 접합의 공핍층내에 실리콘 결정결함을 유발시킴으로써 커패시터에 축적된 전하를 소실시키는 누설현상을 유발시켜 DRAM의 리프레쉬 특성을 저하시키는 공정으로 잘 알려져 있다. For example, a method of strengthening device isolation by forming a field oxide film by the LOCOS method and then implanting impurity ions opposite to the doping type of the source / drain regions under the LOCOS method. However, the ion implantation process for strengthening device isolation enhances the capacitor by forming a junction between the doped high concentration of impurity ions and the source / drain region connected to the capacitor and inducing a silicon crystal defect in the depletion layer of the junction. It is well known as a process of reducing the refresh characteristics of a DRAM by causing a leakage phenomenon that loses the charge accumulated in the memory.

도 1은 이러한 소자분리를 강화하기 위한 이온주입 공정에 의하여 DRAM의 리프레쉬 특성이 저하되는 현상을 설명하기 위한 단면도이다.FIG. 1 is a cross-sectional view illustrating a phenomenon in which a refresh characteristic of a DRAM is degraded by an ion implantation process for enhancing device isolation.

도면부호 100은 반도체 기판을, 1은 패드산화막을, 3은 소자분리를 위한 필드산화막을, 5는 트랜지스터의 소오스/ 드레인 영역을, 7은 소자분리를 강화하기 위하여 이온주입된 불순물 이온의 투영비정(projected range) Rp 의 궤적을 나타낸다.Reference numeral 100 is a semiconductor substrate, 1 is a pad oxide film, 3 is a field oxide film for device isolation, 5 is a source / drain region of the transistor, 7 is projection projection of ion implanted impurity ions to enhance device isolation. (projected range) represents the trajectory of R p .

반도체 기판에 불순물 이온을 주입하였을 때 반도체 기판의 표면으로부터 특정한 침투깊이를 중심으로 불순물 이온의 농도는 가우스 분포를 이루는데, 이 가우스 분포의 꼭지점을 반도체 기판의 표면으로부터의 평균적인 침투깊이를 나타내는 투영비정 Rp라 한다.When impurity ions are implanted into a semiconductor substrate, the concentration of impurity ions is a Gaussian distribution centering on a specific penetration depth from the surface of the semiconductor substrate, and a projection representing the average penetration depth from the surface of the semiconductor substrate at the vertex of the Gaussian distribution. It is referred to non-integer R p.

기존의 방식에 따라 LOCOS법에 의하여 소자분리를 위한 필드산화막(3)을 형성한 후 반도체 기판(100)에 7˚정도 경사지게 소자분리 강화를 위한 불순물을 이온주입하면, 도 1에 나타난 것처럼 불순물 이온의 투영비정(projected range) Rp의 궤적(7)이 필드산화막(3)과 소오스/ 드레인 영역(5)과의 경계부분에 가깝게 위치한다. 이는 필드산화막(3)의 하부에 고농도로 주입된 불순물 이온이 소오스/ 드레인 영역(5)에 가깝게 위치하는 것을 의미한다. 그런데, 이 필드산화막(3)과 소오스/ 드레인 영역(5)과의 경계부분은, 필드산화막(3) 형성시 실리콘의 단위격자의 부피와 실리콘 산화물의 단위격자의 부피 차이에서 비롯되는 부피팽창으로 인한 잔류 스트레스(stress)와 불순물 이온주입시 발생하는 실리콘의 격자결함으로 인하여 커패시터에 축적된 전하가 쉽게 누설되는 취약한 부분이다. 따라서, 기존의 소자분리를 강화하기 위한 이온주입 공정은 접합누설(junction leakage)을 많이 발생시켜 DRAM의 리프레쉬 특성을 저하시키는 문제점이 있다.After forming the field oxide film 3 for device isolation by the LOCOS method according to the conventional method, and implanting impurities for enhancing device isolation at an inclination of about 7 ° to the semiconductor substrate 100, impurity ions as shown in FIG. The trajectory 7 of the projected range R p of is located close to the boundary between the field oxide film 3 and the source / drain region 5. This means that impurity ions implanted at a high concentration under the field oxide film 3 are located close to the source / drain region 5. However, the boundary between the field oxide film 3 and the source / drain region 5 is a volume expansion resulting from the difference in the volume of the unit lattice of silicon and the unit lattice of silicon oxide when the field oxide film 3 is formed. Due to the residual stress caused by the lattice defect of the silicon generated during implantation and impurity ions, the charge accumulated in the capacitor easily leaks. Accordingly, the ion implantation process for reinforcing device isolation has a problem of causing a lot of junction leakage and degrading the refresh characteristics of the DRAM.

따라서, 본 발명이 이루고자 하는 기술적 과제는 필드산화막과 소오스/ 드레인 사이의 누설전류에 의한 리프레쉬 특성의 저하를 방지할 수 있는 반도체 장치의 소자 분리 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device capable of preventing a decrease in refresh characteristics due to leakage current between a field oxide film and a source / drain.

상기 기술적 과제를 달성하기 위하여 본 발명은, (a) 제1도전형의 반도체기판 상에 패드산화막을 형성하는 단계; (b) 상기 패드산화막 상에 비활성영역을 한정하는 산화방지막 패턴을 형성하는 단계; (c) 상기 비활성영역의 제1도전형의 반도체기판을 산화시켜 필드산화막을 형성하는 단계; (d) 상기 산화방지막 패턴을 제거하는 단계; 및 (e) 상기 제1도전형의 반도체기판의 전면에, 제1도전형의 불순물 이온을 반도체기판에 수직한 가상선에 대하여 일정한 각도로 경사지게 이온주입하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법을 제공한다.The present invention to achieve the above technical problem, (a) forming a pad oxide film on a semiconductor substrate of the first conductivity type; (b) forming an anti-oxidation film pattern defining an inactive region on the pad oxide film; (c) oxidizing the first conductive semiconductor substrate in the inactive region to form a field oxide film; (d) removing the antioxidant pattern; And (e) implanting the first conductive impurity ions at an angle to the front surface of the first conductive semiconductor substrate at an angle with respect to an imaginary line perpendicular to the semiconductor substrate. It provides a method of device separation.

상기 (e)단계의 일정한 각도는 10°∼ 60°인 것이 바람직하다.The constant angle of step (e) is preferably 10 ° to 60 °.

한편, 상기 (e)단계 이후, 상기 가상선에 대하여 상기 (e)단계의 이온주입방향과 반대방향에서 일정한 각도로 경사지게 제1도전형의 불순물을 이온주입하는 단계를 더 포함할 수 있는 데, 이때의 일정한 각도도 10°∼ 60°인 것이 바람직하며, 상기 가상선에 대하여 상기 (e)단계에서의 이온주입방향과 대칭되도록 하는 것이 더욱 바람직하다.On the other hand, after the step (e), it may further comprise the step of ion implantation of impurities of the first conductivity type inclined at a predetermined angle in the direction opposite to the ion implantation direction of the step (e) with respect to the imaginary line, The constant angle at this time is also preferably 10 ° to 60 °, more preferably symmetrical with the ion implantation direction in step (e) with respect to the virtual line.

본 발명에 따른 반도체 장치의 소자 분리 방법은 접합누설(junction leakage) 발생에 매우 취약한 부분인 필드산화막의 양 가장자리(edge)와 소오스/ 드레인 영역과의 경계부분으로부터 고농도의 불순물 이온을 멀리 분포시킴으로써, 접합누설의 발생을 감소시켜 DRAM의 리프레쉬 특성을 향상시킨다.The device isolation method of the semiconductor device according to the present invention distributes a high concentration of impurity ions away from a boundary between a field edge and a source / drain region of a field oxide film, which is a very vulnerable to junction leakage. Reduce the occurrence of junction leakage to improve the refresh characteristics of the DRAM.

이하, 본 발명의 바람직한 실시예에 대하여 첨부한 도 2 내지 도 4를 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

도 2는 반도체 기판 상에 패드산화막(2)과 실리콘질화막 패턴(4)을 형성하는 단계를 설명하기 위한 단면도이다.2 is a cross-sectional view for explaining a step of forming a pad oxide film 2 and a silicon nitride film pattern 4 on a semiconductor substrate.

구체적으로 설명하면, 제1도전형의 반도체 기판(200), 예를 들면 P형 실리콘기판 상에 100Å ∼ 200Å 정도의 패드산화막(2)을 형성하고, 그위에 산화방지막, 예를 들면 실리콘질화막을 1000Å ∼ 2000 Å 정도의 두께로 형성한다. 이어서, 상기 실리콘질화막을 패터닝하여 비활성영역을 한정하는 실리콘질화막 패턴(4)을 형성한다. 이때, 상기 실리콘질화막 패턴(4)에 의하여 노출되는 부분은 비활성영역이 되는 부분이며, 상기 실리콘질화막 패턴(4)에 의하여 노출되지 않는 영역은 기본 셀이 형성되는 활성영역이 되는 부분이다. In detail, a pad oxide film 2 of about 100 mW to 200 mW is formed on the first conductive semiconductor substrate 200, for example, a P-type silicon substrate, and an antioxidant film, for example, a silicon nitride film is formed thereon. It is formed to a thickness of about 1000 kPa to 2000 kPa. Subsequently, the silicon nitride film is patterned to form a silicon nitride film pattern 4 defining an inactive region. In this case, a portion exposed by the silicon nitride layer pattern 4 is an inactive region, and a region not exposed by the silicon nitride layer pattern 4 is a portion which becomes an active region in which a basic cell is formed.

도 3은 소자분리를 위한 필드산화막(6)을 형성한 후, 소자분리를 강화하기 위한 불순물 이온을 주입하는 단계를 설명하기 위한 단면도이다.3 is a cross-sectional view for explaining a step of implanting impurity ions for enhancing device isolation after forming the field oxide film 6 for device isolation.

구체적으로 설명하면, 상기 실리콘질화막 패턴(4)이 형성된 반도체 기판(200)을 1050℃ 정도의 온도에서 열산화시켜 필드산화막(6)을 형성한다. 이때, 실리콘질화막 패턴(4)의 하부에 위치하는 기판은 산화되지 않고 후공정에서 활성영역이 된다. Specifically, the field oxide film 6 is formed by thermally oxidizing the semiconductor substrate 200 on which the silicon nitride film pattern 4 is formed at a temperature of about 1050 ° C. At this time, the substrate positioned below the silicon nitride film pattern 4 is not oxidized and becomes an active region in a later step.

이어서, 소자분리를 강화하기 위하여 상기 필드산화막(6)이 형성된 반도체 기판(200)의 전면에, 상기 반도체 기판(200)의 도전형과 같은 도전형의 불순물, 예를 들면 붕소(boron) 이온을 1차로 이온주입한다. 이때, 상기 1차 이온주입의 방향은 상기 반도체 기판(200)에 수직한 가상선에 대하여 10°∼ 60°의 각도를 이루도록 하고, 붕소이온의 도우즈는 5.0×1011 ∼ 1.0×1013/cm3 정도가 되도록 하며, 붕소이온의 이온주입 에너지는 포물선 형태를 보이는 투영비정(projected range) Rp 의 궤적의 꼭지점이 필드산화막(6)의 바로 아래에 형성될 수 있도록 조절한다. 계속하여, 상기 가상선에 대하여 상기 1차 이온주입 방향과 대칭되는 방향에서 붕소 이온을 2차 이온주입하는 데, 이때의 붕소이온의 도우즈 및 이온주입 에너지는 1차 이온주입과 동일하게 한다. 이로써, 반도체 장치의 소자분리가 완성된다.Subsequently, in order to enhance device isolation, an impurity of a conductivity type, such as boron ions, such as a conductivity type of the semiconductor substrate 200 is deposited on the entire surface of the semiconductor substrate 200 on which the field oxide film 6 is formed. Primary ion implantation. At this time, the direction of the primary ion implantation is to form an angle of 10 ° to 60 ° with respect to the imaginary line perpendicular to the semiconductor substrate 200, the dose of boron ion is 5.0 × 10 11 ~ 1.0 × 10 13 / cm, and such that the third degree, the ion implantation of boron ion energy is adjusted to be a vertex of the trajectory of the parabola shape of the visible non projection (projected range) p R formed immediately below the field oxide film (6). Subsequently, the secondary ion is implanted with boron ions in a direction symmetrical with the primary ion implantation direction with respect to the imaginary line, wherein the dose and ion implantation energy of boron ions are the same as the primary ion implantation. This completes device isolation of the semiconductor device.

도 4는 상기 소자분리를 강화하기 위한 불순물 이온 주입 공정에 의하여 도핑된 불순물 이온의 반도체 기판내에서의 분포형태를 투영비정(projected range) Rp 의 궤적(8)으로 나타낸 단면도이다.FIG. 4 is a cross-sectional view showing the distribution form 8 of the projected range R p in the semiconductor substrate of the doped impurity ions doped by the impurity ion implantation process for enhancing the device isolation.

구체적으로 설명하면, 상기한 바와 같이 10°∼ 60°정도의 경사를 주어 불순물 이온을 주입하면, 도 1에서 설명한 것과 달리 투영비정(projected range) Rp 의 궤적(8)이 필드산화막(6)의 하부에서는 포물선의 형태로 좁게 중앙부분에 치우쳐 형성되고, 활성영역에서는 직선의 형태로 소오스/ 드레인 영역(10)으로부터 멀리 떨어져 깊게 형성된다. 이에 따라, 접합누설(junction leakage) 발생에 매우 취약한 부분인 필드산화막(6)과 소오스/ 드레인 영역과의 경계부분으로부터 고농도의 불순물 이온이 멀리 분포한다. 따라서, 본 발명에 따른 소자 분리 방법은 접합누설(junction leakage) 발생을 감소시킴으로써 DRAM의 리프레쉬 특성을 향상시킨다.Specifically, as described above, when impurity ions are implanted with an inclination of about 10 ° to 60 °, the trace 8 of the projected range R p is different from that described in FIG. 1. In the lower part of the center, the parabolic shape is narrowly formed in the center portion, and in the active region, a straight line is formed far away from the source / drain region 10. As a result, a high concentration of impurity ions are distributed far from the boundary between the field oxide film 6 and the source / drain region, which are very susceptible to junction leakage. Therefore, the device isolation method according to the present invention improves the refresh characteristics of DRAM by reducing the occurrence of junction leakage.

계속하여, 도시하지는 아니 하였지만 활성영역상에 게이트와 소오스/ 드레인 영역과 커패시터를 형성한 후, 각각의 소자를 구동하기 위한 인터콘넥션을 형성하여 DRAM 반도체 장치를 완성한다. Subsequently, although not shown, a gate, a source / drain region, and a capacitor are formed on the active region, and then interconnections for driving respective elements are formed to complete the DRAM semiconductor device.

상기한 바와 같이, 본 발명에 따른 반도체 장치의 소자분리방법은 접합누설(junction leakage) 발생에 매우 취약한 부분인 필드산화막과 소오스/ 드레인 영역과의 경계부분으로부터 고농도의 불순물이온을 멀리 분포시킴으로써, 접합누설의 발생을 감소시켜 DRAM의 리프레쉬 특성을 향상시킨다. 이에 따라, 커패시터로부터 누설된 전하를 보충하기 위한 리프레쉬 주기를 증가시켜도 되므로 DRAM의 전력소모를 감소시키는 장점이 있다. As described above, the device isolation method of the semiconductor device according to the present invention distributes a high concentration of impurity ions away from a boundary portion between a field oxide film and a source / drain region, which are very susceptible to junction leakage. By reducing the occurrence of leakage to improve the refresh characteristics of the DRAM. Accordingly, the refresh period for replenishing the charge leaked from the capacitor may be increased, thereby reducing the power consumption of the DRAM.

이상, 본 발명을 구체적인 실시예를 들어 상세하게 설명하였으나, 본 발명은 이에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다. The present invention has been described in detail with reference to specific embodiments, but the present invention is not limited thereto, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

도 1은 종래의 기술에 의한 반도체 장치의 소자 분리 방법의 문제점을 설명하기 위한 단면도이다. 1 is a cross-sectional view illustrating a problem of a device isolation method of a semiconductor device according to the prior art.

도 2 내지 도 4은 본 발명의 바람직한 실시예에 따른 반도체 장치의 소자 분리 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도들이다.2 to 4 are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with a preferred embodiment of the present invention according to a process sequence.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

2 : 패드산화막 4 : 실리콘질화막 패턴2: pad oxide film 4: silicon nitride film pattern

6 : 필드산화막 8 : 이온주입된 불순물 이온의 투영비 정(projected range) Rp의 궤적 10 : 소오스/ 드레인 영역6 Field oxide film 8 Trajectory of projected range R p of ion implanted impurity ions 10 Source / drain region

200 : 반도체 기판200: semiconductor substrate

Claims (3)

(a) 제1도전형의 반도체기판 상에 패드산화막을 형성하는 단계;(a) forming a pad oxide film on the first conductive semiconductor substrate; (b) 상기 패드산화막 상에 비활성영역을 한정하는 산화방지막 패턴을 형성하는 단계;(b) forming an anti-oxidation film pattern defining an inactive region on the pad oxide film; (c) 상기 비활성영역의 제1도전형의 반도체기판을 산화시켜 필드산화막을 형성하는 단계;(c) oxidizing the first conductive semiconductor substrate in the inactive region to form a field oxide film; (d) 상기 산화방지막 패턴을 제거하는 단계;(d) removing the antioxidant pattern; (e) 상기 제1도전형의 반도체기판의 전면에, 제1도전형의 불순물 이온을 반도체기판에 수직한 가상선에 대하여 10°내지 60°의 각도로 경사지게 제1차 이온주입하는 단계; 및(e) primary ion implantation inclined at an angle of 10 ° to 60 ° with respect to an imaginary line perpendicular to the semiconductor substrate, on the front surface of the first conductive semiconductor substrate; And (f) 상기 가상선에 대하여 상기 제1차 이온주입 방향과 반대방향에서 10°내지 60°의 각도로 경사지게 제1도전형의 불순물을 제2차 이온주입하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.(f) a second ion implantation of impurities of the first conductivity type inclined at an angle of 10 ° to 60 ° in a direction opposite to the primary ion implantation direction with respect to the imaginary line; Method of device separation of devices. 제1항에 있어서,The method of claim 1, 상기 (f)단계의 상기 제2차 이온주입 단계의 불순물 이온의 주입방향은 상기 가상선에 대하여 상기 (e)단계에서의 상기 제1차 이온주입방향과 대칭되도록 하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.Wherein the implantation direction of the impurity ions in the secondary ion implantation step of step (f) is symmetrical with the primary ion implantation direction in step (e) with respect to the imaginary line. Device isolation method. 제2항에 있어서,The method of claim 2, 상기 (e)단계의 상기 제1차 이온주입 단계는 붕소 이온을 5.0×1011 ∼ 1.0×1013/cm3 의 도즈로 이온 주입하고, 상기 제2차 이온주입 단계는 상기 제1차 이온주입단계와 이온, 이온주입 도즈 및 이온주입 에너지를 동일하게 하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.In the first ion implantation step (e), boron ions are implanted with a dose of 5.0 × 10 11 to 1.0 × 10 13 / cm 3 , and the second ion implantation step is the first ion implantation step. A device isolation method for a semiconductor device, characterized in that the steps and the ion, ion implantation dose and ion implantation energy are the same.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432107A (en) * 1992-11-04 1995-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor fabricating method forming channel stopper with diagonally implanted ions
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5554544A (en) * 1995-08-09 1996-09-10 United Microelectronics Corporation Field edge manufacture of a T-gate LDD pocket device
US5624859A (en) * 1995-06-07 1997-04-29 Advanced Micro Devices, Inc. Method for providing device isolation and off-state leakage current for a semiconductor device
KR980012141A (en) * 1996-07-24 1998-04-30 문정환 Semiconductor device and manufacturing method thereof
KR19980048841A (en) * 1996-12-18 1998-09-15 김광호 Device Separation Method of Semiconductor Device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432107A (en) * 1992-11-04 1995-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor fabricating method forming channel stopper with diagonally implanted ions
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5624859A (en) * 1995-06-07 1997-04-29 Advanced Micro Devices, Inc. Method for providing device isolation and off-state leakage current for a semiconductor device
US5554544A (en) * 1995-08-09 1996-09-10 United Microelectronics Corporation Field edge manufacture of a T-gate LDD pocket device
KR980012141A (en) * 1996-07-24 1998-04-30 문정환 Semiconductor device and manufacturing method thereof
KR19980048841A (en) * 1996-12-18 1998-09-15 김광호 Device Separation Method of Semiconductor Device

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