KR900005356B1 - Burid source type dynamic semiconductor memory device - Google Patents

Abstract

The memory device has cells in which the source electrode is buried inside a trench capacitor. The device is prepared by sputterig a BPSG (borophospor silicate glass) thin film (41), etching it to form a first trench (27), forming a predetermined patterm filling a first polysilicon (40) on the inside of the first trench (27), sputtering a second polysilicon (37), forming a pattern of the second trench; sputering a third polysilicon; and implanting As ions of 5 x 1015 cm-2 to form a drain (35) and buried source (33).

Description

Source buried dynamic semiconductor memory device

1 is a conventional dynamic semiconductor memory device.

(a) is a top view which shows the state in which the source is installed.

(b) is sectional drawing which shows the state in which the source was installed.

2 is a cross-sectional view of a dynamic semiconductor memory device using a conventional N-type well.

3 is a plan view of a source buried dynamic semiconductor memory device according to one embodiment of the present invention.

4 is a cross-sectional view taken along the line A-A of FIG.

5 is a cross-sectional view taken along the line B-B in FIG.

6A-6E are longitudinal cross-sectional views showing the fabrication process of the source buried dynamic semiconductor memory device of the present invention.

* Explanation of symbols for main parts of the drawings

1,31 P-type silicon substrate 2: Plate electrode

15,32 P-type epitaxial layer 3: insulating film

18,33 source 26 active region

27: first trench 28: bit line

29 silicon junction 30 second trench

34: gate oxide film 35: drain

36: capacitor oxide film 37: second polycrystalline silicon

38: low temperature oxide film 39: silicon nitride protective film

40: first polysilicon 41: BPSG film

The present invention relates to a source buried dynamic semiconductor memory device having a cell in which a source electrode is embedded in a trench capacitor in a highly integrated dynamic semiconductor.

In general, the memory cell occupies about 605 in the chip area of the memory device. Therefore, minimizing the memory cell area is essential to promote ultra-high integration. In order to meet such demands, the process of converting memory cells due to high integration has mostly used planar type cells up to 256K DRAM. The megabit DRAM has been replaced by a stack type cell due to the limitation of the size reduction of the cell.

However, as the demand in the information industry for maximum capacity, such as 4M DRAM and 16M DRAM, continues to increase, grooves are formed on silicon substrates by forming grooves in silicon substrates by increasing the effective area on a finite plane. Since the new trench structure is newly introduced, the trench cell structure is mostly adopted in the 4M DRAM stage, and this trend is expected to increase as the integration of 16M DRAM increases.

The unit of the dynamic memory cell is composed of one transistor and one capacitor. In the case of 4M DRAM, the cell size is about 10 μm ^2, and in the ultra-high density stage of about 16M DRAM, the cell size is about 5 μm ² . To achieve this extreme reduction in cell size for next-generation memory devices, extreme trenches such as forming deep trenches of about 8 μm in narrow aperture widths (1-2 μm ² ) or double-separating polysilicon films in narrow trenches are required. Skills are needed. In particular, the severe electrical interference between cells due to the reduction of the cell spacing and the suppression of soft error caused by the alpha particle incident are the most important issues for the development of next-generation memory devices along with the reduction of the cell size. The conventional cell is a DIET (DIelectrically Encapsulated Trench Capacitor Cell) of 4M DRAM (DRAM) as shown in first (a) (b) and has a size of 12.72 μm ² (2.4 μm × 5.3 μm). That is, on the P-type silicon substrate 1, the plate electrode 2, the insulating film 3, the storage node 4, the polysilicon 5 connecting the source and the storage node, and the LOCOS (LOCal Oxidultion of Silicon) insulating film ( 6), capacitor dielectric film 7, source 8, drain 9, word line 10, bit line 11 and trench capacitor region 123, and trench contact region 13;

In the cell structure, since the polysilicon 2 doped with boron is surrounded by the capacitor dielectric film 7 with the polysilicon 4 doped with phosphorus, the silicon substrate 1 toward the silicon substrate 1. Since the depletion layer distance can be shortened, the gap between trenches can be narrowed.

It is anticipated that the above characteristics will further reduce the cell size to be applicable to 16M DRAM. However, the reduction of the gap between cells causes additional problems such as narrowing the gap between the trench contact 13 and the word line 10 and the diagonal gap between the trench contact 13, so that the cell can be reduced only by the ability to control the interference between the trenches. The proposal is somewhat unreasonable.

FIG. 2 is a substrate plate trench (SPT) cell of 4M DRAM, a P-type silicon substrate 14, a P-type epitaxial layer 15, an N-type well 16, a boron-doped drain 17, and a boron-doped source. (18) Boron-doped polycrystalline silicon (19) Capacitor dielectric film 20 Polycrystalline silicon (19) connecting boron-doped polysilicon (19) and source (18) Word line (22) Bit line (23) LOCOS It is an insulating film 24. Unlike conventional cells, this cell uses a P-type transfer transistor by setting an active region in an N-type well because the N-type well and the P-type substrate and the P-type epilayer boundary are used. The energy barrier formed prevents the minority carriers generated by alpha particle incidence and other substrate noise from being collected in the storage capacitor, thereby suppressing the occurrence of softer errors and increasing the signal-to-noise ratio. will be.

As such, the cell type has a different structure for each purpose such as suppression of interference between cells and suppression of soft error generation, but basically a transfer transistor composed of a drain, a source, and a gate as shown in FIGS. 1 and 2. And storage capacitors, as well as isolation for isolation from neighboring cells, have become fundamental elements of the cell area.

Therefore, the purpose of the present invention is to avoid the sudden increase in the technical difficulty in increasing the integration of DRAM (RAM), instead of filling the area of the source portion present in the cell form inside the trench capacitor, ultra-high density memory even at the existing process technology level. To make a cell.

Another object of the present invention is to significantly reduce the source area compared to the existing cells, and to significantly reduce the probability of occurrence of soft errors due to alpha particle incidence by bringing the distance between the cell, the cell and the active area to within 2 μm. .

It is still another object of the present invention to suppress interference between cells by separating all active regions except trench portions by a trench isolation method.

Hereinafter, the present invention will be described in detail with reference to the following examples.

3 is a cell arrangement diagram according to the present invention. In the present invention, the width of the third polysilicon 25 forming the gate is 0.8 μm, and the interval between the active regions 26 is 1.0 μm, and the gap between the first trenches 27 is 0.5 μm. The area of the first trenches 27 is 0.8 μm × 2.0 μm, and the distance between the third polycrystalline silicon 25 is 2.4 μm, the width of the metal wires 28 is 1.0 μm, and the junction between the metal wires 28 and silicon 29 ) Is 1.5 μm × 0.8 μm, the active area of the junction 29 is 2.1 μm × 1.4 μm, and the distance between the third polysilicon 25 and the first trench 27 is 0.15 μm, and the active area 26 and The overlapping portion of the first trench 27 is 0.55 μm, the longitudinal direction of the first trench 27 and the active area 26 of the junction portion 29 are 0.3 μm, and the metal wire 28 is 1.0 μm. Portions other than the active region 26 are separated by the second trench 30. The drain portion of the transfer transistor is effectively arranged so as to share two transistors, and in the conventional various cells, a source disposed on a plane is buried into the first trench 27 to form a pattern forming process (Photolithography) of the first trench 27. Even considering 0.15 μm of alignment margin due to misalignment between the pattern forming operations of the third polycrystalline silicon 25, the source area on the plane is only 0.12 μm (source area ratio to cell area = 1.8%). Only the source area can be extremely reduced.

The cell driving sequence according to the present invention is as follows. It acts as a word line 25, a bit line 28, information (voltage) is applied from the bit line 28, and the word line 25 is optionally a gate of information. A series of DRAM operations are performed by writing information into the first trench 27 in a specific matrix (address) or reading already stored information while opening or closing the.

4 is a cross-sectional view taken along line A-A of FIG. The third polycrystalline silicon serves as the word line 25, the gate oxide film 34, the metal line serves as the bit line 28, and the arsenic doped drain 35 source 33 forms the first trench 27. It is the part which is buried in). It is a P + type silicon substrate 31 and a P- epi layer 32. The second trench region 30 is filled with an oxide film by a chemical vapor deposition apparatus (CVD). The capacitor oxide film 36, the low temperature oxide film (LTO) 38, and the protective film 39 are provided.

In view of the important process dimensions of the present invention, the first trench 27 has a depth of 5 μm, the second trench 30 has a depth of 1.5 μm, the P-type epi layer 32 has a thickness of 1.2 μm, and the first trench. The space | interval of (27) and the adjacent 1st trench 27 is 0.5 micrometer. In the case of the above-mentioned first trench 27 structure, the third polysilicon 25 has a concentration of about 1 × 10 ²⁰ cm ⁻³ and the P + substrate 31 is about 1 × 10 ¹⁹ cm ⁻³ . At least 40 fF of the capacitance was obtained, indicating that the allowance of the capacitance was sufficient.

The cell according to the present invention is a silicon substrate plate such as BSE (Buried Storage Electrode), SPT, etc., unlike a silicon substrate node type which accumulates electric charges in the trench outer wall such as CCC (Corrugate Cpacitor Cell) or DTC (Depletion Trench Capacitor). (Plate) type was adopted.

In the silicon substrate node type, the depletion layer is formed by the voltage applied to the plate, and when alpha particles are incident, charges generated in the silicon substrate are collected into the trench outer walls, which is likely to cause punch-through and soft errors. On the other hand, the cell according to the present invention stores electric charges in the trench inner wall 27, and the built-in electric charges are protected by the wall insulating film 36, which is resistant to soft errors.

In addition, since the charge sources between adjacent cells are completely separated, cross talking due to charge does not occur even when the depletion layers overlap. For this reason, in the cell structure, the distance between the first trench 27 and the adjacent first trench 27 may be 0.5 μm, and theoretically, the resolution of the pattern formation may be narrowed.

In addition, since the source is embedded in the trench 27, even if a carrier is generated by not only the incident of alpha particles, but also various changes such as light and heat, the area 33 collected into the trench 27 is extremely small. In addition to very strong immunity, the ability to suppress various other electrical noise is very large.

FIG. 5 is a cross-sectional view taken along line BB of FIG. 3 and the active regions 26 are completely separated by the second trench 30 filled with the chemical vapor deposition CVD oxide film, and the first trench 27 is also isolated by the second trench 30. . In addition, the second polycrystalline silicon region 37 and the active region 26 invading the first trench 27 region were also separated into the second trench 30. By such a trench isolation method by the second trench 30, electrical interference between the active region, the trench, the capacitor, and the second polycrystalline silicon can be suppressed.

6 is a cross-sectional view of a portion corresponding to A-A of FIG. 3 schematically illustrating a process of manufacturing a source submerged trench cell according to the present invention in the order of (a) to (f).

First, the process up to FIG. 6 (a) will be briefly described. The P + silicon substrate 31 has a concentration of about 1 x 10 ^-19 cm ^-3 and grows a P-type epitaxial layer 32 having a thickness of 1.2 mu m and a resistance value of 5-20 cm ³ on the substrate. Chemical vapor deposition (CVD) of BPSG (Borophospo Silicate Glass) film 41 having a weight ratio of boron (B) and phosphorus (P) of 8000 Å in thickness of 4%, respectively, as a mask layer for trench etching on the epitaxial layer 32. To be deposited. Subsequently, after forming the first trench 27 pattern, the photoresist is removed, and trench etching is performed by adjusting plasma etching conditions so that the etching ratio of the BPSG film 41 and the silicon substrate 31 is 1:10. Conduct. When the first trench 27 is etched to have a depth of 5 μm, the BPSG film 41 is left at about 3000 μs. The acute angles of the concave portion 42 and the convex portion 43 of the first trench 27 strengthen the electric field so that the corner portions 42 and 43 when the capacitor is finally completed. The breakdown voltage of the transistor is lowered and the leakage current increases, which is a major cause of deterioration of the capacitor reliability.

To suppress this phenomenon, by growing an oxide film having a thickness of about 400 kPa, the acute angles of the corners 42 and 43 are further reduced by removing the 400 kPa oxide film by wet etching. Subsequently, the capacitor oxide film 36 is grown to a thickness of 150 Å, and then the first polycrystalline silicon 40 doped with a thickness of 8000 Å and a phosphorus (P) concentration of about 1 × 10 ²⁰ cm ⁻³ is filled in the first trench 27.

FIG. 6 (b) shows a process of etching back to the inside of the first trench 27 after removing the first polysilicon 40 on the BPSG film 41 by etching back by the plasma etching method. . The important thing in this process is to adjust the etch depth by the junction depth of the transfer transistor (approximately 0.2µm). If there is a large difference between the depth of the drain and the depth of over etching into the first trench 27, the carrier movement between the source and the drain becomes asymmetric, and thus the overetching depth 44 may be adjusted. Be careful.

45 is a capacitor oxide film having a thickness of 150 A exposed due to overetching of the first polycrystalline silicon 40. Referring to FIG. This portion of the oxide film 45 is wet etched with a 100: 1 (hydrogen fluoride) solution for about 6 minutes to expose the P epitaxial layer 32 on the side surface.

6C shows a cross-section of the non-doped second polysilicon 37 deposited about 5000 mV and then etched back by planar etching to planarize. In this case, the second polysilicon 37 is not doped to prevent the channel length from being shortened by the diffusion of the dopant during the heat treatment process after the deposition of the second polycrystalline silicon.

FIG. 6 (d) is a cross-sectional view after the second trench etch following the second trench pattern formation (or active region pattern formation) operation for trench isolation.

In this process, three important points in the process technique are that the first trench isolation region 30 occupies a substantial portion of the first trench region 27, and the second trench depth is at least 0.3 μm deeper than the P-epitaxial layer. And boron (B) ion implantation for the third side channel stop. In the conventional cell arrangement, when the source is buried, the active region, the trench capacitor, and the like are close to each other, so that the source can no longer be reduced. However, as shown in the present invention, the trench isolation region is formed into the first trench region 27. By overlapping 30, this limiting factor is solved so that not only the source buried form is possible, but also the amount of overlapping area can be reduced.

In addition, by penetrating the depth of the second trench 30 to the region of the P + silicon substrate 31 having a high concentration, the length of the depletion layer due to the voltage applied to the adjacent trench can be shortened, thereby reducing the interference between cells.

46 is a part likely to operate as a side wall transistor due to the trench isolation method. In order to eliminate the possibility of side transistor operation, it is necessary to increase the threshold voltage of the portion 46 and remove surface damage of the side portion.

First, in order to increase the threshold voltage, boron fluoride (BF2) is injected while tilting at a concentration of about 1 × 10 ¹³ cm ⁻² with an ion implanter. Reference numeral 47 shows a P-type region formed by this process. Subsequently, after removing the mask oxide film 48 for etching the second trench 30, an oxide film having a thickness of about 200 μm is grown by a dry oxide growth method. In this way, boron (B) injection and thermal oxide film growth method can suppress the leakage current of the side portion 46.

The process up to Figure 6 (e) is as follows. The second trench 30 is filled with a CVD oxide film, but first, an undoped chemical vapor deposition (CVD) oxide film is deposited to a thickness of about 3,000 두께 at about 380 ° C. Then, boron (B) and phosphorus (P) are each 4% by weight. A BPSG film was deposited to a thickness of 12000 mm 3.

Subsequently, the photoresist film is applied, and the back trench is etched back with the plasma etching equipment so that the etching ratio of the photoresist film and the BPSG film is 1 :! to planarize the second trench 30. In this case, the portion of the second trench 30 extending longer than 1.5 μm may not be perfectly flattened by a chemical vapor deposition (CVD) oxide film, but there may be a problem in device operation even if there is some bending. Subsequently, 150 Å of gate oxide film 34 and 4,000 3 of third polysilicon 25 serving as a word line are deposited, and a gate is formed by a gate pattern forming operation, and arsenic is formed to form a drain 35 and a buried source 33. (As) is ion-implanted at a concentration of 5 × 10 ¹⁵ cm ⁻² and diffused by heat treatment so that the injected arsenic is about 0.2 μm in junction depth.

Subsequently, a low temperature oxide film LTO (LTO) 38 made of a BPSG film 4000 된 containing 4% by weight of boron (B) and phosphorus (P) was deposited on 3000 Å of an undoped chemical vapor deposition (CVD) oxide film to form a contact pattern. After the work is completed, the metal wire 28 is connected and finally, the protective film 39 may be deposited using a silicon nitride film by a plasma chemical vapor deposition apparatus (PECVD).

This series of manufacturing processes completes a new cell of the type shown in FIG. As described above, according to the present invention, even if the alignment margin due to misalignment between the patterning operation of the first trench and the patterning operation of the third polycrystalline silicon is considered by embedding the source into the first trench, the source area on the plane is small. The specific gravity of the area can be extremely reduced, and the area where carriers are collected in the trench audio trench due to various changes such as light and heat as well as alpha particle incidence is extremely small, which shows very strong resistance to soft errors. It is also possible to reduce the area by overlapping the second trench isolation region in the first trench region, and to penetrate the second trench depth to the region of high concentration P + type silicon substrate, thereby providing a voltage applied to the adjacent trenches. The length of the depletion layer can be shortened by the interference between cells Reduces the phase and as well as the on the side of the transistor section by giving second trench is by giving the the boron trifluoride (BF ₂₎ in an ion implanter in order to raise the threshold voltage gradient injection and illumination thickness is grown 200Å degree of the oxide film in the oxide film growth method It can provide a new structure that can suppress the leakage current.

Claims (7)

After growing the P-type epitaxial layer 32 on the P-type silicon substrate 31 and depositing a 4WT% BPSG thin film 41 with a weight ratio of boron (B) and phosphorus (P) having a thickness of 8000 kPa thereon by chemical vapor deposition; The first trench 27 is etched to have a depth of 5 μm, and then the pattern forming means and the capacitor oxide film 36 are grown to a thickness of 150 μs, and then a phosphorus (P) concentration of about 8000 μm is about 1 × 10 ²⁰ cm ⁻³ . Means for filling the doped first polysilicon 40 in the first trench 27 and subsequently removing the first polysilicon 40 over the BPSG film 41 by plasma etching. 27) The inner polysilicon 40 is etched about 0.2 [mu] m, and the means for removing the exposed capacitor oxide film 45 by wet etching and the second polysilicon 37 are deposited after about 5000 microseconds. Planarize by plasma etching and form a second trench pattern for trench isolation, Wrench (27) formed in the overlap trench isolation region 30, and this the boron trifluoride (BF2) to increase the threshold voltage of 1 × 10 ¹³ cm ^-2 while the slope in the concentration and then the means for injecting the mask oxide film 48 After removal, the second trench 30 is planarized, and then arsenic (AS) is formed to form a third polycrystalline silicon 25 having a thickness of 4000 kPa of the gate oxide film 34 and then form a buried source 33 for the drain 35. Means for depositing the protective film 39 with silicon oxide film by ion implantation of 5 × 10 ¹⁵ cm ^-2 concentration and diffusion of heat treatment to a junction gear of about 0.2 μm, connecting the low temperature oxide film 38 and the metal wire 28 thereon. A source buried dynamic semiconductor memory device, characterized in that consisting of. The source buried dynamic semiconductor memory device according to claim 1, wherein a source (33) is embedded in the first trench (27) to minimize the area occupied by the source (33) on a plane. 2. The length of the depletion layer according to the voltage applied to the adjacent trenches by overlapping the second trenches 30 in the first trench region 27, but penetrating the depth to the region of the P + silicon substrate 31 having a high concentration. A source buried dynamic semiconductor memory device, characterized in that to shorten and reduce interference between cells. The method of claim 1, wherein the trench isolation using the second trench 30, but the depth of the second trench 30 is deeper than the P- epi layer 32 having a low concentration and thinner to the wall of the second trench 30. Before forming the P-type layer 47 and filling the second trench 30 with the oxide film by chemical vapor deposition, about 200 microseconds of a high quality oxide film 48 is first grown so as to suppress side transistor operation and sidewall leakage current. A source buried dynamic semiconductor memory device. 2. The method of claim 1, wherein the first trench 27 is etched to a depth of 5 [mu] m, but an oxide film having a thickness of 400 mu m is grown and then removed by wet etching to slow the acute angles of the corners 42 and 43. A source buried dynamic semiconductor memory device characterized by improving reliability. The method of claim 1, wherein the second trenches 30 occupy a substantial portion of the first trenches 27, thereby preventing the proximity between the active capacitors 26 and the trench capacitors 27 due to the source filling. A source buried dynamic semiconductor memory device characterized in that interference can be suppressed. The method according to claim 1, wherein the area of the source 33 is reduced so that the distance between the cell and the cell and the active region 26 is approximated to within 2 μm, thereby greatly reducing the probability of occurrence of soft errors due to alpha particle incidence. A source buried dynamic semiconductor memory device characterized by the above-mentioned.

Images