KR100460968B1 - OFDM receiving system - Google Patents

Abstract

The disclosed OFDM receiving system includes a block for estimating the start point of a symbol of an OFDM signal, a block for estimating a coarse frequency offset of the OFDM signal, a block for estimating a fine frequency offset of the OFDM signal, and a block for processing the OFDM signal. A plurality of memories each delay the received OFDM signal for the required time. The capacity of each memory is exactly the size needed to store the OFDM signal for the time it takes for each block to process the signal. Therefore, a large capacity memory for storing an OFDM signal during signal processing is not required, thereby reducing the production cost of the OFDM receiving system.

Description

ODP receiving system {OFDM receiving system}

The present invention relates to an OFDM reception system, and more particularly, to an OFDM reception system having a memory for storing a reception signal for a time required for performing signal processing during signal processing of each block for processing a reception signal.

1 is a block diagram of a conventional OFDM receiving system.

The OFDM signal received by the receiving system is converted into a digital signal by an analog-to-digital converter (ADC) (not shown) and then input to a signal detection block 10. The signal detection block 10 detects whether an OFDM signal has been received. The AGC block 12 amplifies the received signal so that the received signal is a signal within the dynamic range of the ADC. Coarse Frequency Estimation block 14 estimates the approximate frequency offset of the received signal. The symbol timing estimation block 16 estimates the starting point of the symbol of the received signal. Fine Frequency Estimation block 18 estimates the fine frequency offset of the received signal.

The FIFO register 20 is a memory block for storing the received signal input to the receiving system. The frequency correction block 22 corrects the frequency offset. Guard Interval Removal block 24 removes the Guard Interval in the received symbol. The FFT block 26 performs a Fast Fourier Transform on the received signal.

Virtual Carrier Removal and Reposition block 28 removes the Virtual Carrier and rearranges the symbols. The channel estimation block 32 estimates the characteristics of the channel by using a long training symbol included in the received OFDM signal. The equalizer 30 corrects the distortion characteristic of the channel by using the value stored in the FIFO register 20 after channel estimation.

Phase Error Correction block 34 estimates and corrects the phase noise of the clock. Pilot Removal and Power Denormalization block 36 removes the pilot signal and restores the amplitude of the signal normalized at the OFDM transmitter. The hard decision block 38 is a block that determines the constellation of the received signal.

In the conventional OFDM receiving system having the above configuration, the function of the FIFO register 20 is that while each block performs a series of signal processing on received signals after reception of the OFDM signal is confirmed, that is, frequency It performs a function of storing received signals during operations such as offset estimation, symbol start point estimation, virtual carrier removal and symbol rearrangement, channel characteristic estimation, and clock phase noise estimation. As such, while estimating the noise component included in the received signal and estimating the start point of the symbol, the received signals are stored in the FIFO register 20 to prevent the loss of the received signals. Output Timing) to output the received signal from the FIFO register 20 to correct the noise component. Therefore, since a continuous input signal must be continuously stored until the final output signal is generated, a very large FIFO register 20 is required.

In consideration of the prior art as described above, the present invention enables a continuous reception of a received signal for a required time in each signal processing block without employing a large-capacity FIFO register, thereby lowering the production cost and providing a practical OFDM reception system. To provide.

1 is a block diagram of a conventional OFDM receiving system, and

2 is a block diagram of an OFDM receiving system according to the present invention.

Explanation of symbols on the main parts of the drawings

51 to 55: RAM 60: signal detection block

62: AGC block 64: rough frequency estimation block

66: symbol timing estimation block 68: fine frequency estimation block

72: coarse frequency correction block 74: fine frequency correction and GI removal block

76: FFT block

An OFDM receiving system according to the present invention for achieving the above object comprises: a symbol timing estimation block for estimating a starting point of a symbol of a received OFDM signal; A coarse frequency estimation block for estimating a coarse frequency offset of the OFDM signal; A fine frequency estimation block for estimating a fine frequency offset of the OFDM signal in which the coarse frequency offset is corrected; And a plurality of memories each delaying the received OFDM signal for a time required for the symbol timing estimation block, the coarse frequency estimation block, and the fine frequency estimation block to process the OFDM signal.

Here, the plurality of memories are composed of first to fourth memories. The first memory is configured to delay the OFDM signal for a time required for the symbol timing estimation block to estimate a start time of the symbol, and to increase the time required for the coarse frequency estimation block to estimate the coarse frequency offset. Delay the OFDM signal. A second memory, together with the first memory, delays the OFDM signal for a time required for the symbol timing estimation block to estimate the start time of the symbol. The third memory, together with the first memory and the second memory, delays the OFDM signal for a time required for the symbol timing estimation block to estimate the start time of the symbol, and the fine frequency estimation block Delay the OFDM signal for the time required to estimate the fine frequency offset. The fourth memory, together with the third memory, delays the OFDM signal for a time required for the fine frequency estimation block to estimate the fine frequency offset.

On the other hand, the OFDM receiving system according to the present invention, channel estimation block for estimating the characteristics of the channel using a long training symbol (Long Training Symbol) included in the received OFDM signal; A phase error correction block for estimating and correcting phase noise of a clock; A fifth memory for delaying the OFDM signal by the time required for the channel estimation block to estimate the channel; And a sixth memory that delays the OFDM signal by the time required for the phase error correction block to estimate the phase noise.

Here, the memory may be configured as a RAM.

According to the present invention, a plurality of memories having a small size are used instead of a large FIFO register. Therefore, the production cost of the OFDM receiving system can be reduced.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram of an OFDM receiving system according to the present invention.

The OFDM receiving system according to the present invention includes a plurality of RAMs 51 to 56 which can individually perform portions of the functions of the large-capacity FIFO registers in the conventional OFDM receiving system. RAM is needed to store the received signal while each block in the receiving system is operating. In the present embodiment, an example of storing the receiving system using the RAM for the signal processing time required for each block is illustrated, but it is also possible to implement not only the RAM but also a general memory. The capacity of such a general memory or RAM 51 to 56 and the specific operation of the OFDM receiving system using the same will be described later.

The received signal received by the receiving system is converted into a digital signal by an analog-to-digital converter (ADC) (not shown) and then input to a signal detection block 60. The signal detection block 60 detects whether an OFDM signal has been received. The AGC block 62 amplifies the received signal so that the received signal is a signal within the dynamic range of the ADC. Coarse Frequency Estimation block 64 estimates the approximate frequency offset of the received signal. A symbol timing estimation block 66 estimates the starting point of the symbol of the received signal. Fine Frequency Estimation block 68 estimates the fine frequency offset of the received signal.

Coarse Frequency Correction block 72 corrects the coarse frequency offset. Fine Frequency Correction and Guard Interval Removal block 74 corrects fine frequency offsets and also removes Guard Intervals within received symbols. The FFT block 76 performs a Fast Fourier Transform on the received signal.

The Virtual Carrier Removal and Reposition block 78 removes the Virtual Carrier and rearranges the symbols Channel Estimation Block 82 is included in the received OFDM signal. A long training symbol is used to estimate channel characteristics, and the equalizer 80 corrects distortion characteristics of the estimated channel.

Phase Error Correction block 84 estimates and corrects the phase noise of the clock. Pilot Removal and Power Denormalization block 86 removes the pilot signal and restores the amplitude of the signal normalized at the transmitter. The hard decision block 88 determines the constellation of the received signal.

The plurality of RAMs 51 to 56 are disposed between the respective blocks to store the received signals for the time required for the respective signals to be processed. The capacity of each of the RAMs 51 to 56 is large enough to store the received OFDM signal for the time required for the corresponding blocks to process the signal, and preferably, it is accurate to store the received OFDM signal for the required time. Has the required size. As a result, each block can perform a normal signal processing operation while minimizing the size of each RAM 51 to 56.

In the following description, the capacities of the RAMs 51 to 56 are exemplary, and the capacities illustrated in this manner may be varied to be optimized according to the signal processing performance of each block. The capacity of each RAM 51 to 56 is expressed in the form of X × Y, which means that Y data of X bits can be stored. More than Y newly input data are overwritten to the address where the first input data among the existing data is stored. Therefore, the RAM can store X bits of data for substantially Y clock time. As described above, Y is preferably set to be equal to the number of clocks required for signal processing in each block corresponding to each of the RAMs 51 to 56.

The first RAM 51 is provided at the front end of the symbol timing estimation block 66. The first RAM 51 has a size of 10 × 64. The first RAM 51 functions to delay the received signal by a portion (64 clocks) of the total time (256 clocks) required for the symbol timing estimation block 66 to estimate the start of the symbol, and also to estimate the rough frequency. Block 64 functions to delay the received signal by the time (64 clocks) needed to estimate the coarse frequency offset.

The second RAM 52 to the fourth RAM 54 are provided in series at the next stage of the coarse frequency correction block 72. The second RAM 52 has a size of 12 × 128, and both the third RAM 53 and the fourth RAM 54 have a size of 12 × 64.

The second RAM 52 and the third RAM 53 function to delay the received signal for 128 and 64 clocks, respectively, while the symbol timing estimation block 66 estimates the start time of the symbols. In addition, the third RAM 53 functions to delay the received signal for a time (64 clocks) required for the fine frequency estimation block 68 to estimate the fine frequency offset. The fourth RAM 54 also functions to delay the received signal for a time (64 clocks) required for the fine frequency estimation block 68 to estimate the fine frequency offset.

Accordingly, the symbol timing estimation block 66 may use the received signals stored for a total of 256 clocks necessary for estimating the start time of the symbol by using all of the first to third RAMs 51 to 53. The coarse frequency estimation block 64 may use the received signal stored by 64 clocks necessary for estimating the coarse frequency offset using the first RAM 51. The fine frequency estimation block 68 may use the received signal stored as many as 128 clocks necessary for estimating the fine frequency offset using the third RAM 53 and the fourth RAM 54.

The fifth RAM 55 and the sixth RAM 56 have a size of 10 × 52. The fifth RAM 55 is the time (52 clocks) required for the channel estimation block 82 to estimate the channel, and the sixth RAM 56 is the phase error correction block 84 estimating the phase noise by the clock. It delays the time required for the clock (52 clocks).

Hereinafter, a detailed operation of the OFDM reception system according to the present invention having the above configuration will be described.

The signal detection block 60 determines whether an OFDM signal is input, and when the input of the OFDM signal is confirmed, the AGC block 62 estimates the gain of the received signal and outputs a gain control value. When the gain control is completed, the coarse frequency estimation block 64 and the symbol timing estimation block 66 are activated, and they perform the coarse frequency offset estimation operation and the symbol start time estimation operation, respectively. In order to estimate the start time of a symbol, a received signal and a delayed signal delayed by 64 clocks are required. The first RAM 51 having a size of 10 × 64 delays the received signal by 64 clocks and transmits the received signal to the symbol timing estimation block.

When the coarse frequency estimation is completed, the coarse frequency correction block 72 corrects the frequency offset, and the corrected signal is transferred to the second RAM 52 having a size of 12 × 128. Estimation of the starting point of the symbol is performed for a total of 256 clocks. In this case, in order to prevent loss of a signal, a received signal is obtained by using a second RAM 52 having a size of 12 × 128 and a third RAM 53 having a size of 12 × 64. Delay.

The location of the long training symbol is required for the fine frequency estimation. Since this information is known after the start of the symbol, the fine frequency estimation block 68 is a symbol by the symbol timing estimation block 66. Activated after completion of the timing estimation operation. Here, the position information of the long training symbol indicates a time point at which the long training symbol is output from the third RAM 53 used for the delay of the signal.

In the prior art, in order to know the starting point of a long training symbol, signals received after the completion of the OFDM frame input are stored in the FIFO register, the start point of the symbol is estimated, and the first part of the long training symbol is stored in the FIFO register. Get the address located. This method requires a large size FIFO register because all received signals must be stored until the start of the symbol estimate is completed. However, in the present invention, the internal counter is activated from the time when the input of the OFDM frame is confirmed to estimate the start time of the symbol after the completion of the estimation of the start time of the symbol. The delay of the signal used for the coarse frequency offset correction is used to find out when the long training symbol is output from the third RAM 53. The following equation is used to calculate the time point at which the long trading symbol is output from the third RAM 53.

Output point = estimated symbol position-128 + amount of RAM (64 + 128)

In this equation, the pipeline delay due to the hardware configuration of each block is not considered.

The estimated symbol position in this equation represents the end of the long training symbol. Therefore, the long training symbol is started at the position corresponding to -128 samples. The starting point of the fine frequency offset estimation is activated when the counter output equals the above calculated output time + 64 + α. Here, α is a delay component of a signal necessary for calculating a fine frequency offset estimation start point after output point calculation and appears in hardware design. The fine frequency estimation is performed for 64 clocks. During this time, the signal is delayed in the fourth RAM 54 having a size of 12 × 64, and the fine frequency offset correction and the guard interval are controlled after the estimation is completed. To pass.

When the FFT operation is completed, the virtual carriers inserted and transmitted by the transmitter are removed and the signals are rearranged. Next, the channel estimation block 82 for estimating the characteristics of the channel is activated, and delays the signal in the fifth RAM 55 having a size of 10 x 52 during the channel estimation period. When the channel estimation is completed, a function of compensating for the distortion characteristics of the channel and estimating and correcting the phase noise component of the clock is performed. In order to estimate the phase noise of the clock, 52 clocks are required, and the sixth RAM 56 of size 10 × 52 delays the signal for the required time. Compensated for the phase noise, the signal is recovered from the baseband receiving system after the power denormalization function, which removes the pilot signal and restores the amplitude of the signal in accordance with the subcarrier modulation mode. Will print.

In the present invention, the function of the FIFO register is implemented as a memory having a size that can accurately store the received signal during the delay time required by each block without using a large FIFO register that causes a large burden in hardware. Therefore, the hardware burden when manufacturing the receiving system is reduced, and the production cost can be lowered when the receiving system is manufactured by the IC.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone skilled in the art can make various modifications, as well as such modifications are within the scope of the claims.

Claims (5)

A symbol timing estimation block for estimating a starting point of a symbol of the received OFDM signal; A coarse frequency estimation block for estimating a coarse frequency offset of the OFDM signal; A fine frequency estimation block for estimating a fine frequency offset of the OFDM signal in which the coarse frequency offset is corrected; And And a plurality of memories each delaying the received OFDM signal for a time required for the symbol timing estimation block, the coarse frequency estimation block, and the fine frequency estimation block to process the OFDM signal. OFDM receiving system. The method of claim 1, The plurality of memories, Delaying the OFDM signal for the time required for the symbol timing estimation block to estimate the start time of the symbol, and delaying the OFDM signal by the time required for the coarse frequency estimation block to estimate the coarse frequency offset. A first memory; A second memory, together with the first memory, for delaying the OFDM signal for a time required for the symbol timing estimation block to estimate a start time of the symbol; Delaying the OFDM signal for a time required for the symbol timing estimation block to estimate the start time of the symbol together with the first memory and the second memory, and the fine frequency estimation block estimates the fine frequency offset. A third memory for delaying the OFDM signal for a time required for And And a fourth memory for delaying the OFDM signal for a time required for the fine frequency estimation block to estimate the fine frequency offset together with the third memory. The method of claim 2, And the first to fourth memories are RAMs. The method of claim 2, A channel estimation block estimating characteristics of a channel using a long training symbol included in the received OFDM signal; A phase error correction block for estimating and correcting phase noise of a clock; A fifth memory for delaying the OFDM signal by the time required for the channel estimation block to estimate the channel; And And a sixth memory for delaying the OFDM signal by the time required for the phase error correction block to estimate the phase noise. The method of claim 4, wherein And said fifth and sixth memories are RAMs.