KR100457164B1 - Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device - Google Patents

Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device Download PDF

Info

Publication number
KR100457164B1
KR100457164B1 KR1019970028720A KR19970028720A KR100457164B1 KR 100457164 B1 KR100457164 B1 KR 100457164B1 KR 1019970028720 A KR1019970028720 A KR 1019970028720A KR 19970028720 A KR19970028720 A KR 19970028720A KR 100457164 B1 KR100457164 B1 KR 100457164B1
Authority
KR
South Korea
Prior art keywords
conductive layer
layer
insulating film
insulating
semiconductor device
Prior art date
Application number
KR1019970028720A
Other languages
Korean (ko)
Other versions
KR19990004593A (en
Inventor
전성도
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970028720A priority Critical patent/KR100457164B1/en
Publication of KR19990004593A publication Critical patent/KR19990004593A/en
Application granted granted Critical
Publication of KR100457164B1 publication Critical patent/KR100457164B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to guarantee the capacitance sufficient for high integration of a semiconductor device by introducing a simple plug process and by maximizing the area of a capacitor of a semiconductor device. CONSTITUTION: The first insulation layer(12), a pad insulation layer(13) and the second insulation layer(14) are sequentially formed on a silicon substrate(11). The second insulation layer, the pad insulation layer and the first insulation layer are etched by using a storage node contact mask to form a contact hole(15), and the first conductive layer plug(16') is formed to fill the contact hole. The third insulation layer(17), the second conductive layer(18) and the fourth insulation layer(19) are sequentially formed on the resultant structure. A photoresist layer pattern is formed by using a storage node mask having a mixed contact mask type. The fourth insulation layer, the second conductive layer and the third insulation layer are sequentially etched by using the photoresist layer pattern as a mask, and the third conductive layer is formed on the resultant structure. The third conductive layer is anisotropically blanket-etched to form the third conductive layer plug in the center of a stack structure of the fourth insulation layer, the second conductive layer and the third insulation layer and to form the third conductive layer spacer on the sidewall of the stack structure. The fourth, third and second insulation layers are removed to form a storage node.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 간단한 플러그(Plug) 공정을 도입하여 고집적 소자의 캐패시터 면적을 극대화함으로써 반도체 소자의 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of improving characteristics of a semiconductor device by introducing a simple plug process to maximize the capacitor area of a highly integrated device.

일반적으로 반도체 소자가 점점 고집적화됨에 따라 반도체 칩의 면적이 줄어들고, 또한 캐패시터 형성 면적도 줄어들어 캐패시터 용량의 유지가 반도체 소자 집적화의 관건으로 등장하고 있다.In general, as semiconductor devices are increasingly integrated, the area of the semiconductor chip is reduced and the capacitor formation area is also reduced, so that the maintenance of the capacitor capacity has emerged as a key to the integration of semiconductor devices.

따라서 캐패시터 제조공정에 있어서는 캐패시터가 충분한 정전용량을 확보해야 하므로 제조공정이 단순하면서도 캐패시터의 용량을 크게 하는 것이 매우 중요하다.Therefore, in the capacitor manufacturing process, it is very important to increase the capacity of the capacitor while the manufacturing process is simple, because the capacitor must secure sufficient capacitance.

아울러, 일정한 크기의 체적으로 높은 정전용량을 확보하기 위해서는 표면적을 늘려야 하나, 종래의 기술로는 디자인 마진(Design Margin)이 부족하여 안정된 제조공정의 확보가 어렵고 정전용량이 충분하지 못한 단점을 가지고 있으며, 또한 셀-페리 영역 단차의 증가로 인하여 후속공정이 어려워지는 문제점이 있다.In addition, the surface area should be increased in order to secure a high capacitance with a constant size, but it is difficult to secure a stable manufacturing process due to the lack of design margin, and the capacitance is insufficient. In addition, there is a problem that the subsequent process becomes difficult due to the increase of the cell-ferry region level.

또한 실린더형과 같은 구조의 캐패시터를 이용하더라도 주로 실린더 측면과 윗면만을 이용하므로 캐패시터의 면적을 늘리는 데에는 역시 한계가 따르므로 반도체 소자 제조수율 및 신뢰성을 저하시키는 요인으로 작용되는 문제점이 있다.In addition, even when using a capacitor having a cylinder-like structure, since only the cylinder side and the top surface are mainly used, there is a problem in reducing the semiconductor device manufacturing yield and reliability since the limit of the area of the capacitor is also limited.

본 발명은 상기의 문제점을 해결하기 위하여 간단한 플러그 공정을 도입하여 고집적 소자의 캐패시터 면적을 극대화함으로써 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 하고 그에 따른 반도체소자의 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공함에 그 목적이 있다.In order to solve the above problems, a simple plug process is introduced to maximize the capacitor area of a highly integrated device, thereby ensuring sufficient capacitance for high integration of the semiconductor device, and thereby improving the characteristics of the semiconductor device. It is an object to provide a method of manufacturing a capacitor of the device.

도 1 내지 도 5 는 본 발명의 방법에 따른 반도체 소자의 캐패시터 제조 공정단계를 도시한 단면도1 to 5 are cross-sectional views showing a capacitor manufacturing process step of a semiconductor device according to the method of the present invention

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11 : 실리콘 기판 12 : 제 1 절연막11 silicon substrate 12 first insulating film

13 : 패드 절연막 14 : 제 2 절연막13 pad insulating film 14 second insulating film

15 : 콘택홀 16 : 제 1 도전층15 contact hole 16 first conductive layer

16' : 제 1 도전층 플러그16 ': first conductive layer plug

17 : 제 3 절연막 18 : 제 2 도전층17: third insulating film 18: second conductive layer

19 : 제 4 절연막 20 : 캐패시터 형성용 감광막 패턴19: fourth insulating film 20: photosensitive film pattern for forming capacitor

21 : 제 3 도전층 21' : 제 3 도전층 플러그21: third conductive layer 21 ': third conductive layer plug

21" : 제 3 도전층 스페이서 22 : 캐패시터 절연막21 ": third conductive layer spacer 22: capacitor insulating film

상기 목적을 달성하기 위한 본 발명의 방법에 따른 반도체소자의 캐패시터 제조방법은,Capacitor manufacturing method of a semiconductor device according to the method of the present invention for achieving the above object,

실리콘 기판 상부에 제 1 절연막, 패드 절연막 및 제 2 절연막을 순차적으로 형성하는 단계와,Sequentially forming a first insulating film, a pad insulating film, and a second insulating film on the silicon substrate;

저장전극 콘택마스크를 이용하여 상기 제2절연막, 패드절연막 및 제1절연막을 식각하여 콘택홀을 형성하고 이를 매립하는 제1도전층 플러그를 형성하는 공정과,Forming a contact hole by etching the second insulating layer, the pad insulating layer, and the first insulating layer using a storage electrode contact mask to form a first conductive layer plug filling the same;

전체표면상부에 제3절연막, 제2도전층 그리고 제4절연막을 차례로 형성하는 공정과,Forming a third insulating film, a second conductive layer and a fourth insulating film on the entire surface in turn;

콘택마스크 형상이 조합된 저장전극 마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern using a storage electrode mask having a combined contact mask shape;

상기 감광막패턴을 마스크로 하여 상기 제4절연막, 제2도전층 및 제3절연막을 순차적으로 식각하고 전체표면상부에 제3도전층을 형성하는 공정과,Etching the fourth insulating film, the second conductive layer, and the third insulating film sequentially using the photosensitive film pattern as a mask, and forming a third conductive layer over the entire surface thereof;

상기 제3도전층을 이방성 전면 건식 식각하여 상기 제4절연막, 제2도전층 및 제3절연막 적층구조의 중앙부에 제3도전층 플러그를 구비하고 측벽에 제3도전층 스페이서를 구비하는 공정과,Anisotropically dry-etching the third conductive layer to provide a third conductive layer plug in a central portion of the fourth insulating layer, the second conductive layer, and a third insulating layer stacked structure, and a third conductive layer spacer on a sidewall thereof;

상기 제4절연막, 제3절연막 및 제2절연막을 제거하여 저장전극을 형성하는 공정을 포함하는 것을 특징으로 한다.And removing the fourth insulating layer, the third insulating layer, and the second insulating layer to form a storage electrode.

이하 첨부된 도면을 참조하여 본 발명의 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1 내지 도 5 는 본 발명의 방법에 따른 반도체 소자의 캐패시터 형성공정 단계를 도시한 단면도이다.1 to 5 are cross-sectional views showing the steps of forming a capacitor of a semiconductor device according to the method of the present invention.

도 1 을 참조하면, 실리콘 기판(11) 상부에 제 1 절연막(12)을 형성하고, 그 상부에 패드 절연막(13) 및 제 2 절연막(14)을 차례로 형성한다.Referring to FIG. 1, a first insulating film 12 is formed on a silicon substrate 11, and a pad insulating film 13 and a second insulating film 14 are sequentially formed thereon.

이때, 상기 패드 절연막(13)은 상기 제 1 절연막(12) 및 제 2 절연막(14)과의 습식식각 선택비 차이가 큰 절연물질로 형성한다.In this case, the pad insulating layer 13 is formed of an insulating material having a large difference in wet etching selectivity between the first insulating layer 12 and the second insulating layer 14.

그 다음, 저장전극 콘택마스크를 이용한 사진식각공정으로 상기 제2절연막(14), 패드절연막(13) 및 제1절연막(12)을 식각하여 상기 실리콘기판(11)을 노출시키는 콘택홀(15)을 형성한다.The contact hole 15 exposing the silicon substrate 11 by etching the second insulating layer 14, the pad insulating layer 13, and the first insulating layer 12 by a photolithography process using a storage electrode contact mask. To form.

그 다음, 상기 콘택홀(15)을 매립하는 제1도전층(16)을 전체표면상부에 형성한다. 이때, 상기 제1도전층(16)은 매립특성이 우수한 다결정실리콘으로 형성한다.Next, a first conductive layer 16 filling the contact hole 15 is formed on the entire surface. In this case, the first conductive layer 16 is formed of polycrystalline silicon having excellent embedding characteristics.

도 2 를 참조하면, 상기 제2절연막(14)을 노출시키는 이방성 전면 건식식각을 통하여 상기 제1도전층(16)을 식각한다. 이때 콘택홀(15)은 상기 제 1도전층(16)의 두께 정도의 크기를 갖고 있어서 건식식각시 콘택홀(15) 내의 제1도전층(16)은 도면에 도시된 바와 같이, 콘택홀(15) 안쪽이 약간 리세스(recess)된 제1도전층(16) 플러그(16')Referring to FIG. 2, the first conductive layer 16 is etched through anisotropic front dry etching exposing the second insulating layer 14. At this time, the contact hole 15 is about the size of the thickness of the first conductive layer 16, so that the first conductive layer 16 in the contact hole 15 during dry etching, as shown in the drawing, the contact hole ( 15) Plug 16 'with first conductive layer 16 recessed slightly inside

그 다음, 전체표면상부에 제 3 절연막(17), 제 2 도전층(18) 그리고 제 4 절연막(19)을 차례로 형성하고 감광막패턴(20)을 형성한다.Then, the third insulating film 17, the second conductive layer 18, and the fourth insulating film 19 are sequentially formed on the entire surface, and the photosensitive film pattern 20 is formed.

이때, 상기 감광막패턴(20)은 내측에 위치한 모양이 콘택홀(15)의 모양과 비슷한 크기로 형성된 것으로, 통상의 사각형 저장전극 마스크(도시안됨)와 콘택마스크를 조합하여 형성한 모양을 갖는다.In this case, the photoresist pattern 20 is formed to have a shape similar to that of the contact hole 15, and has a shape formed by combining a conventional rectangular storage electrode mask (not shown) and a contact mask.

도 3 을 참조하면, 상기 감광막패턴(20)을 마스크로 하여 상기 제 4 절연막(19), 제 2 도전층(18) 그리고 제 3 절연막(17)을 차례대로 이방성 건식식각한다.Referring to FIG. 3, the fourth insulating layer 19, the second conductive layer 18, and the third insulating layer 17 are sequentially anisotropically dry-etched using the photoresist pattern 20 as a mask.

그 다음, 전체표면상부에 제3도전층(21)을 형성한다. 이때, 상기 제 3도전층(21)은 상기 제1도전층(16)과 같은 다결정실리콘으로 형성한다.Then, the third conductive layer 21 is formed on the entire surface. In this case, the third conductive layer 21 is formed of the same polysilicon as the first conductive layer 16.

도 4 를 참조하면, 상기 제3도전층(21)을 이방성 전면 건식 식각하여 상기 제3 도전층(21)의 스페이서(21")와 제3도전층(21)의 플러그(21')를 형성한다.Referring to FIG. 4, the third conductive layer 21 is anisotropically dry-etched to form the spacer 21 ″ of the third conductive layer 21 and the plug 21 ′ of the third conductive layer 21. do.

도 5 를 참조하면, 등방성 전면 습식식각을 통하여 제4절연막(19), 제3절연막(17) 및 제2절연막(14)을 제거함으로써 제1도전층(16) 플러그(16'), 제2도전층(18), 제3도전층(21) 플러그(21') 및 제3도전층(21) 스페이서(21")로 실리콘기판(11)에 접속되는 저장전극을 형성한다.Referring to FIG. 5, the first conductive layer 16, the plug 16 ′, and the second conductive layer 16 are removed by removing the fourth insulating layer 19, the third insulating layer 17, and the second insulating layer 14 by isotropic full surface wet etching. A storage electrode connected to the silicon substrate 11 is formed by the conductive layer 18, the third conductive layer 21 plug 21 ′, and the third conductive layer 21 spacer 21 ″.

상기 저장전극의 표면에 캐패시터 절연막(22)을 증착하고 후속 공정으로 플레이트전극(도시안됨)을 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있는 캐패시터를 형성한다.A capacitor insulating film 22 is deposited on the surface of the storage electrode and a plate electrode (not shown) is formed in a subsequent process to form a capacitor capable of securing a capacitance sufficient for high integration of the semiconductor device.

이상 상술한 바와 같이, 본 발명의 방법은 종래의 콘택매립을 위한 플러그 공정을 사용하여 캐패시터의 제조에 응용한 것으로, 플러그 공정은 콘택홀의 크기가 작아도 전혀 문제되지 않으므로 고집적 소자의 캐패시터 형성에 유리한 장점이 있다.As described above, the method of the present invention is applied to the manufacture of a capacitor using a conventional plug process for filling a contact, and the plug process is advantageous for forming a capacitor of a highly integrated device since the contact hole is not a problem at all. There is this.

또한 실린더형 캐패시터의 아래 부분도 이용하고, 종래의 플러그 공정을 이용하여 캐패시터 중앙 부분까지 이용함으로써 캐패시터 면적을 종래의 경우보다 약 2 배 정도 증대시키는 것이 가능하여 소자의 리프레쉬 특성을 개선시키는 효과가 있으며, 공정이 단순하여 양산 가능할 뿐만 아니라 반도체소자의 생산성을 향상시킬 수 있는 장점도 있다.In addition, by using the lower part of the cylindrical capacitor and using the conventional plug process to the center of the capacitor, it is possible to increase the capacitor area by about twice as much as the conventional case, thereby improving the refresh characteristics of the device. In addition, the process is simple and mass-produced, and there is an advantage of improving the productivity of the semiconductor device.

Claims (6)

실리콘 기판 상부에 제 1 절연막, 패드 절연막 및 제 2 절연막을 순차적으로 형성하는 단계와,Sequentially forming a first insulating film, a pad insulating film, and a second insulating film on the silicon substrate; 저장전극 콘택마스크를 이용하여 상기 제2절연막, 패드절연막 및 제1절연막을 식각하여 콘택홀을 형성하고 이를 매립하는 제1도전층 플러그를 형성하는 공정과,Forming a contact hole by etching the second insulating layer, the pad insulating layer, and the first insulating layer using a storage electrode contact mask to form a first conductive layer plug filling the same; 전체표면상부에 제3절연막, 제2도전층 그리고 제4절연막을 차례로 형성하는 공정과,Forming a third insulating film, a second conductive layer and a fourth insulating film on the entire surface in turn; 콘택마스크 형상이 조합된 저장전극 마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern using a storage electrode mask having a combined contact mask shape; 상기 감광막패턴을 마스크로 하여 상기 제4절연막, 제2도전층 및 제3절연막을 순차적으로 식각하고 전체표면상부에 제3도전층을 형성하는 공정과,Etching the fourth insulating film, the second conductive layer, and the third insulating film sequentially using the photosensitive film pattern as a mask, and forming a third conductive layer over the entire surface thereof; 상기 제3도전층을 이방성 전면 건식 식각하여 상기 제4절연막, 제2도전층 및 제3절연막 적층구조의 중앙부에 제3도전층 플러그를 구비하고 측벽에 제3도전층 스페이서를 구비하는 공정과,Anisotropically dry-etching the third conductive layer to provide a third conductive layer plug in a central portion of the fourth insulating layer, the second conductive layer, and a third insulating layer stacked structure, and a third conductive layer spacer on a sidewall thereof; 상기 제4절연막, 제3절연막 및 제2절연막을 제거하여 저장전극을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And removing the fourth insulating film, the third insulating film, and the second insulating film to form a storage electrode. 제 1 항에 있어서, 상기 패드 절연막은 제 2 절연막, 제 3 절연막 및 제 4절연막과의 등방성 습식 식각 선택비 차이가 큰 절연물질로 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the pad insulating layer is formed of an insulating material having a large difference in isotropic wet etching selectivity from the second insulating layer, the third insulating layer, and the fourth insulating layer. 제 1 항에 있어서, 상기 패드 절연막은 Si3N4으로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the pad insulating layer is formed of Si 3 N 4 . 제 1 항에 있어서, 상기 제 1 도전층과 제 3 도전층은 콘택홀 직경의 1/2 보다 두껍게 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the first conductive layer and the third conductive layer are formed to be thicker than 1/2 of the contact hole diameter. 제 1 항에 있어서, 상기 제3도전층 플러그의 직경은 상기 콘택홀 직경과 동일하거나 더 크게 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the diameter of the third conductive layer plug is equal to or larger than the diameter of the contact hole. 제 1 항에 있어서, 상기 제1도전층과 제3도전층은 다결정실리콘으로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the first conductive layer and the third conductive layer are formed of polycrystalline silicon.
KR1019970028720A 1997-06-28 1997-06-28 Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device KR100457164B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970028720A KR100457164B1 (en) 1997-06-28 1997-06-28 Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970028720A KR100457164B1 (en) 1997-06-28 1997-06-28 Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device

Publications (2)

Publication Number Publication Date
KR19990004593A KR19990004593A (en) 1999-01-15
KR100457164B1 true KR100457164B1 (en) 2005-01-31

Family

ID=37376833

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970028720A KR100457164B1 (en) 1997-06-28 1997-06-28 Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device

Country Status (1)

Country Link
KR (1) KR100457164B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249693A (en) * 1994-03-14 1995-09-26 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH0851151A (en) * 1994-08-08 1996-02-20 Mitsubishi Electric Corp Semiconductor device and manufacture of semiconductor device
KR19980040661A (en) * 1996-11-29 1998-08-17 김광호 How to form the lower electrode of the capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249693A (en) * 1994-03-14 1995-09-26 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH0851151A (en) * 1994-08-08 1996-02-20 Mitsubishi Electric Corp Semiconductor device and manufacture of semiconductor device
KR19980040661A (en) * 1996-11-29 1998-08-17 김광호 How to form the lower electrode of the capacitor

Also Published As

Publication number Publication date
KR19990004593A (en) 1999-01-15

Similar Documents

Publication Publication Date Title
JP2001053248A (en) Manufacture of cylinder storage electrode of semiconductor element
US6403431B1 (en) Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits
KR100438782B1 (en) Fabrication method of cylinder type capacitor in semiconductor device
JP2622243B2 (en) Method of manufacturing stack capacitor for semiconductor device
KR100457164B1 (en) Method for fabricating capacitor of semiconductor device to guarantee capacitance sufficient for high integration of semiconductor device
US6207496B1 (en) Method of forming capacitor of semiconductor device
KR100346450B1 (en) A method for forming a capacitor of a semiconductor device
KR20010004932A (en) method of forming cylindrical capacitor of semiconductor device
KR100345067B1 (en) Manufacturing method of semiconductor device
KR100431819B1 (en) A method for forming a capacitor of a semiconductor device
KR20040033963A (en) Method for fabricating semiconductor device with self-aligned storage node
KR100369484B1 (en) Method for manufacturing capacitor of semiconductor device
KR960013644B1 (en) Capacitor manufacture method
KR100419748B1 (en) Method for fabricating semiconductor device
KR20050045608A (en) Method for forming semiconductor device
KR100911675B1 (en) Method for fabricating capacitor of semiconductor device
KR100304689B1 (en) Method for manufacturing capacitor of semiconductor device
KR100400282B1 (en) Method for fabricating capacitor of semiconductor device
KR100637688B1 (en) A method for forming a capacitor of a semiconductor device
KR100631938B1 (en) Manufacturing method for capacitor
KR20040060317A (en) A method for forming a storage node of a semiconductor device
KR100187371B1 (en) Method of manufacturing capacitor of semiconductor memory device
KR20020002633A (en) A method for forming a storage node of a semiconductor device
KR980012526A (en) Method for manufacturing capacitor of semiconductor device
KR19990061112A (en) Capacitor Formation Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101025

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee