KR100455734B1 - Dual Port SRAM Cell Data Amplifier - Google Patents

Abstract

The present invention relates to a data amplification circuit of a dual-port SRAM cell. In the conventional apparatus, when the process conditions change during the manufacturing process, the sensing voltage of the inverter is changed to form an unstable feedback loop, and the total number of MOS devices is also large. There was a problem in that the layout was complicated. Accordingly, the present invention provides first and second PMOS transistors for applying a power supply voltage to the read data lines by using read data and read data bars, and first NMOS transistors for pulling down the read data lines by the read data bars. A first pull-up amplifier composed of; Third and fourth PMOS transistors configured to apply a power supply voltage to the read data bar lines by the read data bar and the read data, and to pull up the read data bar lines by the read data; A second pull-up amplifier configured; The inverter may be configured to invert and output the read data bar to quickly pull up the voltage level of the floating terminal to increase the response speed for the next operation and to reduce the layout area by reducing the number of transistor elements.

Description

Dual Port SRAM Cell Data Amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification circuit of a dual port SRAM cell, and in particular, an amplifier circuit having a pull-up circuit can be configured to reduce the number of transistor elements, reduce the layout area, and to float. The present invention relates to an amplification circuit of a dual port SRAM cell that can quickly pull up a voltage level of a terminal to speed up a response to a next operation.

FIG. 1 is a circuit diagram illustrating a configuration of a dual port SRAM cell. As shown in FIG. 1, the write-enabled signal W_WL is simultaneously applied to the gate side of the NMOS transistors MN1 and MN2 to be turned on, and the NMOS transistor MN1 is turned on. When write data W_Data is inputted to the drain side of the output, it is outputted to the source side and latched. The source side output is branched to the gate side input of the NMOS transistor MN6, and is written to the drain side of the NMOS transistor MN2. When the data bar W_DataB is input, it is output to the source side and latched, and the source side output is branched to the gate side input of the NMOS transistor MN5. Here, in the NMOS transistors MN5 and MN6, the source side of the NMOS transistors MN5 and MN6 are commonly tied to ground Vss, and the drain side outputs of the NMOS transistors MN5 and MN6 are respectively connected to the drain side of the NMOS transistors MN3 and MN4. When the readable signal R_WL is simultaneously applied to the gate side of the NMOS transistors MN3 and MN4, read data R_Data is output to the source side output of the NMOS transistor MN3, and the NMOS A read data bar R_DataB is configured to be output to the source side output of the transistor MN4. The operation process of the dual port SRAM cell configured as described above will be described.

The source-side output signal of the NMOS transistor MN1 is applied to the gate side of the NMOS transistors MN3 and MN4 at the same time, so that the source side output signal of the NMOS transistor MN6 is turned on. The source side output signal of the NMOS transistor MN2 is input to the gate side of the NMOS transistor MN5, and the source side outputs of the NMOS transistors MN1 and MN2 are opposite to each other. If 'high' state, the other side is 'low' state. Therefore, when the source output of the NMOS transistor MN1 is 'high', the NMOS transistor MN6 is turned on and pulled down, so the read data bar R_DataB is outputted as 'low', but the NMOS transistor MN2 is outputted. Since the source side output of the NMOS transistor MN5 is turned off, the read data R_Data is output in a floating state.

As described above, when the 'low' level is input, the output of the 'low' state is correctly output, but when the 'high' level is input, the output is not the 'high' level, but the floating state is output. As a result, an amplifier must be provided in order for the 'high' side to accurately output the 'high' level.

FIG. 2 is a circuit diagram of an amplifier having a conventional pull-up function. As shown therein, the read data R_Data is latched by the inverters INV3 and INV4, and its output is inverted by the inverter INV7. In addition, it is input to one side of the NAND gate NAND1, and the read data bar R_DataB is latched by the inverters INV4 and INV6, and its output is input to the other side of the NAND gate NAND1 so that its output is avoided. Commonly applied to the gates of the MOS transistors MP1 and MP2, the source side of the PMOS transistors MP1 and MP2 is connected to the power supply VCC, and each of the drain sides is a read data R_Data and a read data bar R_DataB. A process of an amplifier having a conventional pull-up function configured as connected to a line) will be described with reference to the timing diagram of FIG. 3 as follows.

When the initial state of the read data R_Data is 'high' state, more precisely, the 'floating' state, and the read data bar R_DataB is 'low' state, as shown in (a) of FIG. 3, the read data (R_Data) Transitions from 'high' to 'low', the signal inverted and output by the inverter INV3 is latched and input to one side of the NAND gate NAND1 as shown in FIG. 3 (B). As the output goes to 'low', PMOS transistors (MP1, MP2) are turned on, and the voltage level pulled up to the power supply voltage (VCC) is inputted to output (Sout) through the inverter (INV3, INV8). When the 'high' level is output and the output passes through the inverter INV4 when the data bar R_DataB becomes 'high' from the 'low' state as shown in FIG. As shown in (c), the signal transitioned to 'low' is inputted to the NAND gate NAND1, and its output is again shown as (d) in FIG. As a result, the PMOS transistors MP1 and MP2 are turned off. When the initial state of the next read data bar R_DataB transitions from 'high' to 'low' as shown in Fig. 3 (g), the signal inverted and output by the inverter INV4 as shown in Fig. 3 (a). Is latched and input to one side of the NAND gate NAND1, and the output thereof transitions to 'low' as shown in FIG. 3 (difference) to turn on the PMOS transistors MP1 and MP2 to turn on the power supply voltage VCC. The voltage level pulled up is inputted, and after a predetermined time, the output passes through the inverter INV3 when the read data R_Data is changed from the low state to the high state as shown in FIG. When a signal transitioned to 'low' as shown in (3) is input to the NAND gate NAND1, the output thereof becomes 'high' as shown in (difference) in FIG. 3, so that the PMOS transistors MP1 and MP2 Is turned off.

However, in the conventional apparatus as described above, when the process conditions change during the manufacturing process, the sensing voltage of the inverter is changed to form an unstable feedback loop, and the number of MOS devices is large, resulting in a complicated layout. .

Accordingly, an object of the present invention is to provide a data amplification circuit of a dual port SRAM cell which is created in order to solve the above-mentioned conventional problems, thereby quickly pulling up the voltage level of a floating terminal to increase the response speed for the next operation. There is this.

An object of the present invention as described above is to first pull down the read data line by the first and second PMOS transistor and the read data bar to apply a power supply voltage to the read data line by the read data and the read data bar. A first pull-up amplifier comprising an NMOS transistor; Third and fourth PMOS transistors configured to apply a power supply voltage to the read data bar lines by the read data bar and the read data, and to pull up the read data bar lines by the read data; A second pull-up amplifier configured; This is achieved by constructing an inverter that inverts and outputs the read data bar.

An embodiment according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

FIG. 4 is a data amplification circuit diagram of the dual-port SRAM cell of the present invention. As shown in FIG. 4, the drain of the first PMOS transistor MP31 is supplied with the supply voltage VCC to the source and the read data R_Data to the gate. The side is connected to the source side of the second PMOS transistor MP32 to which the read data bar R_DataB is applied to the gate, and the drain side of the second PMOS transistor MP32 is connected to the gate of the read data bar R_DataB. A first pull-up amplifier 30 configured to be connected to the drain of the first NMOS transistor MN31 whose source is grounded and connected to the read point R_Data line; A fourth PMOS transistor, which receives the read data R_Data from the drain side of the third PMOS transistor MP33 to which the source voltage VCC is applied to the source and the read data bar R_DataB is applied to the gate, Is connected to the source side of MP34, and the drain side of the fourth PMOS transistor MP34 is connected to the drain side of the second NMOS transistor MN32 to which the read data R_Data is applied to a gate and the source is grounded. A second pull-up amplifier 31 configured to connect the connection point to the read data bar R_DataB line; An inverter INV8 for inverting and outputting the read data bar R_DataB is described below with reference to the timing diagram of FIG. 5.

When the initial state of the read data bar R_DataB transitions from the 'high' state to the 'low' state as shown in FIG. 5A, the second and third PMOS transistors MP32 and MP33 are turned on. As shown in FIG. 5B, the first PMOS transistor MP31 is turned on since the read data R_Data is 'low' and the NMOS transistor of the dual port SRAM cell connected to the read data R_Data ( The read data bar R_DataB is floated because the MN5 is turned off, and the level of the read data R_Data is raised to 'high' by the first and second PMOS transistors MP31 and MP32. As shown in FIG. 5D, the fourth PMOS transistor MP34 is turned off by the pull-up signal of the read data R_Data, and the second NMOS transistor MN32 is turned on to turn on the read data bar R_DataB. By pulling down the signal more quickly, the output Sout is made high through the inverter INV8 as shown in FIG.

In addition, when the read data R_Data transitions from 'high' to 'low' by the NMOS transistor MN5 of the dual port SRAM cell of FIG. 1, the second NMOS transistor MN32 of FIG. 3 is turned off. The read data bar R_DataB is controlled by the read data R_Data. That is, since the read data bar R_DataB is 'low', the third PMOS transistor MP33 is already turned on, and the initial state of the read data R_Data is 'high' as shown in FIG. As the state transitions to 'low', the first and fourth PMOS transistors MP31 and MP34 are turned on. As shown in FIG. 5, the third PMOS transistor MP33 has the read data bar R_DataB ' Since it was in the low 'state, the NMOS transistor MN5 of the dual port SRAM cell connected to the read data bar R_DataB is turned off and the read data bar R_DataB is floated so that the third and fourth PMOS are The level of the read data bar R_DataB is increased by the transistors MP33 and MP34 at the 'low' level as shown in FIG. 5 to raise to the 'high' level. The second PMOS transistor MP32 is turned off by the signal of the read data bar R_DataB pulled up as described above, and the first NMOS transistor MN31 is turned on to pull down the signal of the read data R_Data more quickly. The output Sout of the inverter INV8 having received the 'high' level of the read data bar R_DataB is finally output at the 'low' level as shown in FIG.

As described above, the data amplification circuit of the dual-port SRAM cell of the present invention has an effect of rapidly pulling up the voltage level of the floating terminal to increase the response speed for the next operation and reducing the layout area by reducing the number of transistor elements. have.

1 is a circuit diagram showing the configuration of a dual port SRAM cell.

2 is a circuit diagram of an amplifier having a conventional pull-up function.

3 is a timing diagram of each part of FIG. 2;

4 is a data amplification circuit diagram of a dual port SRAM cell of the present invention.

5 is a timing diagram of each part of FIG. 4;

* Description of the symbols for the main parts of the drawings *

30: first pull-up amplifier 31: second pull-up amplifier

MP31 to MP34: PMOS transistor MN31, MN32: NMOS transistor

INV1 to INV8: Inverter

Claims (2)

A first pull-up comprising first and second PMOS transistors for applying a power supply voltage to the read data line by a read data and a read data bar, and a first NMOS transistor for pulling down the read data line by the read data bar; An amplifier; Third and fourth PMOS transistors configured to apply a power supply voltage to the read data bar lines by the read data bar and the read data, and to pull up the read data bar lines by the read data; A second pull-up amplifier configured; And an inverter for inverting the read data bar and outputting the read data bar. The method of claim 1, wherein the first pull-up amplifier is connected to a source of the second PMOS transistor receiving a read data bar to the gate of the drain of the first PMOS transistor is applied to the source and the read data is applied to the gate And the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor having a read data bar applied to the gate thereof and the source is grounded, and the connection point thereof is connected to the read data line. Data amplifier circuit of the port SRAM cell.

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