CN116580737A - Device, system and method for generating clock pulse width signal for word line delay interlocking circuit - Google Patents

Abstract

Embodiments of the present invention describe systems and devices for a word line delay interlock circuit. The device includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate is configured to receive a reset signal. An interlock circuit is coupled to the output of the first logic gate and is configured to generate a first signal and selectively operate the first logic gate. The delay circuit is connected to an output of the interlock circuit and is configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit. The selective operation of the first logic gate prevents a changing edge of the reset signal from being transferred to the delay circuit in response to the reset signal changing logic state. The embodiment of the invention also discloses a method for generating the clock pulse width signal.

Description

Device, system and method for generating clock pulse width signal for word line delay interlocking circuit

Technical Field

Embodiments of the present invention relate generally to the field of electronic circuits, and more particularly, to devices, systems, and methods of generating clock pulse width signals for word line delay interlock circuits.

Background

Static Random Access Memory (SRAM) devices are widely used in electronic applications requiring high speed and low power consumption. SRAM devices are typically composed of one or more SRAM cells implemented using transistors.

Disclosure of Invention

One aspect of the present invention provides a device for a word line delay interlock circuit, comprising: a first logic gate configured to receive a reset signal; an interlock circuit connected to an output of the first logic gate, the interlock circuit configured to generate a first signal and selectively operate the first logic gate; and a delay circuit connected to an output of the interlock circuit, the delay circuit configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit, wherein selective operation of the first logic gate prevents a changing edge of the reset signal from being transferred to the delay circuit in response to the reset signal changing logic state.

Another aspect of the present invention provides a method of generating a clock pulse width signal, the method comprising: selectively operating the first logic gate by the interlock circuit to prevent a changing edge of the reset signal from being transferred to the delay circuit; generating, by the delay circuit, a clock pulse width signal based on a delayed version of the first signal output by the interlock circuit; and providing the clock pulse width signal to the interlock circuit through a feedback loop for future signal delays.

Yet another aspect of the present invention provides a system for a word line delay interlock circuit, comprising: a Static Random Access Memory (SRAM) device comprising a plurality of cells connected together by word lines, the SRAM device configured to perform a write operation to store information in one or more of the plurality of cells; and a word line driving circuit including: an interlock circuit configured to generate an interlock signal and selectively operate the logic gate to prevent a changed edge of the reset signal from being transferred to the delay circuit; and the delay circuit is connected to the output end of the interlocking circuit, and is configured to generate a clock pulse width signal according to the interlocking signal, wherein the clock pulse width signal is fed back to the interlocking circuit and provided to the word line to promote the writing operation.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings.

Fig. 1 is a block diagram of an exemplary memory device shown in accordance with various embodiments of the present disclosure.

FIG. 2 is an electrical schematic diagram of an example WL delay circuit with WL interlock circuits shown in accordance with various embodiments of the present disclosure.

Fig. 3 is a graphical diagram illustrating various input and output pulses of a WL circuit in an operating mode according to various embodiments of the disclosure.

FIG. 4 is an electrical schematic diagram of another exemplary WL delay circuit with WL interlock circuit shown in accordance with various embodiments of the present disclosure.

FIG. 5 is an electrical schematic diagram of another exemplary WL delay circuit with WL interlock circuit shown in accordance with various embodiments of the present disclosure.

FIG. 6 is an electrical schematic diagram of another exemplary WL delay circuit with WL interlock circuit shown in accordance with various embodiments of the present disclosure.

Fig. 7 is a process flow diagram illustrating a method of generating a clock pulse width signal according to various embodiments of the present disclosure.

Detailed Description

The invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Such as in the following description, forming the first component over or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper" and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

An SRAM device may be comprised of one or more SRAM cells. The SRAM cell may include a different number of transistors. The transistors may form a data latch for storing a data bit. Additional transistors may be added to control access to the transistors. The SRAM cells may be arranged in an array having rows and columns. Typically, each row of SRAM cells is connected to a Word Line (WL), which determines whether the current SRAM cell is selected. Each column of SRAM cells is connected to a Bit Line (BL) or BL pair (BL/BLB), which is used to store data bits to or read stored data bits from a selected SRAM cell.

The SRAM cell performs read and write operations. The process of storing information in an SRAM cell is referred to as "writing". The process of reading information stored on an SRAM cell is referred to as "reading". Both read and write information are transferred in square wave representation of electronic pulses of logic high (e.g., '1') and logic low (e.g., '0'). When a pulse transitions between a logic high (e.g., '1') and a logic low (e.g., '0'), it is represented as an edge of a square wave. The pulse transition from a logic high (e.g., "1") to a logic low (e.g., "0") is referred to as a falling edge. The pulse transition from a logic low (e.g., '0') to a logic high (e.g., '1') is referred to as a rising edge. The pulse width is a measure of the time between the rising and falling edges of a pulse. In this description, the terms pulse and signal may be used interchangeably.

A write operation in an SRAM requires that the bit line (BL/BLB) be turned off before the word line (WL/WLB) is turned on. In other words, the falling edge of the bit line pulse should occur before the rising edge of the WL pulse. This time is called WL margin. The WL delay circuit may control the WL margin by introducing a timing delay to modify the pulse width. The timing delay delays the time that a rising or falling edge occurs. This is used to ensure that the write operation is successful (e.g., the information is stored in the SRAM cell), i.e., the WL remains on for the amount of time required to store all the information to the SRAM cell. The write operation is also controlled by a reset signal (GCKPB). However, in some cases, the reset signal may stop the write operation before the write operation is completed, resulting in a write failure (e.g., information is not stored in the SRAM cell because it requires more time to complete). This may occur because WL latency results in a time delay for the write operation, which may occur at the same time that the reset signal is received. Such a reset would truncate or reduce the WL pulse width. The subject matter described herein uses a WL interlock circuit that modifies the write pulse width in the WL delay circuit to facilitate successful write operations.

Fig. 1 is a block diagram of an exemplary memory device 100, shown in accordance with various embodiments of the present disclosure. The memory device 100 is comprised of a number of electrical components, including a memory array 110 and a Word Line (WL) delay circuit 120, as well as a number of other components, such as those described in more detail in fig. 2. The memory array 110 includes a number of memory cells (also referred to as bit cells) 112, 114 configured to store information in the form of a logic low (e.g., '0') or a logic high (e.g., '1'). As previously described, storing this information in a bitcell is referred to as a write operation. Reading stored information from a bit cell is referred to as a read operation. WL delay circuit 120 includes WL interlock circuit 125. The WL interlock circuit 125 modifies the write pulse width in the WL delay circuit 120 to facilitate a successful write operation, as described in more detail in fig. 2.

Fig. 2 is an electrical schematic diagram of an exemplary WL delay circuit 200 with WL interlock circuit 250 shown in accordance with various embodiments of the present disclosure. WL interlock circuit 250 has two modes: a standby mode and an operating mode. In the standby mode, a read operation occurs, and WL interlock circuit 250 is not used. In the operating mode, a write operation occurs and WL interlock circuit 250 helps the write operation generate a sufficient pulse width by preventing pulse contraction. The pulse width generated using WL interlock circuit 250 is described in more detail in fig. 3. In standby mode and operating mode, the complementary Shutdown (SDB) signal is a logic high (e.g., '1'), which enables the WL delay circuit 200 to operate. When the complementary shutdown SDB signal is logic low (e.g., '0'), the WL delay circuit 200 is not operated (e.g., is shut down). Further, in the standby mode and the operation mode, the bank select signal (BSB) is logic low (e.g., '0').

WL interlock circuit 250 includes p-channel metal oxide semiconductor (PMOS) transistors 251, 252, n-channel metal oxide semiconductor (NMOS) transistors 253, 254, and logic gate 255. For ease of illustration and understanding, logic gate 255 in FIG. 2 is shown as a NAND gate. However, the logic gate 255 may be any combination of logic gates that perform a similar logic function as a NAND gate (such as an AND gate with its output connected to an inverter). In addition to WL interlock circuit 250, WL delay circuit 200 includes logic gate 201, inverters 202, 203, 204, multiplexer 205, and delay lines 206, 207. Delay lines 206, 207 further facilitate modification of the write pulse output by WL delay circuit 200 by introducing a physical delay associated with the transmission of an electrical signal over the length of delay lines 206, 207. In some embodiments, the delay lines 206, 207 are absent, but the write pulses output by the respective WL delay circuits are still implemented by the various inverters in the respective WL delay circuits. For illustration and ease of understanding, logic gate 201 is shown in fig. 2 as a NOR gate. However, the logic gate 201 may be any combination of logic gates that perform a logic function similar to a NOR gate (such as an OR gate whose output is connected to an inverter).

The logic gate 201 receives a reset signal GCKPB and a bank select signal BSB. The source/drain regions of NMOS transistor 254 and PMOS transistor 252 are connected together and generate a delay DEL signal that is input to logic gate 202. Source/drain regions may refer to sources or drains, either individually or collectively depending on the context. The delayed DEL signal output from the logic gate 201 is also the output of the WL interlock circuit 250. The other source/drain region of PMOS transistor 252 is connected to the source/drain region of PMOS transistor 251 and to the node of logic gate 201. The connection of PMOS transistor 252 to the node of logic gate 201 facilitates control of the operation of logic gate 201. The gate region of PMOS transistor 252 is connected to lock signal LOCKB output from logic gate 255. The other source/drain region of PMOS transistor 251 is connected to supply voltage VDD. The gate region of the PMOS transistor 251 is connected to the complementary write enable signal WEB. The source/drain region of NMOS transistor 253 is connected to the node of logic gate 201 to facilitate control of logic gate 201. The other source/drain region of NMOS transistor 253 is connected to ground VSS. The other source/drain region of the NMOS transistor 254 is also connected to the ground terminal VSS. The gate region of the NMOS transistor 254 is connected to the complementary write enable signal WEB. In addition to the output signal of logic gate 201, logic gate 255 receives complementary shutdown signal SDB and signal feedback from the clock pulse width CKPWRB output by inverter 204.

Inverter 202 is connected to the output of WL interlock circuit 250. The output of inverter 202 is connected to delay line 206. Delay line 206 is also connected to the input of inverter 203. Another delay line 207 is connected to the output of the inverter 203. Delay line 207 is coupled to the input of inverter 204. The output of inverter 204, i.e., clock pulse width CKPWRB, is connected to the input node of multiplexer 205. The multiplexer 205 also receives a reset signal GCKPB. The multiplexer 205 is controlled by a write enable signal (WE). The inverters 202, 203, 204 form delay loops 220 and 230 through the connection of delay lines 206, 207. In other words, the first delay loop 220 is formed by the inverters 202, 203 and the delay line 206. The second delay loop 230 is formed by the inverters 203, 204 and the delay line 207.

The active PMOS or NMOS transistor acts as a closed switch, applying a voltage from one of the source/drain regions. The non-operating PMOS or NMOS transistor acts as an open switch, with no voltage applied from one of the source/drain regions. Generally, a PMOS transistor is in an "ON" state (e.g., operating) when the voltage applied to the gate region is logic low (e.g., '0'). When the voltage applied to the gate region is logic high (e.g., '1'), the NMOS transistor is in an "ON" state (e.g., operating).

The read operation occurs when multiplexer 205 selects a logic low (e.g., '0') input. This occurs when the write enable signal (WE) is a logic low (e.g., '0'). During a read operation, WL interlock circuit 250 is in a standby mode. Logic gate 201 is not powered and is therefore disabled. The complementary Write Enable (WEB) is a logic high (e.g., '1'), which disables PMOS transistor 251 (e.g., in an "OFF" state) and NMOS transistor 254 is operated (e.g., in an "ON" state). The complementary shutdown Signal (SDB) provided to logic gate 255 is a logic high (e.g., '1'). The clock pulse width signal (CKPWRB) output from the inverter 204 is logic high (e.g., '1'), while the delay signal (DEL) is logic low (e.g., '0'). The logic gate 255 compares the complementary off Signal (SDB), the clock pulse width signal (CKPWRB), and the delay signal. For any combination of three input signals, the NAND gate outputs a logic high (e.g., '1'), unless all three input signals are logic high (e.g., '1'), then the NAND gate outputs a logic low (e.g., '0'). Thus, in standby mode, logic gate 255 outputs a complementary lock signal LOCKB that is a logic high (e.g., '1'). When the complementary lock signal LOCKB is at a logic high level (e.g., '1'), the NMOS transistor 253 is operated (e.g., in an "ON" state), and the PMOS transistor 252 is not operated (e.g., in an "OFF" state). When both NMOS transistor 253 and NMOS transistor 254 are in operation, the delay signal (DEL) is coupled to ground and thus is logic low (e.g., "0"). Inverter 202 inverts the delay signal (DEL) to a logic high (e.g., '1'), which is transmitted along delay line 206, i.e., an additional line (e.g., a physical line), to inverter 203. Delay line 206 introduces a time delay in the signal due to the distance that the signal is output from inverter 202 to inverter 203. Inverter 203 inverts a logic high signal (e.g., '1') to a logic low signal (e.g., '0'). The logic low signal (e.g., 0) is transmitted along delay line 207, i.e., an additional line (e.g., a physical line) to inverter 204. Delay line 207 introduces a time delay in the signal due to the distance that the signal is output from inverter 203 to inverter 204. Inverter 204 inverts the logic low signal (e.g., '0') back to the logic high signal (e.g., '1'). In other words, the clock pulse width signal (CKPWRB) is a logic high (e.g., '1'), which is fed back to logic gate 255, as previously described. The write enable signal (WE) in standby mode is logic low (e.g., '0'), as opposed to the complementary write enable signal (WEB). In the case where the multiplexer 205 is controlled by a logic low (e.g., '0'), the multiplexer 205 outputs a pulse signal (GCKPCB), which is a signal-reset signal (GCKPB) provided at a low level (e.g., '0') node, and is set to a logic high (e.g., '1') in a standby mode.

When multiplexer 205 selects a logic high (e.g., '1') input, a write operation occurs. This occurs when the write enable signal (WE) is logic high (e.g., '1'). During a write operation, WL interlock circuit 250 is in an operational mode. Logic gate 201 is powered by VDD in the operational mode. When the write enable signal (WE) is logic high (e.g., '1'), the complementary write enable signal (WEB) is logic low (e.g., '0'). Under a complementary write enable signal (WEB) of logic low (e.g., '0'), PMOS transistor 251 is active (e.g., in an "ON" state) and NMOS transistor 254 is inactive (e.g., in an "OFF" state). When the reset signal (GCKPB) transitions from a logic high (e.g. "1") to a logic low (e.g. "0"), the delay signal (DEL) changes from a logic low (e.g. "0") to a logic high (e.g. "1") after one logic gate 201 delays. The lock signal (LOCKB) is set to logic low (e.g., '0') after a delay of one logic gate 201. This occurs when all three inputs of logic gate 251, namely, the complementary shutdown Signal (SDB), the delay signal (DEL) and the clock pulse width signal (CKPWRB), are logic high (e.g., '1'). The locking signal (LOCKB) is a logic low level (e.g., '0') locking the operation of the WL circuit 200 until the clock pulse width signal (CKPWRB) transitions from a logic high (e.g., '1') to a logic low level (e.g., '0'). When the lock signal (LOCKB) is logic low (e.g., '0'), the NMOS transistor 253 is inactive (e.g., in an "OFF" state), which in turn disables (e.g., selectively operates) the logic gate 201. The disabling of the logic gate 201 prevents edges of the reset signal GCKPB from entering the delay loops 220, 230. The delay signal (DEL) passes through delay loops 220, 230 to generate a clock pulse width signal (CKPWRB). After the clock pulse width signal (CKPWRB) changes from logic high (e.g., '1') to logic low (e.g., '0'), the lock signal (LOCKB) is set to logic high (e.g., '1'). This is because logic gate 251 outputs a logic high (e.g., '1') for any combination of inputs that involve a logic low (e.g., '0').

The reset signal (GCKPB) resets upon a transition from a logic high (e.g., '1') to a logic low (e.g., '0') and back to a logic high (e.g., '1'). Even if the reset signal (GCKPB) is reset, the clock pulse width signal (CKPWRB) does not instantaneously change from logic high (e.g., '1') to logic low (e.g., '0') because of the delay loops 220, 230. The delay signal (DEL) changes from logic high (e.g., '1') to logic low (e.g., '0') after a delay of one logic gate 201, and then the lock signal (LOCKB) is set to logic high (e.g., '1') in view of the signal propagation of the delay signal DEL while still in the delay loops 220, 230.

WL interlock circuit 250 waits for lock signal LOCKB to go logic high (e.g., '1') to allow the reset signal (GCKPB) to propagate through the remainder of WL delay circuit 200. As described above, the lock signal LOCKB output from the logic gate 251 is logic high only when all of the input-delay signal (DEL), the complementary off Signal (SDB), and the clock pulse width signal (CKPWRB) are logic high (e.g., '1'). The wait of WL interlock circuit 250 reduces the need to maintain WL pulse width while protecting the WL pulse width of the pulse (GCKPCB) output by multiplexer 205. The WL pulse width is at a maximum in view of its function of the reset signal (GCKPB) pulse width and the write path delay introduced by the delay loops 220, 230. Furthermore, for large memory instances, the write active power is reduced by more than about 6% -7%.

Fig. 3 is a diagram 300 of various input and output pulses of WL circuit 200 in an operational mode, shown in accordance with various embodiments of the present disclosure. Line graph 310 shows the reset signal (GCKPB) input to logic gate 201 and multiplexer 205. Line graph 320 shows the clock pulse width signal (CKPWRB) if the delay introduced by the delay loops 230, 240 is greater than the pulse width of the reset signal (GCKPB). Line graph 330 shows the clock pulse width signal (CKPWRB) if the delay introduced by the delay loops 230, 240 is less than the pulse width of the reset signal (GCKPB). As shown in the graphs 320, 330, even if the rising edge of the reset signal (GCKPB) arrives before the delay is completed, the pulse width of the clock pulse width signal (CKPWRB) remains unchanged and does not shrink as emphasized by the line 312 of fig. 3. This in turn facilitates successful write operations by avoiding failures.

Fig. 4 is an electrical schematic diagram of another example WL delay circuit 400 with WL interlock circuit 250 shown in accordance with various embodiments of the present disclosure. WL delay circuit 400 is similar in operation and construction to WL delay circuit 200 except that WL delay circuit 400 includes delay loops 420, 430 that do not include delay lines. In other words, delay loop 420 is formed by inverters 202, 203 and delay loop 430 is formed by inverters 203, 204. Delay loop 420 does not include delay line 206 and delay loop 430 does not include delay line 207. All other components and functions described in fig. 2 remain unchanged.

Fig. 5 is an electrical schematic diagram of a WL delay circuit 500 with another example of a WL interlock circuit 250 shown in accordance with various embodiments of the present disclosure. WL delay circuit 500 is similar in operation and construction to WL delay circuit 200 except that WL delay circuit 500 includes delay loops 520, 530, only one of which includes delay line 206. In other words, delay loop 520 is formed by inverters 202, 203 and delay loop 530 is formed by inverters 203, 204. Delay loop 520 does include delay line 206. However, delay loop 530 does not include delay line 207. All other components and functions described in fig. 2 remain unchanged.

Fig. 6 is an electrical schematic diagram of another example WL delay circuit 600 with WL interlock circuit 250 shown in accordance with various embodiments of the present disclosure. WL delay circuit 500 is similar in operation and construction to WL delay circuit 200 except that WL delay circuit 600 includes delay loops 620, 630, with only one delay loop including delay line 207. In other words, the delay loop 620 is formed by the inverters 202, 203 and the delay loop 630 is formed by the inverters 203, 204. Delay loop 620 does not include delay line 206. However, delay loop 630 does include delay line 207. All other components and functions described in fig. 2 remain unchanged.

Fig. 7 is a process flow diagram 700 illustrating a method of generating a clock pulse width signal according to various embodiments of the present disclosure. Although fig. 7 is described herein with reference to the previously described structures for ease of understanding, it will be appreciated that the method is applicable to many other structures as well. At step 710, the interlock circuit 250 selectively operates the first logic gate 201 by preventing the changing edges of the reset signal from being transferred to the delay circuit (e.g., delay loops 220, 230). In step 720, a delay circuit (e.g., delay loops 220, 230) generates a clock pulse width signal (CKPWRB) based on a delayed version of the first signal (e.g., delay signal DEL) output by the interlock circuit 250. At step 730, a clock pulse width signal (CKPWRB) is provided to the interlock circuit 250 (e.g., to the logic gate 251) through a feedback loop (e.g., from the output of the logic gate 204 to the input of the logic gate 255) for future signal delays.

Numerous advantages may be provided using the various systems, circuits, and methods described herein. For example, using the subject matter described herein may provide sufficient write pulse width for a write operation of an SRAM cell by preventing pulse shrinking. Furthermore, using WL interlock circuitry may help reduce the write active power of large memory instances.

In one embodiment, a device includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate is configured to receive a reset signal. An interlock circuit is connected to the output of the first logic gate. The interlock circuit is configured to generate a first signal and selectively operate the first logic gate. The delay circuit is connected with the output end of the interlocking circuit. The delay circuit is configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit. The selective operation of the first logic gate prevents a changing edge of the reset signal from being transferred to the delay circuit in response to the reset signal changing logic state.

In some embodiments, since the operation of the first logic gate is temporarily suspended, the pulse width of the clock pulse width signal is maintained independent of the reset signal.

In some embodiments, the clock pulse width signal is provided to a word line of the memory device in response to the write enable signal being in a high logic state.

In some embodiments, changing the logic state of the reset signal includes changing from a high logic state to a low logic state.

In some embodiments, the delay circuit includes a first delay loop including a first inverter and a second inverter connected in series, and a second delay loop connected to an output of the first delay loop, the second delay loop including the second inverter and a third inverter connected in series.

In some embodiments, a first delay line is disposed between the first inverter and the second inverter, and a second delay line is disposed between the second inverter and the third inverter.

In some embodiments, a first delay line is disposed between the first inverter and the second inverter or between the second inverter and the third inverter.

In some embodiments, the interlock circuit comprises: a first transistor comprising a first gate region, a first source/drain region, and a second source/drain region, wherein the first transistor is configured to receive a complementary write enable signal at the first gate region and a supply voltage at the first source/drain region, wherein the second source/drain region is connected to a first node of the first logic gate; a second transistor including a second gate region, a third source/drain region, and a fourth source/drain region, wherein the third source/drain region of the second transistor is connected to the second source/drain region of the first transistor, the fourth source/drain region is connected to an output of the first logic gate, and the second transistor is configured to receive a lock signal at the second gate region; a third transistor including a third gate region, a fifth source/drain region, and a sixth source/drain region, wherein the third gate region of the third transistor is connected to the latch signal, the fifth source/drain region is connected to the first logic gate at a second node, and the sixth source/drain region is connected to a ground terminal; a fourth transistor including a fourth gate region, a seventh source/drain region, and an eighth source/drain region, wherein the fourth transistor is configured to receive the complementary write enable signal at the fourth gate region, and the seventh source/drain region is connected to an output terminal of the first logic gate, and the eighth source/drain region is connected to a ground terminal; and a second logic gate connected to the second transistor and the third transistor, the second logic gate configured to compare the first signal, the off signal, and the clock width pulse signal to generate the lock signal.

In some embodiments, the second logic gate is a NAND gate and the first logic gate is a NOR gate.

In some embodiments, the device further comprises: a multiplexer connected to an output of the third inverter and configured to receive the reset signal, wherein the multiplexer is configured to output the clock pulse width signal or the reset signal according to the write enable signal.

In another embodiment, a method of generating a clock pulse width signal includes selectively operating a first logic gate by an interlock circuit to prevent a varying edge of a reset signal from being transferred to a delay circuit. The delay circuit generates a clock pulse width signal according to the delayed version of the first signal output by the interlock circuit. The clock pulse width signal is provided to the interlock circuit through a feedback loop for future signal delays.

In some embodiments, since the operation of the first logic gate is temporarily suspended, the pulse width of the first pulse signal is maintained independent of the reset signal.

In some embodiments, the method further comprises: the clock pulse width signal is provided to a word line of the memory device through the multiplexer in response to the write enable signal being in a high logic state.

In some embodiments, changing the logic state of the reset signal includes changing from a high logic state to a low logic state.

In some embodiments, the delay circuit includes a first delay loop including a first inverter and a second inverter connected together in series, and a second delay loop connected to an output of the first delay loop, the second delay loop including the second inverter and a third inverter connected in series.

In some embodiments, a first delay line is disposed between the first inverter and the second inverter, and a second delay line is disposed between the second inverter and the third inverter.

In some embodiments, a first delay line is disposed between the first inverter and the second inverter or between the second inverter and the third inverter.

In some embodiments, the method further comprises: receiving, by a first transistor comprising a first gate region, a first source/drain region, and a second source/drain region, a complementary write enable signal at the first gate region, and a supply voltage at the first source/drain region, wherein the second source/drain region is connected to a first node of the first logic gate; receiving a latch signal at a second gate region by a second transistor comprising the second gate region, a third source/drain region and a fourth source/drain region, wherein the third source/drain region of the second transistor is connected to a second source/drain region of the first transistor, the fourth source/drain region is connected to an output of the first logic gate; selectively operating by the second transistor or a third transistor comprising a third gate region, a fifth source/drain region and a sixth source/drain region, wherein the third gate region of the third transistor is connected to the latch signal and the fifth source/drain region is connected to the first logic gate at a second node and the sixth source/drain region is connected to ground; receiving the complementary write enable signal at a fourth gate region by a fourth transistor comprising a fourth gate region, a seventh source/drain region and an eighth source/drain region, wherein the seventh source/drain region is connected to an output of the first logic gate and the eighth source/drain region is connected to ground; and comparing the first signal, the off signal, and the clock width pulse signal through a second logic gate connected to the second transistor and the third transistor to generate a lock signal.

In some embodiments, the second logic gate is a NAND gate and the first logic gate is a NOR gate.

In another embodiment, a system includes an SRAM device and a wordline driver circuit. The SRAM device includes a plurality of cells connected together by word lines. The SRAM device is configured to perform a write operation to store information in one or more cells of the plurality of cells. The word line driving circuit includes an interlock circuit and a delay circuit. The interlock circuit is configured to generate an interlock signal and selectively operate the logic gate to prevent a varying edge of the reset signal from being transferred to the delay circuit. The delay circuit is connected to an output of the interlock circuit and is configured to generate a clock pulse width signal based on the interlock signal, the clock pulse width signal being fed back to the interlock circuit and provided to the word line to facilitate a write operation.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A device for a word line delay interlock circuit, comprising:

a first logic gate configured to receive a reset signal;

an interlock circuit connected to an output of the first logic gate, the interlock circuit configured to generate a first signal and selectively operate the first logic gate; and

a delay circuit connected to an output of the interlock circuit, the delay circuit configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit,

wherein, responsive to the reset signal changing logic state, selective operation of the first logic gate prevents a changing edge of the reset signal from being transferred to the delay circuit.

2. The device of claim 1, wherein a pulse width of the clock pulse width signal is maintained independent of the reset signal as a result of operation of the first logic gate being temporarily suspended.

3. The device of claim 1, wherein the clock pulse width signal is provided to a word line of the memory device in response to the write enable signal being in a high logic state.

4. The device of claim 1, wherein changing the logic state of the reset signal comprises changing from a high logic state to a low logic state.

5. The device of claim 1, wherein the delay circuit comprises a first delay loop comprising a first inverter and a second inverter connected in series, and a second delay loop connected to an output of the first delay loop, the second delay loop comprising the second inverter and a third inverter connected in series.

6. The device of claim 5, wherein a first delay line is disposed between the first inverter and the second inverter, and a second delay line is disposed between the second inverter and the third inverter.

7. The device of claim 5, wherein a first delay line is disposed between the first inverter and the second inverter or between the second inverter and the third inverter.

8. A method of generating a clock pulse width signal, the method comprising:

selectively operating the first logic gate by the interlock circuit to prevent a changing edge of the reset signal from being transferred to the delay circuit;

generating, by the delay circuit, a clock pulse width signal based on a delayed version of the first signal output by the interlock circuit; and

the clock pulse width signal is provided to the interlock circuit through a feedback loop for future signal delays.

9. The method of claim 8, wherein a pulse width of the first pulse signal is maintained independent of the reset signal as an operation of the first logic gate is temporarily suspended.

10. A system for a word line delay interlock circuit, comprising:

a Static Random Access Memory (SRAM) device comprising a plurality of cells connected together by word lines, the SRAM device configured to perform a write operation to store information in one or more of the plurality of cells; and

a word line driving circuit comprising:

an interlock circuit configured to generate an interlock signal and selectively operate the logic gate to prevent a changed edge of the reset signal from being transferred to the delay circuit; and

the delay circuit is connected to an output terminal of the interlock circuit, and is configured to generate a clock pulse width signal according to the interlock signal, the clock pulse width signal being fed back to the interlock circuit and supplied to the word line to promote the write operation.