KR100452041B1 - Method for forming copper wire in a semiconductor device - Google Patents
Method for forming copper wire in a semiconductor device Download PDFInfo
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- KR100452041B1 KR100452041B1 KR10-2002-0085480A KR20020085480A KR100452041B1 KR 100452041 B1 KR100452041 B1 KR 100452041B1 KR 20020085480 A KR20020085480 A KR 20020085480A KR 100452041 B1 KR100452041 B1 KR 100452041B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 소자의 구리배선 형성 방법에 관한 것으로, 구리배선을 형성한 후 1차 플라즈마 처리를 통해 구리배선의 표면에 형성된 구리산화층을 제거하는 동시에 화합물층을 형성한다. 그리고 표면에 실리콘을 흡착시킨 상태에서 2차 플라즈마 처리를 실시하여 구리배선과 연마 정지층의 표면에 화합물층을 형성한다. 상기와 같이 형성된 화합물층에 의해 계면을 통한 구리(Cu) 원자의 이동이나 스트레스 이동이 억제되어 구리배선의 신뢰성이 향상된다. 또한, 구리배선과 연마 정지층 표면의 계면 상태가 양호해져 확산 방지 절연막과의 접합성이 증대된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper wiring in a semiconductor device, and after forming copper wiring, a copper oxide layer formed on the surface of the copper wiring is removed through primary plasma treatment to form a compound layer. The secondary plasma treatment is performed while silicon is adsorbed on the surface to form a compound layer on the surface of the copper wiring and the polishing stop layer. The compound layer formed as described above suppresses the movement of copper (Cu) atoms and stress movement through the interface, thereby improving the reliability of the copper wiring. In addition, the interface state between the copper wiring and the surface of the polishing stop layer becomes good, and the bonding property with the diffusion barrier insulating film is increased.
Description
본 발명은 다마신(Damascene) 공정을 이용한 다층 구조의 구리배선 형성 방법에 관한 것으로, 더욱 상세하게는 구리(Cu) 원자의 이동에 의한 배선의 신뢰성 저하를 방지할 수 있도록 한 구리배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a copper wiring having a multi-layer structure using a damascene process, and more particularly, to a method for forming a copper wiring that can prevent a decrease in reliability of wiring due to movement of copper (Cu) atoms. It is about.
종래에는 도 1a에 도시된 바와 같이, 소정의 공정을 거친 실리콘 기판(1) 상에 하부 저유전 절연막(2)이 형성된 상태에서 하부 저유전 절연막(2) 상에 연마 정지층(3)을 형성한다. 연마 정지층(3)과 하부 저유전 절연막(2)을 패터닝하여 소정 깊이의 비아홀 및 트렌치를 형성하고, 전체 상부면에 확산 방지 금속막(4) 및 구리박막(5)을 순차적으로 형성한다. 연마 정지층(3) 상에 증착된 구리박막(5) 및 확산 방지 금속막(4)을 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정으로 제거하여 트렌치 내에 확산 방지 금속막(4)에 의해 둘려 쌓여진 구리배선(5)을 형성한다.In the related art, as shown in FIG. 1A, the polishing stop layer 3 is formed on the lower low dielectric insulating film 2 while the lower low dielectric insulating film 2 is formed on the silicon substrate 1 that has undergone a predetermined process. do. The polishing stop layer 3 and the lower low dielectric insulating film 2 are patterned to form via holes and trenches having a predetermined depth, and the diffusion preventing metal film 4 and the copper thin film 5 are sequentially formed on the entire upper surface. The copper thin film 5 and the anti-diffusion metal film 4 deposited on the polishing stop layer 3 are removed by a chemical mechanical polishing (CMP) process and surrounded by the anti-diffusion metal film 4 in the trench. The stacked copper wirings 5 are formed.
도 1b에 도시된 바와 같이, 플라즈마 처리를 실시하여 노출된 구리배선(5)의 표면에 형성된 구리산화층을 제거하고, 전체 상부면에 확산 방지 절연막(6) 및 상부 저유전 절연막(7)을 순차적으로 형성한다. 이 후 상부 저유전 절연막(7)을 패터닝하여 소정 깊이의 트렌치를 형성하고 상기와 같은 다마신 공정을 통해 상부 구리배선(도시되지 않음)을 형성한다.As shown in FIG. 1B, the copper oxide layer formed on the surface of the exposed copper wiring 5 is removed by performing a plasma treatment, and the diffusion barrier insulating film 6 and the upper low dielectric insulating film 7 are sequentially disposed on the entire upper surface. To form. Thereafter, the upper low dielectric insulating film 7 is patterned to form trenches having a predetermined depth, and an upper copper wiring (not shown) is formed through the damascene process as described above.
그런데 상기와 같이 다마신 공정을 이용하여 다층 구조의 구리배선을 형성하면 구리배선(5)의 상부 및 하부에서 확산 방지 금속막(4)과 확산 방지 절연막(6)사이의 계면을 통한 구리(Cu) 원자의 이동(Electro migration; EM)이나 스트레스 이동(Stress migration; SM)이 발생되어 배선의 신뢰성이 저하된다. 또한, 구리배선(5)과 연마 정지층(3) 표면의 계면 상태가 불량하여 절연막(6 및 7)과의 접합성이 낮아지고, 이에 따라 소자의 전기적 특성이 저하된다.However, when the copper wiring of the multi-layer structure is formed using the damascene process as described above, the copper (Cu) through the interface between the diffusion preventing metal film 4 and the diffusion preventing insulating film 6 is formed on the upper and lower portions of the copper wiring 5. ) Atom migration (EM) or stress migration (SM) occurs, which reduces the reliability of the wiring. In addition, the interface state between the copper wiring 5 and the surface of the polishing stop layer 3 is poor, and thus the bonding property between the insulating films 6 and 7 is lowered, thereby lowering the electrical characteristics of the device.
따라서 본 발명은 구리배선을 형성한 후 플라즈마를 이용한 표면처리 및실리콘 흡착을 위한 표면처리를 실시함으로써 상기한 단점을 해소할 수 있는 반도체 소자의 구리배선 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device which can solve the above-mentioned disadvantages by forming a copper wiring and then performing a surface treatment using plasma and a surface treatment for silicon adsorption.
상기한 목적을 달성하기 위한 본 발명은 소정의 공정을 거친 실리콘 기판 상에 하부 저유전 절연막이 형성된 상태에서 상기 하부 저유전 절연막 상에 연마 정지층을 형성하는 단계와, 상기 연마 정지층과 하부 저유전 절연막을 패터닝하여 소정 깊이의 트렌치를 형성하는 단계와, 상기 트렌치 내에 확산 방지 금속막에 의해 둘려 쌓여진 구리배선을 형성하는 단계와, 상기 구리배선의 표면에 형성된 산화층을 제거하고 표면에 구리가 함유된 화합물층이 형성되도록 1차 플라즈마 처리하는 단계와, 실리콘이 함유된 가스를 이용하여 전체 표면에 실리콘을 흡착시키는 단계와, 상기 실리콘이 흡착된 화합물층 및 연마 정지층의 표면에 화합물층이 형성되도록 2차 플라즈마 처리하는 단계와, 전체 상부면에 확산 방지 절연막 및 상부 저유전 절연막을 순차적으로 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a polishing stop layer on the lower low dielectric insulating film in a state where the lower low dielectric insulating film is formed on a silicon substrate subjected to a predetermined process, the polishing stop layer and the lower low Patterning a dielectric insulating film to form a trench having a predetermined depth, forming a copper wiring surrounded by a diffusion preventing metal film in the trench, removing an oxide layer formed on the surface of the copper wiring and containing copper on the surface Performing a first plasma treatment to form a compound layer, adsorbing silicon to the entire surface by using a gas containing silicon, and forming a compound layer on the surface of the compound-adsorbed compound and the polishing stop layer. Plasma treatment and sequentially spreading the diffusion barrier insulating film and the upper low dielectric insulating film on the entire upper surface In that it comprises a step of forming a features.
상기 하부 및 상부 저유전 절연막은 탄소를 함유하거나 저밀도의 유기 또는무기 계열의 막으로 이루어지며, 3000 내지 10000Å의 두께로 형성된 것을 특징으로 한다.The lower and upper low dielectric insulating films may be formed of an organic or inorganic series film containing carbon or having a low density, and formed to a thickness of 3000 to 10000 kPa.
상기 연마 정지층은 탄소를 함유하지 않는 산화막, 질소를 함유한 실리콘 질화막이나 실리콘 질화산화막 또는 탄소를 함유한 실리콘 카바이드 계열의 막인 것을 것을 특징으로 한다.The polishing stop layer is characterized in that it is an oxide film containing no carbon, a silicon nitride film containing nitrogen, a silicon nitride oxide film or a silicon carbide film containing carbon.
상기 구리배선은 상기 트렌치를 포함하는 전체 상부면에 상기 확산 방지 금속막 및 구리박막을 순차적으로 증착하는 단계와, 화학적기계적연마 공정으로 상기 연마 정지층 상에 증착된 구리박막 및 확산 방지 금속막을 제거하는 단계를 통해 형성된 것을 특징으로 한다.The copper wiring may sequentially deposit the diffusion preventing metal film and the copper thin film on the entire upper surface including the trench, and remove the copper thin film and the diffusion preventing metal film deposited on the polishing stop layer by a chemical mechanical polishing process. Characterized in that formed through the step.
상기 1차 및 2차 플라즈마 처리에 이용되는 플라즈마는 질소 및 수소가 함유된 가스 또는 암모니아 계열의 가스를 이용하여 생성하며, 상기 1차 및 2차 플라즈마 처리는 100 내지 350℃ 또는 -50 내지 50℃의 온도에서 실시하는 것을 특징으로 한다.The plasma used for the primary and secondary plasma treatment is generated using a gas containing nitrogen and hydrogen or an ammonia-based gas, and the primary and secondary plasma treatments are 100 to 350 ° C or -50 to 50 ° C. Characterized in that carried out at a temperature of.
상기 화합물층은 CuNx, SiOxNy 또는 SiOCNx 형태이며, 상기 실리콘이 함유된 가스는 SiH4계열의 가스, TEOS 가스 또는 메칠이나 에칠을 함유한 실리콘 가스인 것을 특징으로 한다.The compound layer is in the form of CuNx, SiOxNy or SiOCNx, the gas containing silicon is characterized in that the SiH 4 series gas, TEOS gas or silicon gas containing methyl or ethyl.
도 1a 및 도 1b는 종래 반도체 소자의 구리배선 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a copper wiring of a conventional semiconductor device.
도 2a 및 도 2b는 본 발명에 따른 반도체 소자의 구리배선 형성 방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of devices for explaining a method for forming copper wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11: 실리콘 기판1, 11: silicon substrate
2, 12: 하부 저유전 절연막2, 12: lower low dielectric insulating film
3, 13: 연마 정지층3, 13: polishing stop layer
4, 14: 확산 방지 금속막4, 14: diffusion preventing metal film
5, 15: 구리배선5, 15: copper wiring
6, 18: 확산 방지 절연막6, 18: diffusion barrier insulating film
7, 19: 상부 저유전 절연막7, 19: upper low dielectric insulating film
16, 17: 화합물층16, 17: compound layer
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
도 2a 및 도 2b는 본 발명에 따른 반도체 소자의 구리배선 형성 방법을 설명하기 위한 소자의 단면도이다.2A and 2B are cross-sectional views of devices for explaining a method of forming copper wirings of a semiconductor device according to the present invention.
도 2a를 참조하면, 소정의 공정을 거친 실리콘 기판(11) 상에 하부 저유전 절연막(12)이 형성된 상태에서 하부 저유전 절연막(12) 상에 연마 정지층(13)을 형성한다. 하부 저유전 절연막(12)은 탄소를 함유하거나 저밀도의 유기 또는 무기 계열의 막을 스핀 온(Spin on) 방식으로 도포하거나 화학기상증착법(CVD)으로 증착하여 형성하며 3000 내지 10000Å의 두께로 형성한다.Referring to FIG. 2A, the polishing stop layer 13 is formed on the lower low dielectric insulating film 12 in a state where the lower low dielectric insulating film 12 is formed on the silicon substrate 11 that has undergone a predetermined process. The lower low-k dielectric layer 12 is formed by applying a carbon-containing or low-density organic or inorganic-based film by spin on or depositing by chemical vapor deposition (CVD) and having a thickness of 3000 to 10000 kPa.
연마 정지층(13)과 하부 저유전 절연막(12)을 패터닝하여 단차가 높은 소정 깊이의 비아 및 트렌치를 형성하고, 전체 상부면에 확산 방지 금속막(14) 및 구리박막(15)을 순차적으로 형성한다. 연마 정지층(13) 상에 증착된 구리박막(15) 및 확산 방지 금속막(14)을 화학적기계적연마(CMP) 공정으로 제거하여 트렌치 내에 확산 방지 금속막(14)에 의해 둘려 쌓여진 구리배선(15)을 형성한다. 연마 정지층(13)은 탄소를 함유하지 않는 산화막, 질소를 함유한 실리콘 질화막이나 실리콘 질화산화막 또는 탄소를 함유한 실리콘 카바이드 계열의 막으로 형성한다. 화학적기계적연마(CMP) 공정은 연마 정지층(13)이 일정 두께 잔류되거나 또는 모두 제거될 때까지 실시한다.The polishing stop layer 13 and the lower low dielectric insulating film 12 are patterned to form vias and trenches having a predetermined depth with high steps, and the diffusion preventing metal film 14 and the copper thin film 15 are sequentially formed on the entire upper surface. Form. The copper thin film 15 and the anti-diffusion metal film 14 deposited on the polishing stop layer 13 are removed by a chemical mechanical polishing (CMP) process to enclose the copper wiring enclosed by the anti-diffusion metal film 14 in the trench ( 15). The polishing stop layer 13 is formed of an oxide film containing no carbon, a silicon nitride film containing nitrogen, a silicon nitride oxide film or a silicon carbide film containing carbon. The chemical mechanical polishing (CMP) process is performed until the polishing stop layer 13 remains or is removed to a certain thickness.
구리배선(15)의 표면에 형성된 구리산화층을 제거하고 노출된 구리배선(15)의 표면에 매우 얇은 두께의 구리가 함유된 화합물층(16)이 형성되도록 100 내지 350℃의 온도에서 1차 플라즈마 처리를 실시한다. 이 때 플라즈마는 질소 및 수소가 함유된 가스 또는 암모니아 계열의 가스를 이용하여 생성한다. 이와 같은 플라즈마 처리를 통해 CuNx 등과 같은 형태의 중간 화합물층(16)이 형성되며, 후속 공정에서 산소나 실리콘 등의 확산에 의한 CuSix 등의 형성이 방지된다. 이 때 결함(Defect)의 발생이 효과적으로 방지되도록 플라즈마 처리를 -50 내지 50℃의 저온에서 실시할 수도 있다.The first plasma treatment is performed at a temperature of 100 to 350 ° C. to remove the copper oxide layer formed on the surface of the copper wiring 15 and to form a compound layer 16 containing very thin copper on the surface of the exposed copper wiring 15. Is carried out. At this time, the plasma is generated using a gas containing nitrogen and hydrogen or an ammonia-based gas. Through such a plasma treatment, an intermediate compound layer 16 having a form such as CuNx is formed, and formation of CuSix or the like by diffusion of oxygen or silicon is prevented in a subsequent process. At this time, the plasma treatment may be performed at a low temperature of -50 to 50 ° C so as to effectively prevent the occurrence of defects.
100 내지 450℃의 온도에서 실리콘(Si)이 함유된 가스 예를 들어, SiH4계열의 가스, TEOS 가스 또는 메칠이나 에칠을 함유한 실리콘 가스를 이용한 표면처리를 통해 화합물층(16) 및 연마 정지층(13)의 표면에 실리콘(Si)이 흡착되도록 한다.Compound layer 16 and polishing stop layer by surface treatment using a gas containing silicon (Si) at a temperature of 100 to 450 ° C., for example, SiH 4 series gas, TEOS gas or silicon gas containing methyl or ethyl. Silicon (Si) is adsorbed on the surface of (13).
도 2b를 참조하면, 실리콘(Si)이 흡착된 화합물층(16) 및 연마 정지층(13)의 표면에 얇은 두께의 화합물층(17)이 형성되도록 100 내지 350℃의 온도에서 2차 플라즈마 처리를 실시한다. 이 때 플라즈마는 질소 및 수소가 혼합된 가스 또는 암모니아 계열의 가스를 이용하여 생성하며, 2차 플라즈마 처리를 통해 SiOxNy 또는 SiOCNx 형태의 화합물층(17)이 20㎚ 이하의 두께로 형성된다.Referring to FIG. 2B, a secondary plasma treatment is performed at a temperature of 100 to 350 ° C. to form a thin compound layer 17 on the surfaces of the compound layer 16 and the polishing stop layer 13 on which silicon (Si) is adsorbed. do. At this time, the plasma is generated by using a mixture of nitrogen and hydrogen, or ammonia-based gas, and the second layer is used to form a compound layer 17 having a SiOxNy or SiOCNx form having a thickness of 20 nm or less.
상기와 같이 화합물층(17)이 형성되면 연속적으로 전체 상부면에 확산 방지 절연막(18) 및 상부 저유전 절연막(19)을 순차적으로 형성한다. 확산 방지 절연막(18)은 실리콘 질화막이나 SiCx 계열의 막으로 형성하며, 같은 장비에서 연속적으로 형성하여 하부 절연막과 상부 절연막과의 접합성이 증대되도록 한다. 상부 저유전 절연막(19)은 탄소를 함유하거나 저밀도의 유기 또는 무기 계열의 막을스핀 온 방식이나 도포하거나 화학기상증착법(CVD)으로 증착하여 형성하며 3000 내지 10000Å의 두께로 형성한다.When the compound layer 17 is formed as described above, the diffusion barrier insulating film 18 and the upper low dielectric insulating film 19 are sequentially formed on the entire upper surface thereof. The diffusion barrier insulating film 18 is formed of a silicon nitride film or a SiCx-based film, and is continuously formed in the same equipment to increase the adhesion between the lower insulating film and the upper insulating film. The upper low dielectric insulating film 19 is formed by coating a carbon-containing or low-density organic or inorganic-based film by spin-on or coating, or by chemical vapor deposition (CVD), and has a thickness of 3000 to 10000 kPa.
본 발명에 따른 1차 및 2차 플라즈마 처리는 구리배선(15)에 힐록(Hillock)과 같은 결함이 발생되지 않도록 10초 이하의 시간동안 실시하는 것이 바람직하다. 1차 및 2차 플라즈마 처리를 통해 형성된 화합물층(16 및 17)은 구리배선(15) 상부 및 하부에서 연마 정지층(13), 확산 방지 절연막(16) 및 상부 절연막(18) 사이의 계면을 통한 구리(Cu) 원자의 이동이나 스트레스 이동을 억제시켜 구리배선의 신뢰성이 향상되도록 한다. 또한, 구리배선(15)과 연마 정지층(13) 표면의 계면 상태를 양호하게 만들어 확산 방지 절연막(18)과의 접합성을 증대시킨다.The primary and secondary plasma treatment according to the present invention is preferably carried out for a time of 10 seconds or less so that a defect such as Hilllock (Hillock) does not occur in the copper wiring 15. The compound layers 16 and 17 formed through the primary and secondary plasma treatments are formed through the interface between the polishing stop layer 13, the diffusion barrier insulating film 16, and the upper insulating film 18 above and below the copper wiring 15. By suppressing the movement of copper (Cu) atoms or stress movement to improve the reliability of the copper wiring. In addition, the interface between the copper wiring 15 and the surface of the polishing stop layer 13 is made good, thereby increasing the bonding property with the diffusion preventing insulating film 18.
본 발명은 콘택홀이 포함되는 다층 구조의 구리배선 형성 공정 뿐만 아니라 다마신 공정으로 배선을 형성하는 공정에 적용이 가능하다.The present invention can be applied to a process of forming a wiring by a damascene process as well as a process of forming a copper wiring of a multilayer structure including a contact hole.
상술한 바와 같이 본 발명은 구리배선을 형성한 후 1차 플라즈마 처리를 통해 구리배선의 표면에 형성된 구리산화층을 제거하는 동시에 화합물층을 형성한다. 그리고 표면에 실리콘을 흡착시킨 상태에서 2차 플라즈마 처리를 실시하여 구리배선과 연마 정지층의 표면에 화합물층을 형성한다. 상기와 같이 형성된 화합물층에 의해 계면을 통한 구리(Cu) 원자의 이동이나 스트레스 이동이 억제되어 구리배선의 신뢰성이 향상된다. 또한, 구리배선과 연마 정지층 표면의 계면 상태가 양호해져 확산 방지 절연막과의 접합성이 증대된다.As described above, the present invention removes the copper oxide layer formed on the surface of the copper wiring through the first plasma treatment after the copper wiring is formed to form a compound layer. The secondary plasma treatment is performed while silicon is adsorbed on the surface to form a compound layer on the surface of the copper wiring and the polishing stop layer. The compound layer formed as described above suppresses the movement of copper (Cu) atoms and stress movement through the interface, thereby improving the reliability of the copper wiring. In addition, the interface state between the copper wiring and the surface of the polishing stop layer becomes good, and the bonding property with the diffusion barrier insulating film is increased.
Claims (8)
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