KR100450403B1 - High Speed Backplane in Switch Network System - Google Patents

Abstract

The present invention efficiently arranges switches and line cards in the backplane using hard metric connectors, and allocates signal lines of all ports concentrated to the switches to the connectors with a relatively high signal-to-ground ratio, thereby increasing switch port density and increasing the distance between data transmission lines. It relates to a high speed backplane of a system in which a sufficiently maintained switch with less crosstalk and loss is used. The present invention provides a high speed backplane of a system in which a switch for serial data transmission is provided by providing a connection of a switch board and a line card having pins of a 5 + 2 row connector, respectively. Assign the middle pin of the pin to the ground pin and assign two pins to each of the ground pins as differential signal pins to configure the corresponding line as one port, and connect one line between each port to the ground pin. By assigning connector pins of the switch board and line card ports, respectively, to maintain a signal-to-ground ratio of 1: 1.5. In addition, the present invention, while connecting the ports of the two switchboards with the ports of the left and right symmetrical line card, the ports of the switchboard in order from the top to the bottom of the left and right line card alternately symmetrically Connect with

Description

High Speed Backplane in Switch Network System

The present invention relates to a backplane of a switch system having a plurality of ports, and more particularly, to efficiently arrange switches and line cards in a backplane using a hard metric connector and to provide signal to ground ratios for signal lines of all ports concentrated at the switch. It is related to a high speed backplane of a system in which switches are allocated to a high connector to increase switch port density and maintain sufficient data transmission line spacing, so that switches with low crosstalk and loss are used.

In order to meet the demand for high-speed services, the interconnection of various boards for implementing a large-scale system is generally made of a back-plane. To prevent crosstalk between signal lines on the backplane, the spacing between signal lines must be wide enough and the signal line assignment pins of the connector must be shielded by the ground pins. However, if the signal pin of such a connector is surrounded by a ground pin and the signal-to-ground ratio is 1: 2 or more, the pin utilization is lowered and the physical volume of the system increases due to the expansion of the number of ports of the switch system in order to sufficiently maintain the gap between signal lines. There is.

As described above, in the conventional backplane, data transmission of each port is connected by a parallel bus, and the density of the line in the backplane is high, and pins are required for signal line allocation, which makes it difficult to expand the number of ports and miniaturize the system. Since the bus width of the parallel bus needs to be increased in order to increase the size, the inconvenience and waste of switching both the backplane, the switch, and the line card were required in order to switch to a high-capacity, high-speed system. In addition, in case of serial data transmission, multiple ground pins are used to prevent crosstalk between signal lines, and slots for other cards are not placed on the printed circuit board where the lines pass to facilitate the arrangement of the lines connecting the ports. There was a drawback that the system became too large because it was left blank.

Meanwhile, various methods of allocating or arranging pins of a backplane connector are disclosed. As an example, Korea Patent Application No. 1998-17909 uses an 8 + 2 row connector, but the maximum pin utilization is good, the impedance can be matched around 50Ω, and the reinforced hard is arranged with pins to minimize connector crosstalk. A high speed signal pin of a connector having a metric lattice spacing is disclosed. The 5 + 2 row connector is coupled to the high-speed signal pin of a predetermined position on the backplane to surround the ground pin, and the remaining high speed signal pin and the remaining ground pins of one side of the 5 + 2 row connector are arranged in a predetermined shape. The high-speed single-ended signal line between the boards is formed through the medium. However, the signal pin is difficult to match at an impedance of more than 50 Ω and does not provide a giga-class signal pin, and the pin use efficiency is improved, but a large-capacity small switch system is not realized.

In addition, Korean Patent Application No. 1997-64489 discloses a pin assignment method for reducing crosstalk noise in a backplane connector having a large number of input / output signal lines. The method solves the ground bounce problem and reduces noise crosstalk by dividing the input / output signal groups by dividing them, separating them by ground, and separating the input / output signal groups having different attributes by ground, respectively.

In addition, Korean Patent Application No. 1999-48522 discloses a MIPS backplane using a 10/100/1000 Mbps Ethernet switch to enable efficient allocation of bandwidth and expansion of slot number by using an Ethernet switch instead of a backplane in a MIPS system. However, the MIPS backplane only describes the expansion of the radio bandwidth and the slot number, and does not provide a technique for port expansion and data rate improvement in a system in which a switch is used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to minimize crosstalk while increasing pin utilization, and to provide a switch for miniaturization of a large-capacity switch system capable of accommodating a large number of ports while maintaining a sufficient space between signal lines on the backplane. It is to provide a high speed backplane of the system used.

In addition, the other purpose is to properly arrange the ports of the switch and the line card in the system to increase the number of ports of the switch, to maintain sufficient distance between transmission lines to prevent crosstalk and loss of the transmission line, to reduce the length of the transmission line and backplane The present invention provides a high-speed backplane that is cross-mounted between line cards that provide a shielding effect on a transmission line disposed on the circuit.

1 is a pod layout of a switch board and a line card according to the present invention.

Figure 2 is a conceptual diagram of the port connection between the switch board and the line card according to the present invention.

3 is a line card port disposed in the upper end of the switch port group according to the present invention.

Figure 4 is a line card port arranged in the lower end of the switch port group according to the present invention.

5 is a pattern structure diagram between a switch board and a line card according to the present invention.

Figure 6 is a connector pin assignment of the port according to the present invention.

Explanation of symbols on the main parts of the drawings

100,101: switch board 102 to 109: line card

110: transmitter 111: receiver

300,301,400,401: ports

In order to achieve the above object, the present invention provides a high speed backplane of a system in which a switch for serial data transmission is provided by providing a connection of a switch board and a line card having pins of a 5 + 2 row connector, respectively.

The middle pin of the 5 + 2 row connector pins is assigned to the ground pin, and two pins are allocated to the differential signal pins on both sides of the ground pin to configure the corresponding line as one port. By assigning a line between the ports to a ground pin, the connector pins of the switch board and line card ports are assigned to maintain a signal-to-ground ratio of 1: 1.5, respectively. to provide.

In addition, the present invention for achieving the above object, in the high-speed backplane of the system in which a switch for providing a connection of the switchboard and the line card to the switchboard port corresponding to the number of the line card as a group is used,

Line cards are symmetrically arranged around two switch boards, and each switch board port is connected to a port of a plurality of left and right line cards, and the left and right line cards are sequentially moved from the top to the bottom of the switch board. It provides a high-speed backplane of a system in which a switch is used, which is alternately connected to a port of symmetrical connection.

The present invention relates to the design of a backplane for mounting a large-capacity switch having a large number of ports and a high data transfer rate for each port by using a hard metric 5 + 2 row connector. In addition, a data rate of about 2.5 Gbps or more per transmission line is realized without being affected by the cell or packet type. One transmission line uses two connector pins to transmit serialized data at high speed, and four pins are used to configure one port for both transmission and reception, and include a ground pin that is allocated to prevent crosstalk between ports. Ten pins per port is sufficient.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail the present invention.

1 is a port layout view of a switch board and a line card according to the present invention, Figure 1a is a top view of the switch board and the line card port and Figure 1b is a bottom view layout. 1A and 1B, the two switchboards 100 and 101 on which the switches are mounted have 32 ports, respectively, and the line cards 102, 103, 104, 105, 106, 107, 108, and 109 have four cards arranged in symmetry. The number of ports of each line card 102-109 is 4 ports, respectively. Since the system to which the present invention is applied provides 1 + 1 switch protection switching, the two switchboards 100 and 101 are mounted side by side. Ports of the switchboards 100 and 101 and the line cards 102 to 109 reverse the positions of the transmitters 110 and 111 and the receivers 112 and 113 to prevent twisting when connecting patterns. For example, when the transmission port of the switchboard is to the left and the reception port is to the right, the transmission port of the line card is to the right and the reception port is to the left, thereby preventing twisting of each other during pattern connection. The reverse is also possible.

The backplane (not shown) according to the present invention provides a connection between two switchboards 100,101 and left and right line cards 102-109 having a speed of 622Mbps per port. The switch boards 100 and 101 and the line cards 102 to 109 serialize data to transmit data through differential signal lines provided by the backplane. Each port uses only 4 pins, 2 pins for each of the transmitters 110 and 111 and the receivers 112 and 113. Transmission of serialized data over the backplane uses 8B / 10B linecoding or SONET frames to prevent data errors. Since this transmission method has its own error prevention and error checking functions, no separate signal line is required for error checking. In the present invention, when the 16-port switch is used, a 622Mbps x 16 = 10Gbps switch can be mounted, and when the 32-port switch is mounted, the backplane becomes a 20Gbps switch system. In addition, the data rate per port can be increased to 2.5Gbps without changing the backplane, enabling the switch to 2.5Gbps x 16 = 40Gbps or 2.5Gbps x 32 = 80Gbps switch systems.

2 is a conceptual diagram of a port connection between a switch board and a line card according to the present invention. As shown in FIG. 2, when two 32-port switches are mounted for 1 + 1 switching, the signal line density of the switch slot portion becomes very high. Accordingly, in order to lower the density of the signal lines and maintain the gap between the signal lines, the ports of the two switchboards 100 and 101 are symmetrically arranged from left to right with respect to the line cards 102 to 109 arranged side by side. Alternately allocates sequentially. 2A and 2B show allocation of upper and lower ports of the switchboard 100 on the left side of the two switchboards 100 and 101, respectively, and FIGS. 2C and 2D show upper and lower portions of the switchboard 101 on the right side, respectively. It shows the allocation of the bottom port respectively.

Meanwhile, the 32 switch ports of the switch boards 100 and 101 are divided into eight switch ports as shown in FIG. 2, and each is divided into one group 200, 201, 202, 203, 204, 205, 206, and 207. Each of the line card ports is arranged in two ways. have. This is illustrated in FIGS. 3 and 4. The arrangement method will be described with reference to FIGS. 3 and 4.

Figure 3 is a port of the line card according to the present invention arranged on the upper end of the switch port group, the overall layout according to the layout of Figures 2a and 2c. In this case, the first port 300 at the top of the port group connects to the nearest line card on either side, and the next port 301 is assigned to the opposite port in the symmetrical position. That is, after the line cards are arranged symmetrically around two switch boards, the first port 300 of the first switch board is connected to the port of the nearest line card on either side (if left line card is connected). Port (301) connects to the line card port on the right side opposite the symmetrical position. The third port then connects to the next port on the left line card and the fourth port connects to the next port on the right line card. In this way, the ports on the switch board are connected to the ports on the left and right line cards sequentially from top to bottom, but are connected symmetrically.

Figure 4 is a port of the line card according to the present invention arranged at the lower end of the switch port group, the overall layout according to the layout of Figures 2b and 2d. In this case, the first port 400 at the top of the port group connects with the farthest line card on either side, and the next port 401 is assigned to the opposite port in the symmetrical position. In the same way, switch ports are arranged side by side with the line card symmetrically from top to bottom.

3 and 4, when the ports are arranged on the line card in the symmetrical order from the top to the bottom, the density of the actual signal line is reduced by half and the wiring is overlapped without overlapping portions between the signal lines. In the case of the transfer board, the port is allocated in the same manner, and in a system using a 32-port switch with 1 + 1 switching, the signal lines between the ports can be connected using only four layers with little crosstalk and loss.

5 is a pattern structure diagram between a switch board and a line card according to the present invention. As shown in FIG. 5, in order to maintain the straightness of the track and to connect it with the shortest distance, the direction of the track is changed in a stepped manner whenever passing through each slot portion. This arrangement reduces the length of the track and minimizes discontinuities. In addition, the shielding effect of the line can be provided by allocating the circumference passing through the slot portion to the ground pin 501 (only a part is shown in the figure).

Furthermore, to avoid signal loss, all bends are rounded and the two differential signal lines maintain spacing and line width to ensure impedance matching near 100Ω.

6 is a connector pin assignment diagram of a port according to the present invention. As shown in FIG. 6, when the 5 + 2 row connector is used, the Z and F columns cannot be used as signal lines, but are grounded to provide a shielding effect. Among the remaining 5 pins, A and B pins are assigned to the differential signal pin 601, C to the ground pin, and D and E columns are assigned to the differential signal pin 602 to configure one port 600. Each port 600 is spaced by one space, but one pin of each port company is assigned to the ground pin 603. One of the two differential signal lines 600 and 601 ports is a transmitter port and one is a receiver port. In this case, a transmission rate of 2.5Gbps or more per transmission line can be realized while maintaining a signal-to-ground ratio of 1: 1.5 in the slot portion in which the switch is mounted, such as an asynchronous transfer mode (ATM) switch or a packet switch. That is, as shown in FIG. 6, when the ground pins 603 are allocated one line between each port 600, one port 600 and one ground in a set composed of first and second lines are provided. Pin 603 and this set is repeated over and over. Here, four pins (601, 602) allocated as differential signal lines in the one port (600) are four (A, B, D, E) and one pin assigned to the ground pin is one in the port (600) (C), five from the ground pin 603, a total of six. Accordingly, four signal pins and six ground pins among the ten pins of the port 600 and the ground pin 603 become six, and the ratio of the signal to ground pins is 4: 6, that is, 1: 1.5. In this way, by assigning the signal-to-ground ratio of 1: 1.5, the transmission line transmission rate can be maintained at 2.5Gbps or more, and compared with the conventional signal-to-ground ratio 1: 2, the pin utilization is increased and the number of connectors is reduced, thereby reducing the overall volume. Will be. For example, if the signal-to-ground ratio is 1: 2, there should be 200 ground pins when there are 100 signal pins. However, as in the present invention, when the signal-to-ground ratio is 1: 1.5, only 150 ground pins are required, thereby improving the pin usage rate and minimizing the physical volume of the switch system while maintaining sufficient space between signal lines.

In addition, when the pins are allocated as described above, the differential signal line consisting of two pins is reversed in the direction of the electric field, so that crosstalk hardly occurs, and the other differential signal lines are shielded by the ground pin. In addition, a low voltage differential signaling (LVDS) level signal is transmitted through a differential signal line. In order to deliver the LVDS level signal without noise and crosstalk, an impedance matching of 100 Ω is required and the two signal lines should be maintained at the same interval. The pin arrangement of the present invention can prevent noise and crosstalk as well as impedance matching when transmitting serial data using LVDS.

Details of the detailed description and drawings described above are only one embodiment for describing the present invention, and those skilled in the art to which the present invention pertains may substitute and change the present invention without departing from the spirit of the present invention. will be.

Accordingly, the scope of the present invention should be determined by the appended claims rather than by the foregoing description and drawings.

According to the present invention, proper pin assignment methods and port arrangements provide impedance matching for LVDS signals and minimize signal noise and crosstalk.

In addition, the port utilization of the switch can be increased by increasing the pin utilization rate, and the data transmission speed of the port can be increased by 2.5Gbps or more due to the low crosstalk and loss of the line, so that a 32-port switching system configures an 80Gbps switching system without changing the backplane. can do. Furthermore, there is an effect that can configure a large capacity small switching system.

Claims (8)

In a high speed backplane of a system where a switch is used for serial data transmission by providing a connection of a switchboard and a line card, each having a pin of a 5 + 2 row connector, The middle pin of the 5 + 2 row connector pins is assigned to the ground pin, and two pins are allocated to the differential signal pins on both sides of the ground pin to configure the corresponding line as one port. A high speed backplane in a system in which a switch is used, which allocates a line between the ports to a ground pin so as to allocate the connector pins of the switch board and the line card port to maintain a signal-to-ground ratio of 1: 1.5. The method of claim 1, The position of the transmission port and the receiving port of the switchboard is a high-speed backplane of the system using a switch, characterized in that to prevent the twisting of the pattern when connecting the port by using the position of the transmission port and the receiving port of the line card, respectively. delete In a high-speed backplane of a system in which a switchboard port corresponding to the number of linecards is used as a group and a switch is used to provide connection of the switchboard and the linecard. Line cards are symmetrically arranged around two switch boards, and each switch board port is connected to a port of a plurality of left and right line cards, and the left and right line cards are sequentially moved from the top to the bottom of the switch board. A high speed backplane in a system where a switch is used, characterized in that it is alternately connected to the ports of the switch. The method of claim 4, wherein When the line card port is disposed at the upper end of the switchboard port group, the uppermost port of the switchboard port is connected with the nearest linecard port on either side of the left and right, and the port immediately below the uppermost port is symmetrical of the connected linecard. A high-speed backplane in a switch-enabled system, characterized in that it connects to the port on the opposite side of the location and the remaining switchboard ports connect symmetrically from top to bottom sequentially. The method of claim 4, wherein When the line card port is arranged at the lower end of the switchboard port group, the uppermost port of the switchboard port is connected with the farthest linecard port on either side and the port immediately below the uppermost port is symmetrical of the connected linecard. A high-speed backplane in a switch-enabled system, characterized in that it connects to the port on the opposite side of the position and the remaining switchboard ports connect the ports in sequential order from side to side. The method of claim 4, wherein A high speed backplane of a system in which a switch is used, characterized in that when a pattern of a data transmission line passes through a switchboard, a peripheral pin is assigned to a ground pin and the structure of the pattern is cascaded to reduce a connection path. The method of claim 7, wherein 2. A high speed backplane in a system employing a switch, wherein two differential signal lines maintain a spacing and width of said transmission line to match impedance near 100 Ω.