CN214413127U - Electronic device, first connector and printed circuit board - Google Patents

Abstract

The application discloses electronic equipment, a first connector and a printed circuit board, and relates to the technical field of network equipment. The electronic device includes a first connector and a printed circuit board; the bottom of the first connector comprises a first row of pins and a second row of pins which are adjacent, and the leading-out directions of the pins in the first row of pins and the second row of pins are a first leading-out direction and a second leading-out direction which are different in direction; the top surface of the printed circuit board is provided with a first row of pads and a second row of pads which are adjacent to each other, the pads in the first row of pads and the second row of pads are respectively provided with a first row of through holes and a second row of through holes, the first row of through holes and the second row of through holes are respectively used for leading out leads for connecting a first row of pins and a second row of pins, and the leading-out directions of the leads led out from the first row of through holes and the second row of through holes are respectively a third leading-out direction and a fourth leading-out direction which are far away from each other; the first row of pins is in compression joint with the first row of welding discs, and the second row of pins is in compression joint with the second row of welding discs.

Description

Electronic device, first connector and printed circuit board

Technical Field

The present application relates to the field of network device technologies, and in particular, to an electronic device, a first connector, and a printed circuit board.

Background

With the rapid development of communication technology, the demand for signal transmission of electronic devices is increasing.

The electronic device includes a connector and a Printed Circuit Board (PCB), the bottom of the connector is provided with a plurality of pins, and a via hole is punched on a pad of the PCB, so that a lead wire led out from the via hole is connected to the pins of the connector. The printed circuit board comprises a plurality of layers of circuit boards, wiring is carried out on each layer of circuit board according to a specified wiring principle, and signals in the electronic equipment are transmitted to a specified circuit board on the printed circuit board through pins on the connector or are transmitted to the pins on the connector through the specified circuit board on the printed circuit board.

Because the leading-out directions of two adjacent rows of pins in the connector are generally set to be the same direction, the leads led out from two adjacent rows of via holes have the problem of long routing distance or the problem of relatively short position. The wiring distance is long, so that the transmission route of signals is long, and the loss of the signals is easy to occur; the relative position is close, and crosstalk between two opposite signals is easily caused. The signal loss and crosstalk affect the accuracy of signal transmission, and thus the error rate of the electronic device is too high.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides electronic equipment, a first connector and a printed circuit board. The technical scheme at least comprises the following scheme:

according to an aspect of the present application, there is provided an electronic apparatus including: a first connector and a printed circuit board;

the bottom of the first connector comprises a first row of pins and a second row of pins which are adjacent, the leading-out direction of the pins in the first row of pins is a first leading-out direction, the leading-out direction of the pins in the second row of pins is a second leading-out direction, and the first leading-out direction is different from the second leading-out direction;

the top surface of the printed circuit board is provided with a first row of pads and a second row of pads which are adjacent, the pads in the first row of pads are provided with first row of through holes, the first row of through holes are used for leading out leads connected with first row of pins, the pads in the second row of pads are provided with second row of through holes, the second row of through holes are used for leading out leads connected with second row of pins, the leading-out direction of the leads led out from the first row of through holes is a third leading-out direction, the leading-out direction of the leads led out from the second row of through holes is a fourth leading-out direction, and the third leading-out direction and the fourth leading-out direction are mutually far away;

the first row of pins is in compression joint with the first row of welding discs, and the second row of pins is in compression joint with the second row of welding discs.

According to one aspect of the present application, there is provided a first connector, a bottom portion of the first connector comprising a first row of pins and a second row of pins adjacent to each other;

the leading-out direction of the pins in the first row of pins is a first leading-out direction, the leading-out direction of the pins in the second row of pins is a second leading-out direction, and the first leading-out direction is different from the second leading-out direction.

According to one aspect of the application, a printed circuit board is provided, wherein a top surface of the printed circuit board is provided with a first row of pads and a second row of pads which are adjacent;

a first row of through holes are formed in the bonding pads in the first row of bonding pads, a second row of through holes are formed in the bonding pads in the second row of bonding pads, and the first row of through holes and the second row of through holes are used for leading out leads;

the leading-out direction of the leads led out of the first row of through holes is a third leading-out direction, the leading-out direction of the leads led out of the second row of through holes is a fourth leading-out direction, and the third leading-out direction and the fourth leading-out direction are mutually far away.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

the leading-out directions of two rows of adjacent pins on the first connector are set to be different directions, and then the through holes are arranged on the bonding pads corresponding to the pins, so that the leading-out directions of the leads led out by the two rows of adjacent through holes are different, and signals in the electronic equipment are led out from directions far away from each other, thereby reducing the loss or crosstalk of the signals, improving the accuracy of signal transmission and relatively reducing the error rate of the electronic equipment.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an electronic device according to an exemplary embodiment of the present application;

FIG. 2 is a schematic plan view of an A-A layer of a printed circuit board provided by an exemplary embodiment of the present application;

FIG. 3 is a schematic diagram of an electronic device in the prior art;

FIG. 4 is a schematic plan view of the A-A layer of a prior art printed circuit board;

FIG. 5 is a schematic layout of pins of a first connector according to an exemplary embodiment of the present application;

FIG. 6 is a schematic plan view of a printed circuit board provided in an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a printed circuit board provided in an exemplary embodiment of the present application;

FIG. 8 is a schematic structural diagram of an electronic device provided in an exemplary embodiment of the present application;

FIG. 9 is a partial schematic view of a printed circuit board provided in an exemplary embodiment of the present application;

FIG. 10 is a front view of a layered outlet of a printed circuit board provided in an exemplary embodiment of the present application;

FIG. 11 is a side view of a layered wire-out of a printed circuit board provided by an exemplary embodiment of the present application;

fig. 12 is a top view of a printed circuit board provided by an exemplary embodiment of the present application.

The various reference numbers in the drawings are illustrated below:

100-an electronic device;

110-first connector:

111-ith row of pins; 112-row i + 1; 113-nth row pins; 114-n +1 th row of pins;

115-connector base;

120-printed circuit board:

121-ith row of pads; 122-row i +1 pads; 123-nth row of pads; 124-row n +1 pads;

125-plate body; 126-an insulating region;

130-a second connector;

01-pin; 011-first row of pins; 012-second row of pins;

02-a pad; 021-first row of pads; 022-a second row of pads; 023-third row of pads; 024 fourth row

A pad;

03-via holes; 031-a first row of vias; 032 — second row of vias; 033-a third row of vias; 034-fourth row

A via hole; 035-ground return holes;

041. 042-lead;

131-ith row of through holes; 132-ith +1 th row of via holes; 133-nth row of vias; 134-n +1 th row of vias; 141-first layer leads; 142-second layer leads.

Detailed Description

Unless defined otherwise, all technical terms used in the examples of the present application have the same meaning as commonly understood by one of ordinary skill in the art.

In the embodiments of the present application, reference to "front" and "rear" is made to front and rear as shown in the drawings. "first end" and "second end" are opposite ends.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of an electronic device 100 according to an exemplary embodiment of the present application. Illustratively, the electronic device 100 includes: a first connector 110 and a printed circuit board 120.

The electronic device 100 is one of a switch, router, server, and host bus adapter.

Connectors refer to devices used to connect signal modules and network ports, and may be used in corresponding switches, routers, servers, and host bus adapters. Illustratively, the first connector 110 belongs to one of the connectors. Depending on the signal transmission medium, there are several alternative types of the first connector 110, including but not limited to one of the following: board-to-cable connectors, proprietary interface connectors, radio frequency connectors, power connectors, fiber optic interface connectors. Illustratively, the first connector 110 is a fiber interface connector that may be used to connect the optical module with a port of the switch.

Illustratively, the number of the first connectors 110 can be set according to actual needs. For example, the number of the first connectors 110 is one of 1, 2, 4, 6, and 8. The first connector 110 includes, but is not limited to, at least one of the following models, depending on the model: a four-lane Pluggable connector (QSFP) and an eight-lane Pluggable connector (OSFP). The description will be made taking as an example that the first connector 110 is a QSFP series connector.

The printed circuit board 120, also called a printed circuit board, is used to connect with electronic components and provide an electrical circuit for the electronic components. Illustratively, the printed circuit board 120 includes at least one layer of circuit board, and the number of the circuit boards included in the printed circuit board 120 may be set according to actual needs. The printed circuit board 120 can be divided into a single-sided board, a double-sided board, a four-sided board, a six-sided board, and other multi-layered boards according to the number of layers of the circuit board.

Referring to fig. 1 and 2, the bottom of the first connector 110 includes a first row of pins 011 and a second row of pins 012 adjacent to each other, where a lead-out direction of a pin 01 in the first row of pins 011 is a first lead-out direction, a lead-out direction of a pin 01 in the second row of pins 012 is a second lead-out direction, and the first lead-out direction and the second lead-out direction are different. Wherein the first and second lead-out directions are shown by solid arrows in fig. 2. Printed circuit board 120's top surface is provided with adjacent first row of pad 021 and second row pad 022, be provided with first row of via 031 on the pad 02 in the first row pad 021, first row of via 031 is used for drawing forth the lead wire of connecting first row pin 011, be provided with second row of via 032 on the pad 02 in the second row pad 022, second row of via 032 is used for drawing forth the lead wire of connecting second row pin 012, the direction of drawing forth of the lead wire of drawing forth in the first row of via 031 is the third direction of drawing forth, the direction of drawing forth of the lead wire of drawing forth in the second row of via 032 is the fourth direction of drawing forth, the third direction of drawing forth keeps away from each other with the fourth direction of drawing forth. Wherein the third lead-out direction and the fourth lead-out direction are shown by dashed arrows in fig. 2. The first row pins 011 are pressed against the first row pads 021, and the second row pins 012 are pressed against the second row pads 022.

Illustratively, the top of the pin 01 is fixedly connected with the bottom of the first connector 110, and the extending direction of the bottom of the pin 01 is the leading-out direction of the pin 01. As shown in fig. 1, the pin 01 is an L-shaped airfoil pin, the top of the airfoil pin is fixedly connected to the copper pillar at the bottom of the first connector 110, and the extending direction of the bottom of the airfoil pin is the leading-out direction of the airfoil pin.

Illustratively, the leads 01, pads 02 and leads are all made of a conductive material, such as one of metallic copper or metallic tin. Illustratively, the via 03 disposed on the pad 02 may be filled with a conductive material. The filled conductive material is equivalent to a lead wire passing through the via 03 and is used for connecting the pin 01 of the first connector to a corresponding circuit board.

As schematically shown in fig. 1 and fig. 2, a lead 041 and a lead 042 are led out from the adjacent via 03 on the a-a layer circuit board, respectively, for example. Here, the lead-out direction of the lead 041 is the third lead-out direction, and the lead 042 is the fourth lead-out direction.

As shown in fig. 1, a first lead-out direction of a pin 01 in a first row of pins 011 is led out to the right, a second lead-out direction of a pin 01 in a second row of pins 012 is led out to the left, leads are respectively led out from via holes 03 to be connected with the corresponding pin 01, and the leads are routed on the a-a layer circuit board. The leads 01 in the first row of leads 011 are crimped with the pads 02 in the first row of pads 021, and the leads 01 in the second row of leads 012 are crimped with the pads 02 in the second row of pads 022. In conjunction with the wiring diagram of the a-a layer circuit board in the printed circuit board 120 shown in fig. 2, the lead 041 is led out to the right first and then to the top; via 042 exits first to the left and then to the bottom.

In the related art, referring to fig. 3, the first connector 110 includes adjacent m-th row pins and m + 1-th row pins, where m is a positive integer, and the leading directions are the same. For example, the lead-out directions of the mth row of pins and the (m + 1) th row of pins are both led out to the right.

Referring to fig. 3 and 4, taking as an example that a lead 041 and a lead 042 are respectively led out from two adjacent via holes 03 on the a-a layer circuit board, where the lead 041 is led out upward, the lead 042 is led out downward, and the lead 042 has two leading manners: referring to fig. 4 (a), the lead 042 is drawn leftward to the outside of the pad 02 and then drawn downward. At this time, the distance between the signal transmitted by the lead 042 and the signal transmitted by the lead 041 is long, but the trace length of the lead 042 is long, so that the transmission route of the signal is long, and the loss of the signal is easy to occur. Referring to fig. 4 (b), the lead 042 is led out rightward from the via 03 and then downward. At this time, the trace length of the lead 042 is relatively reduced by the length of one pad 02, but the distance between the signal transmitted by the lead 042 and the signal transmitted by the lead 041 is short, which is likely to cause crosstalk between two opposite signals.

As can be seen from comparing fig. 3 and fig. 1, in the electronic device 100 provided in the embodiment of the present application, the leading directions of two rows of pins 01 adjacent to each other on the first connector 110 are different. For example, the first row of pins 011 extends rightward, and the second row of pins 012 extends leftward. As can be seen from comparing fig. 4 (a) and fig. 2, in the electronic device 100 provided in the embodiment of the present application, the routing of the leads on the a-a layer circuit board is reduced by the length of one pad 02. Typically, the length of one pad 02 is 50-60 milli-feet (mil), which corresponds to a relative reduction in the signal transmission path by one pad 02. Alternatively, as can be seen from comparing fig. 4 (b) and fig. 2, in the electronic device 100 provided in the embodiment of the present application, the lead-out directions of the leads led out from two adjacent rows of vias 03 are different, which corresponds to a longer distance of the transmission route between the reverse signals, and crosstalk between the reverse signals is reduced. That is, the electronic device 100 provided in the embodiment of the present application avoids loss or crosstalk between signals, relatively improves accuracy of signal transmission, and reduces an error rate of the electronic device 100.

To sum up, according to the electronic device 100 provided in the embodiment of the present application, the leading-out directions of two adjacent rows of pins on the first connector 110 are set to different directions, and then the via holes 03 are arranged on the pads 02 corresponding to the pins 01, and the leading-out directions of the leads led out by the two adjacent rows of via holes 03 are different, so that signals in the electronic device are led out from directions away from each other, thereby reducing loss or crosstalk of the signals in the electronic device 100, improving accuracy of signal transmission, and reducing an error rate of the electronic device 100. Specifically, the lead wires led out from two adjacent rows of via holes 03 have different leading-out directions, so that the distance between the reverse signals is large, thereby avoiding crosstalk between adjacent signals and relatively reducing signal transmission routes.

In the use process of the electronic device 100, the leading-out directions of two rows of pins 01 adjacent to each other on the first connector 110 are different. That is, the leading directions of the two adjacent rows of pins 01 are not parallel. Since signals in the electronic device 100 are transmitted by the pins 01 and the leads led out from the vias 03, the transmission accuracy of the signals in two adjacent rows is affected by the leading-out direction of the pins 01 in two adjacent rows and the leading-out direction of the leads led out from the vias 03.

As shown schematically in fig. 2, in the electronic device 100 provided in the embodiment of the present application, the first lead-out direction and the second lead-out direction are opposite. That is, the lead-out direction of the pin 01 in the first row of pins 011 is opposite to the lead-out direction of the pin 01 in the second row of pins 012.

With reference to fig. 1 and 2, two vias 03 are respectively disposed on the pads 021 and 022 in the first row and the second row, which are adjacent to each other, and a lead 041 is led out from the via 03 to the right and a lead 042 is led out from the other via 03 to the left. At this time, the closest distance between the lead 041 and the lead 042 corresponds to a straight distance between two vias 03, which is the farthest pitch of the holes punched on two adjacent pads.

To obtain a better signal transmission effect, as schematically shown in fig. 2, in the electronic device 100 provided in the embodiment of the present application, the third leading-out direction and the fourth leading-out direction are opposite. That is, the lead wire drawn out of first row of via holes 031 is drawn out in the opposite direction to the lead wire drawn out of second row of via holes 032.

Referring to fig. 2, the lead 041 and the lead 042 are led out from opposite directions, so that transmission routes of a signal transmitted by the lead 041 and a signal transmitted by the lead 042 also extend in opposite directions. For example, the third drawing direction is drawn to the upper right, and the fourth drawing direction is drawn to the lower left. At this time, the distance between the signal transmitted by the lead 041 and the signal transmitted by the lead 042 can be maximized, and the interference between the two signals can be minimized.

In summary, in the electronic device 100 provided in the embodiment of the present application, the leading-out direction of the pin 01 and the leading-out direction of the lead led out from the via hole 03 are defined, so that the interference between two adjacent signals can be reduced to the minimum, the accuracy of transmission between two adjacent signals can be ensured, and the error rate of the electronic device 100 can be reduced.

In addition, the pin definition of each pin 01 is different according to the model of the first connector 110. Taking the first connector 110 as an example of a QSFP series first connector, as schematically shown in fig. 5, the bottom of the first connector 110 is provided with 4 rows of pins 01, and the number of the pins 01 is 76, wherein 4 rows and 4 columns of high-speed signal pins (indicated by a shaded part in the figure) are provided at intervals, so as to form 16 pairs of differential signals. Every 4 pairs of pins 01 are used for transmitting a group of high-speed signals, two pairs of pins 01 are used for receiving the high-speed signals, and two pairs of pins 01 are used for sending the high-speed signals; the remaining pins are a plurality of ground pins for connecting to grounded vias (also called ground return vias) on the printed circuit board 120 and a plurality of dummy pins.

Illustratively, the number of the leads 01 and the pads 02 is the same. Accordingly, in the case where the first connector 110 is a first connector of QSFP series, schematically shown in fig. 6, the printed circuit board 120 is provided with 4 rows of pads 02, the number of the pads 02 is 76, and the pads 02 corresponding to the 4 rows and 4 columns of high-speed signal pins are provided with vias 03 for leading out leads connected to the corresponding pins 01.

Illustratively, a plurality of pins 01 are uniformly arranged on the first connector 110, and a certain number of pins 01 form a pin group. Correspondingly, a plurality of bonding pads 02 are uniformly arranged on one circuit board of the printed circuit board 120, and a certain number of bonding pads 02 form a bonding pad group.

Illustratively, in the electronic device 100 provided in the embodiment of the present application, the first connector 110 includes odd-numbered rows of pins and even-numbered rows of pins, the first row of pins 011 is one of the odd-numbered rows of pins, and the second row of pins 012 is one of the even-numbered rows of pins.

The leading-out direction of the odd-numbered rows of pins is a first leading-out direction, and the leading-out direction of the even-numbered rows of pins is a second leading-out direction.

Since the pins 01 in the same row of pins usually occur in pairs, as shown in fig. 5, taking the bottom of the first connector 110 as an example including four adjacent rows of valid pins 01 (marked by the shaded parts in the figure), the four adjacent rows of pins 01 are the ith row of pins 111, the (i + 1) th row of pins 112, the nth row of pins 113 and the (n + 1) th row of pins 114, respectively, and each row includes 4 pairs of pins 01, each pair including two pins 01. The ith row of pins 111 and the nth row of pins 113 are odd rows of pins, the (i + 1) th row of pins 112 and the (n + 1) th row of pins 114 are even rows of pins, the blank pins 01 are ground pins or blank pins in the figure, and i and n are positive integers.

Illustratively, the lead-out direction of the ith row of pins 111 is a first lead-out direction; the lead-out direction of the i +1 th row of pins 112 is a second lead-out direction; the lead-out direction of the nth row of pins 113 is a first lead-out direction; the lead-out direction of the n +1 th row pin 114 is the second lead-out direction. Wherein the first lead-out direction and the second lead-out direction are different directions. Optionally, the first leading-out direction is opposite to the second leading-out direction.

Among them, the ith row pin 111, the (i + 1) th row pin 112, the nth row pin 113, and the (n + 1) th row pin 114 are pin groups formed by an even number of pins 01.

Illustratively, in the electronic device 100 provided in the embodiment of the present application, the first connector 110 further includes a first connector base 115, and the pin 01 is disposed on the first connector base 115.

Illustratively, in the electronic device 100 provided in the embodiment of the present application, the printed circuit board 120 includes pads in odd rows and pads in even rows, which are alternately disposed on the same layer of circuit board, the first row of pads 021 is one row of pads in the odd rows, and the second row of pads 022 is one row of pads in the even rows.

Odd-numbered rows of through holes are formed in the odd-numbered rows of bonding pads and used for leading out lead wires connected with the odd-numbered rows of pins; even rows of through holes are formed in the even rows of bonding pads and used for leading out lead wires connected with the even rows of pins; the leading-out direction of the leads led out from the odd-numbered rows of the through holes is a third leading-out direction; the leading-out direction of the leads led out from the even rows of the through holes is a fourth leading-out direction; the odd-numbered rows of pins are in compression joint with the odd-numbered rows of welding discs, and the even-numbered rows of pins are in compression joint with the even-numbered rows of welding discs.

As shown in fig. 6 and 7, taking the top surface of the printed circuit board 120 as an example that includes four adjacent rows of effective pads 02, the four adjacent rows of pads 02 are the ith row of pads 121, the (i + 1) th row of pads 122, the nth row of pads 123 and the (n + 1) th row of pads 124 respectively disposed on the same layer of circuit board, and each row includes 4 pairs of pads 02, each pair including two pads 02. The ith row of pads 121 and the nth row of pads 123 are odd-numbered pads, the (i + 1) th row of pads 122 and the (n + 1) th row of pads 124 are even-numbered pads, and i and n are positive integers.

Illustratively, an ith row of through holes 131 are formed in the ith row of pads 121, and the ith row of through holes 131 are used for leading out leads connected with the ith row of pins 111; an i +1 th row of through holes 132 are formed in the i +1 th row of bonding pads 122, and the i +1 th row of through holes 132 are used for leading out leads connected with the i +1 th row of pins 112; an nth row of through holes 133 are formed in the nth row of bonding pads 123, and the nth row of through holes 133 are used for leading out lead wires connected with the nth row of pins 113; the n +1 th row of bonding pads 124 are provided with n +1 th row of through holes 134, and the n +1 th row of through holes 134 are used for leading out leads connected with the n +1 th row of pins 114. Among them, the ith row via 131 and the nth row via 133 are odd row vias, and the (i + 1) th row via 132 and the (n + 1) th row via 134 are even row vias.

Illustratively, the lead-out direction of the lead led out from the i-th row of via holes 131 and the lead-out direction of the lead led out from the n-th row of via holes 133 are a third lead-out direction, and the lead-out direction of the lead led out from the i + 1-th row of via holes 132 and the lead-out direction of the lead led out from the n + 1-th row of via holes 134 are a fourth lead-out direction; the ith row pin 111 is in pressure contact with the ith row pad 121, the (i + 1) th row pin 112 is in pressure contact with the (i + 1) th row pad 122, the nth row pin 113 is in pressure contact with the nth row pad 123, and the (n + 1) th row pin 114 is in pressure contact with the (n + 1) th row pad 124.

Among them, the ith row pad 121, the (i + 1) th row pad 122, the nth row pad 123, and the (n + 1) th row pad 124 are a pad group formed of an even number of pads 02. Illustratively, the third lead-out direction and the fourth lead-out direction are different directions. Optionally, the third leading-out direction is opposite to the fourth leading-out direction.

As shown in fig. 6 and 7, in the electronic device 100 according to the embodiment of the present application, the printed circuit board 120 further includes a board body 125, and the plurality of pads 02 are disposed on the board body 125.

In addition, during the use of the electronic device 100, the lead wire drawn out from the via hole 03 is connected to the pin 01 of the first connector 110, and signals in the electronic device 100 are transmitted through the lead wire. Therefore, the length of the lead will have an effect on the transmission of the signal. The longer the length of the leads, the longer the transmission path of the signal, so that the more likely the signal is to be lossy or cross-talk, resulting in a higher error rate for the electronic device 100.

In order to avoid the overlong length of the lead, the specific arrangement position of the via hole 03 on the pad 02 can refer to the leading-out direction of the pin 01. Illustratively, in the electronic device 100 provided in the embodiment of the present application, the vias 03 correspond to the pins 01 one to one, and the vias 03 are disposed in the leading direction of the corresponding pins 01.

For example, the pin 01 is an L-shaped airfoil pin, and the extending direction of the bottom of the airfoil pin is the leading direction of the airfoil pin. Accordingly, a via 03 is punched in the land 02 corresponding to the airfoil pin. Wherein, the punching position is positioned in the extending direction of the bottom of the airfoil pin.

When the ith row pin 111 is a pin led out to the right as schematically shown in fig. 5, correspondingly, referring to fig. 6, an ith row via 131 is opened on the ith row pad 121. Wherein, the punching position of the ith row of via holes 131 is located at the right side of the ith row of pads 121.

When the i +1 th row pin 112 is a pin led out to the left as schematically shown in fig. 5, correspondingly, referring to fig. 6, an i +1 th row via 132 is opened on the i +1 th row pad 122. Wherein the punch-out position of the i +1 th row via 132 is located at the left side of the i +1 th row pad 122.

To sum up, in the electronic device 100 provided in the embodiment of the present application, the lead-out directions of two adjacent rows of pins 01 are set to be opposite directions, so that the transmission distance between two adjacent signals in the electronic device 100 is the largest, and the interference between the two adjacent signals is the smallest. In addition, the through hole 03 is arranged in the leading-out direction of the corresponding pin 01, so that the lead can be directly connected with the pin 01 after passing through the through hole 03, the wiring length of the lead is reduced, and the signal loss is reduced.

In the use process of the electronic device 100, a plurality of connectors are usually required to be connected to the printed circuit board 120, and taking the number of the connectors included in the electronic device 100 as two as an example, the first connector 110 is disposed on the upper layer of the printed circuit board 120, and the second connector 130 is disposed on the lower layer of the printed circuit board 120. Wherein the second connector 130 belongs to one of the connectors.

Illustratively, the electronic device 100 provided in the embodiment of the present application further includes a second connector 130. Wherein the bottom of the first connector 110 is pressed against the top surface of the printed circuit board 120, and the bottom of the second connector 130 is pressed against the bottom surface of the printed circuit board 120.

As schematically shown in fig. 8, the second connector 130 has the same pin structure as the first connector 110; the bottom surface of the printed circuit board 120 is provided with a third row of pads 023 and a fourth row of pads 024 which are adjacent; the pins 01 at the bottom of the second connector 130 are crimped to the pads 023 and 024 in the third row in the same manner as the first connector 110. Referring to fig. 1 and 8, the pins 01 located at the bottom of the second connector 130 are arranged in a central symmetry manner with the pins 01 located at the bottom of the first connector 110.

Fig. 9 shows an alternative implementation of the printed circuit board 120, in which only the pads 02, the vias 03 and the leads leading from the vias 03 are shown. Illustratively, in the electronic device 100 provided in the embodiment of the present application, the printed circuit board 120 includes at least two layers of circuit boards.

A top via hole is formed in the top circuit board of the printed circuit board 120, and the top via hole is used for leading out a lead connected with a pin 01 located at the bottom of the first connector 110; a bottom via hole is formed in the bottom circuit board of the printed circuit board 120, and the bottom via hole is used for leading out a lead connected with a pin 01 located at the bottom of the second connector 130; there is at least one pair of top and bottom vias in the same vertical direction, which is a direction perpendicular to the printed circuit board 120.

Referring to fig. 9 and 10, the printed circuit board 120 includes a first row of pads 021 and a second row of pads 022 disposed on the same layer of circuit board, and a plurality of first layer leads 141 are respectively led out from the first row of vias 031 and the second row of vias 032. Wherein, this layer of circuit board can be seen as the top circuit board, and via hole 03 in the first row of via hole 031 and via hole 03 in the second row of via hole 032 can be seen as the top via hole. In addition, black parts shown in fig. 9 are a pad 02, a via 03 and a plurality of second-layer leads 142 disposed on another layer of the circuit board, including a third row of pads 023 and a fourth row of pads 024 disposed on another layer of the circuit board, a third row of vias 033 and a fourth row of vias 034 are disposed on the third row of pads 023 and the fourth row of pads 024, and the plurality of second-layer leads 142 are respectively led out from the third row of vias 033 and the fourth row of vias 034. Wherein, another layer of the circuit board can be regarded as a bottom circuit board, and the via holes 03 in the third row of via holes 033 and the fourth row of via holes 034 can be regarded as bottom via holes.

Referring to fig. 11, top vias (i.e., via 03 in first row of vias 031 and via 03 in second row of vias 032) are located in the same vertical direction, and bottom vias (i.e., via 03 in third row of vias 033 and via 03 in fourth row of vias 034) are located in the same vertical direction. In the figure, solid arrows indicate that the lead led out from the top via is connected to the pin 01 at the bottom of the first connector 110, and dashed arrows indicate that the lead led out from the bottom via is connected to the pin 01 at the bottom of the second connector 130.

Illustratively, the traces of the first layer of leads 141 are located on the top circuit board and the traces of the second layer of leads 142 are located on the bottom circuit board. The routing direction of the first layer of leads 141 led out from the first row of via holes 031 and the routing direction of the first layer of leads 141 led out from the second row of via holes 032 deviate from each other, and the first layer of leads 141 are connected to the pins 01 of the first connector 110 disposed on the upper layer of the printed circuit board 120; the routing direction of the second layer lead 142 led out by the third row of via holes 033 and the routing direction of the second layer lead 142 led out by the fourth row of via holes 034 deviate from each other, and the second layer lead 142 is connected to the pin 01 of the second connector 130 disposed on the lower layer of the printed circuit board 120.

In addition, a partially idle pad 02 and via 03 are also shown in fig. 9. Fig. 10 shows a printed circuit board 120 based on fig. 9, in which the pads 02 and vias 03 of fig. 10 are removed.

As shown in fig. 11 schematically, in the electronic device 100 provided in the embodiment of the present application, the pitch of the top via and the bottom via in the vertical direction is not less than 30 mils. Wherein the pitch of the top and bottom vias in the vertical direction is represented by Z1.

That is, in the electronic device 100 provided in the embodiment of the present application, the printed circuit board 120 may be provided with a through hole, and the through hole penetrates through all layers of the circuit boards. The through holes can be used as a plurality of through holes 03, and conductive materials are filled in the through holes to be used as leads. When the through hole is not needed for one or more layers of circuit boards of the printed circuit board 120, the through hole of the layer is plugged by a back drilling operation.

In summary, the electronic device 100 provided in the embodiment of the present application includes the first connector 110, the printed circuit board 120, and the second connector 130, and the bottom of the first connector 110 is pressed against the top of the printed circuit board 120 and the bottom of the second connector 130 is pressed against the bottom of the printed circuit board 120 by arranging the pins 01 of the bottom of the first connector 110 and the pins 01 of the bottom of the second connector 130 to be centrosymmetric, so that the two connectors are connected to the printed circuit board 120.

During use of the electronic device 100, the transmission of signals is accomplished through conductive features on the wiring board of the printed circuit board 120. Since the area of the printed circuit board 120 is limited, and the pins 01 of the first connector 110 need to be pressed against the pads 02 of the designated circuit board, there are more leads on each layer of circuit board. In the signal transmission process of the electronic device 100, the adjacent signal transmissions have mutual interference due to the close routing distance of the leads.

In order to avoid interference between adjacent signals and reduce signal transmission loss, the electronic device 100 according to the embodiment of the present application is provided with a plurality of insulating regions 126 on the printed circuit board 120. As schematically shown in fig. 12, each insulating region 126 includes at least one top via and a bottom via that are adjacent to each other, and the top via and the bottom via are located in adjacent planes in the vertical direction.

The insulating region 126 is used for isolating interference of signal transmission between two adjacent vias 03. As shown in fig. 12, the insulating region 126 includes four vias 03 on the same layer of the circuit board. Wherein, the first row of pad 021 and the second row of pad 022 are located same layer circuit board, and the first row of pad 021 and the second row of pad 022 include two pairs of pads 02 respectively, are provided with the via hole 03 on the pad 02, are drawn forth first layer lead wire 141 by via hole 03. Fig. 12 also shows pads 02 and vias 03 on another layer of circuit board, specifically, a third row of pads 023 (not shown in the figure, where the position of the dotted line can be referred to) and a fourth row of pads 024 (not shown in the figure, where the position of the dotted line can be referred to) are disposed on another layer of circuit board, the third row of pads 023 and the fourth row of pads 024 respectively include two pairs of pads 02, the vias 03 are also disposed on the pads 02, the second layer of leads 142 are led out from the vias 03, and the layer of the circuit board on which the second layer of leads 142 is disposed is lower than the layer of the circuit board on which the first layer of leads 141 is disposed.

Additionally, the printed circuit board 120 includes ground reflow holes 035. Illustratively, one ground reflow hole 035 is correspondingly disposed on the periphery of one via 03, and the ground reflow hole 035 leads out from the ground wiring board on the printed circuit board 120 to be connected with the ground pins of the first connector 110 and/or the third connector 130.

Illustratively, the hole center distance between two adjacent top vias or two adjacent bottom vias is L1, the value of L1 is 31.5 mils, and the error value is ± 10 mils. In addition, the hole center distance between each top via and each bottom via (corresponding to each via 03) and the corresponding ground return hole 035 is L2, the value of L2 is 31.5mil, and the error value is ± 10 mil.

Illustratively, the pitch between adjacent top and bottom vias included in the insulating region 126 is L3, L3 is 28 mils, and the error value is ± 10 mils. The area of the insulating region 126 may be set according to actual needs, and as shown in fig. 12 schematically, in the electronic device 100 provided in the embodiment of the present application, the insulating region 126 disposed on the printed circuit board 120 includes at least two rectangular sections. Wherein the area of each rectangular interval is L4 × L5, the value of L4 is 60 mils, and the error value is +/-10 mils; l5 has a value of 40 mils and an error of + -10 mils.

In addition, the via 03 may be provided by using a drill. Illustratively, the via 03 is drilled using a drill below 8 mil.

In summary, in the electronic device 100 provided in the embodiment of the present application, the plurality of insulating regions 126 are disposed on the printed circuit board 120, so that signals transmitted on the lead wires led out from the adjacent top via hole and the adjacent bottom via hole are not interfered, and the loss of signal transmission is reduced.

As shown schematically in fig. 1 and 5, the present embodiment provides a first connector 110, and the foregoing description related to the first connector 110 can be applied to the present embodiment.

Illustratively, the first connector 110 provided in the embodiment of the present application includes a first row of pins 011 and a second row of pins 012 that are adjacent to each other.

The leading direction of the pins 01 in the first row of pins 011 is a first leading direction, the leading direction of the pins 01 in the second row of pins 012 is a second leading direction, and the first leading direction and the second leading direction are different.

Illustratively, the first lead-out direction and the second lead-out direction are opposite.

Illustratively, the first connector 110 provided in the embodiment of the present application includes the first connector 110 including odd-numbered rows of pins and even-numbered rows of pins, where the first row of pins 011 is one of the odd-numbered rows of pins, and the second row of pins 012 is one of the even-numbered rows of pins.

The leading-out direction of the odd-numbered rows of pins is a first leading-out direction; the lead-out direction of the pins in the even-numbered rows is the second lead-out direction.

Illustratively, the first connector 110 further includes a first connector base 115, and the pin 01 is disposed on the first connector base 115.

As schematically shown in fig. 6 to 11, the embodiment of the present application provides a printed circuit board 120, and the descriptions related to the printed circuit board 120 in the foregoing can be applied to the embodiment of the present application.

Illustratively, the top surface of the printed circuit board 120 provided by the embodiment of the present application is provided with a first row of pads 021 and a second row of pads 022 which are adjacent to each other.

A first row of through holes 031 are formed in the pads 02 of the first row of pads 021, a second row of through holes 032 are formed in the pads 02 of the second row of pads 022, and the first row of through holes 031 and the second row of through holes 032 are used for leading out leads; the lead wire led out from the first row of through holes 031 is led out in a third direction, the lead wire led out from the second row of through holes 032 is led out in a fourth direction, and the third direction and the fourth direction are away from each other.

Illustratively, the third lead-out direction and the fourth lead-out direction are opposite.

Illustratively, the printed circuit board 120 provided in the embodiment of the present application includes odd rows of pads and even rows of pads disposed on the same layer of circuit board, where the first row of pads 021 is one row of pads in the odd rows of pads, and the second row of pads 022 is one row of pads in the even rows of pads.

The odd-numbered rows of the bonding pads are provided with odd-numbered rows of through holes, the even-numbered rows of the bonding pads are provided with even-numbered rows of through holes, and the odd-numbered rows of through holes and the even-numbered rows of through holes are used for leading out leads; the leading-out direction of the leads led out from the odd-numbered rows of the through holes is a third leading-out direction; the leading-out direction of the leads leading out of the even rows of the through holes is the fourth leading-out direction.

Illustratively, the printed circuit board 120 further includes a board body 125, and the plurality of pads 02 are disposed on the board body 125.

In the present application, it is to be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated.

All the above optional technical solutions may be combined arbitrarily to form optional embodiments of the present application, and are not described herein again.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. An electronic device (100), characterized in that the electronic device (100) comprises: a first connector (110) and a printed circuit board (120);

the bottom of the first connector (110) comprises a first row of pins (011) and a second row of pins (012) which are adjacent, the leading-out direction of the pins (01) in the first row of pins (011) is a first leading-out direction, the leading-out direction of the pins (01) in the second row of pins (012) is a second leading-out direction, and the first leading-out direction and the second leading-out direction are different;

the top surface of the printed circuit board (120) is provided with a first row of adjacent pads (021) and a second row of adjacent pads (022), a first row of through holes (031) are arranged on the pads (02) in the first row of pads (021), the first row of through holes (031) are used for leading out and connecting the leads of the first row of pins (011), a second row of through holes (032) are arranged on the pads (02) in the second row of pads (022), the second row of through holes (032) are used for leading out and connecting the leads of the second row of pins (012), the leading-out direction of the leads led out in the first row of through holes (031) is a third leading-out direction, the leading-out direction of the leads led out in the second row of through holes (032) is a fourth leading-out direction, and the third leading-out direction and the fourth leading-out direction are far away from each other;

the first row of pins (011) are in compression joint with the first row of pads (021), and the second row of pins (012) are in compression joint with the second row of pads (022).

2. The electronic device (100) of claim 1, wherein the first exit direction and the second exit direction are opposite.

3. The electronic device (100) of claim 1, wherein the third and fourth exit directions are opposite.

4. The electronic device (100) of any of claims 1 to 3, wherein the first connector (110) comprises an alternating odd and even bank of pins, the first bank of pins (011) being one of the odd bank of pins and the second bank of pins (012) being one of the even bank of pins;

the leading-out direction of the odd-numbered rows of pins is the first leading-out direction; the lead-out direction of the pins in the even rows is the second lead-out direction.

5. The electronic device (100) of claim 4, wherein the printed circuit board (120) comprises an odd row of pads and an even row of pads arranged on the same layer of circuit board in an alternating manner, wherein the first row of pads (021) is one row of pads in the odd row of pads, and the second row of pads (022) is one row of pads in the even row of pads;

odd-numbered rows of through holes are formed in the odd-numbered rows of bonding pads and used for leading out lead wires connected with the odd-numbered rows of pins;

even rows of through holes are formed in the even rows of bonding pads and used for leading out lead wires connected with the even rows of pins;

the leading-out direction of the lead wires led out from the odd-numbered rows of the through holes is the third leading-out direction; the leading-out direction of the lead wires led out from the even rows of the through holes is the fourth leading-out direction;

and the odd-row pins are in compression joint with the odd-row welding discs, and the even-row pins are in compression joint with the even-row welding discs.

6. The electronic device (100) of any of claims 1 to 3, wherein the electronic device (100) further comprises a second connector (130);

the second connector (130) has the same pin structure as the first connector (110);

a third row of pads (023) and a fourth row of pads (024) which are adjacent to each other are arranged on the bottom surface of the printed circuit board (120);

the pins (01) at the bottom of the second connector (130) are pressed on the pads (023) and the pads (024) of the third row in the same pressing mode as the first connector (110);

the pins (01) positioned at the bottom of the second connector (130) and the pins (01) positioned at the bottom of the first connector (110) are distributed in a central symmetry manner.

7. The electronic device (100) of claim 6, wherein the printed circuit board (120) comprises at least two layers of wiring boards;

a top via hole is formed in a top circuit board of the printed circuit board (120), and the top via hole is used for leading out a lead connected with a pin (01) at the bottom of the first connector (110);

a bottom via hole is formed in a bottom circuit board of the printed circuit board (120), and the bottom via hole is used for leading out a lead connected with a pin (01) at the bottom of the second connector (130);

there is at least one pair of the top and bottom vias in the same vertical direction, which is a direction perpendicular to the printed circuit board (120).

8. The electronic device (100) of claim 7, wherein the top via and the bottom via have a pitch in the vertical direction of no less than 30 milli-feet.

9. A first connector (110), characterized in that the bottom of the first connector (110) comprises a first row of pins (011) and a second row of pins (012) which are adjacent;

the leading-out direction of the pins (01) in the first row of pins (011) is a first leading-out direction, the leading-out direction of the pins (01) in the second row of pins (012) is a second leading-out direction, and the first leading-out direction and the second leading-out direction are different.

10. A printed circuit board (120), characterized in that a top surface of the printed circuit board (120) is provided with a first row of pads (021) and a second row of pads (022) which are adjacent;

a first row of through holes (031) are formed in the bonding pads (02) in the first row of bonding pads (021), a second row of through holes (032) are formed in the bonding pads (02) in the second row of bonding pads (022), and the first row of through holes (031) and the second row of through holes (032) are used for leading out leads;

the leading-out direction of the lead wires led out of the first row of through holes (031) is a third leading-out direction, the leading-out direction of the lead wires led out of the second row of through holes (032) is a fourth leading-out direction, and the third leading-out direction and the fourth leading-out direction are far away from each other.

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