KR100449274B1 - Address transition detection circuit - Google Patents

Abstract

PURPOSE: An address transition detection circuit is provided, which is appropriate for low voltage swing and thus also is appropriate for a low voltage/low power semiconductor chip. CONSTITUTION: According to the address transition detection circuit, the first inverter unit(210) inverts an inputted address signal(ai) and then outputs it. The first delay unit(220) delays the address signal(ai) and then outputs it. The second delay unit(230) delays the output of the first inverter unit. The first transistor(240) is turned on/off in response to the output of the first delay unit, and receives the output of the first inverter unit when it is turned on and then outputs it. The second transistor(250) is turned on/off in response to the output of the second delay unit, and receives the address signal when it is turned on and then outputs it. And the second inverter(270) inverts outputs of the first and the second transistor.

Description

Address change detection circuit {ADDRESS TRANSITION DETECTION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address change detection circuit, and more particularly, to an address change detection circuit applicable to a low voltage / low power semiconductor device.

With the rapid development of semiconductor technology and the development of application specific integrated circuit (ASIC) technology, the system-on-chip (acceleration) of system-in-chip that integrates each part of the system in one system in one chip is accelerating. .

Along with this trend, power consumption by the chips has been suggested as a problem, and thus low-voltage / low-power of semiconductor chips has emerged as a major challenge. In particular, in the case of portable products using batteries, research on high-capacity batteries has been intensified as a method for prolonging the portable use time, but there is also increasing interest in the development of low-voltage / low-power semiconductor devices. In particular, in the case of a semiconductor memory, it is necessary to develop a memory having a low voltage / low power characteristic, and for this, a circuit for address transition detection (ATD) has been developed and provided.

In designing a memory, there is a need for a method of detecting address changes to generate differential timing signals for word-line, equalization and sensing. The circuit used in this case is the address change detection circuit, which plays an important role in reducing the active power of the memory.

1 is a circuit diagram of a full CMOS type as an example of a conventional address change detection circuit.

As shown in FIG. 1, in the full CMOS type, the address change detection circuit includes an inverter 110 that receives and inverts an address signal ai, a first delay unit 120 that delays and outputs the address signal ai; A first NOR gate 130 for performing NOR operation on the address signal ai and the output of the first delay unit 120, and a second delay unit 130 for delaying and outputting the output of the inverter 110; A second NOR gate 150 for NOR operation on the output of the inverter 110 and the output of the second delay unit 130, and outputs of the first and second NOR gates 130 and 150. And a third NOR gate 160 outputting the NOR operation.

The address change detection circuit configured as described above detects a change in the input address signal ai and outputs a detection signal .phi. (Ai). In this case, two-stage NOR gates consisting of the first to third NOR gates 130, 150, and 160 are used to generate the detection signal Φ (ai). However, in this case, a glitch may occur due to a process variation. Therefore, there is a case where the detection signal? (Ai) cannot be generated stably. In addition, the first to third NOR gates 130, 150, and 160 use two-input NOR gates. In general, two-input NOR gates are composed of four transistors, and thus, 16 transistors are used as a whole. .

As described above, the conventional address change detection circuit is not suitable for a low voltage swing when applied to a low voltage semiconductor device, and has a lot of power consumption. In addition, there is a problem that a large number of transistors are used to occupy a large area.

Accordingly, an object of the present invention is to provide an address change detection circuit suitable for a low voltage swing and suitable for a low voltage / low power semiconductor chip as proposed to solve the above-mentioned problems.

1 is a circuit diagram of a full CMOS type as an example of a conventional address change detection circuit;

2 is a detailed circuit diagram of an address change detection circuit according to a preferred embodiment of the present invention.

According to a feature of the present invention for achieving the object of the present invention as described above, the differential timing signal for the word line (line), equalization and sensing (mounting) mounted in the semiconductor memory An address change detection circuit for generating C) includes: a first inversion unit for inverting and outputting an input address signal; A first delay unit delaying and outputting the address signal; A second delay unit which delays and outputs an output of the first inverting unit; A first transistor that is turned on / off in response to an output of the first delay unit, and receives and outputs an output of the first inverter when turned on; A second transistor that is turned on / off in response to an output of the second delay unit, and receives and outputs the address signal when turned on; And a second inverter that receives the outputs of the first and second transistors and inverts the outputs.

In this embodiment, by a DC pass generated in the second inverter by the voltage drop of the first and second transistors, including current consumption compensation means configured between the power supply voltage terminal and the input terminal of the second inverter. Prevents current consumption.

In this embodiment, the current consumption compensation means includes a transistor configured between a power supply voltage terminal and an input terminal of the second inverter and turned on / off by an output of the second inverter.

In this embodiment, the transistor is a P-type MOS transistor.

In this embodiment, the first and second transistors are composed of N-type pass transistors.

According to the present invention as described above, the address change detection circuit generates the detection signal Φ (ai) by using an N-type pass transistor of one stage, and can quickly generate the detection signal Φ (ai) with a low voltage swing. Applicable when operating at high speed, it is also applicable when operating at low voltage / low power. In addition, unlike the related art, the number of transistors used may be reduced, thereby reducing the mounting area.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a detailed circuit diagram of an address change detection circuit according to a preferred embodiment of the present invention.

As shown in FIG. 2, the novel address change detection circuit of the present invention is largely divided into first and second inverters 210 and 270, first and second delay units 220 and 230, and first through second. 3 transistors 240, 250, and 260. The first and second transistors 230 and 240 are configured as N-type pass transistors, and the third transistor 260 is configured as a P-type MOS transistor.

The first inverter 210 inverts and outputs the address signal ai. The first and second delay units 220 and 230 receive and delay the address signal ai and its inverted signal, respectively, and output the delayed signals, which are input to the gate terminals of the first and second transistors 240 and 250, respectively. . The first and second transistors 240 and 250 are turned on / off off according to the voltage level of the signal input to the gate terminal, respectively, so that the address signal ai or the first inverter 210 An inversion signal is input to the second inverter 270 to output a detection signal? (Ai) that detects an address change.

In this case, the inverter consumes unnecessary current by the DC path generated by the voltage drop of the first and second transistors 240 and 250. Therefore, in order to prevent this, the third transistor 260 is configured as a compensation transistor between the power supply voltage terminal VDD and the input terminal of the second inverter 270, and the output of the second inverter 27 is input to the gate. do. Therefore, unnecessary generation of power consumption by the DC path is prevented.

According to the present invention as described above, the address change detection circuit generates the detection signal? (Ai) by using an N-type pass transistor of one stage. Therefore, as compared with the conventional full CMOS type address change detection circuit, it is possible to generate the detection signal? (Ai) faster with a lower voltage swing. Therefore, it can be applied when operating at high speed, and also applicable when operating at low voltage / low power. In addition, unlike the related art, the number of transistors used may be reduced, thereby reducing the mounting area.

Claims (5)

In an address change detection circuit mounted in a semiconductor memory for generating differential timing signals for word-line, equalization, and sensing: A first inverting unit 210 inverting and outputting the input address signal ai; A first delay unit 220 for delaying and outputting the address signal ai; A second delay unit 230 delaying an output of the first inverter 210 and outputting the delayed output; A first transistor 240 that is turned on / off in response to the output of the first delay unit 220, and receives and outputs the output of the first inverter 210 when turned on; A second transistor 250 that is turned on / off in response to the output of the second delay unit 230 and receives and outputs the address signal ai when turned on; And a second inverter (270) for receiving the outputs of the first and second transistors (240, 250), and inverting and outputting the outputs. The method of claim 1, Including the current consumption compensation means 260 is configured between the power supply voltage terminal (VDD) and the input terminal of the second inverter 270, by the voltage drop of the first and second transistors 240, 250 2 The address change detection circuit, characterized in that the current consumption is prevented from occurring by the DC path generated in the inverter (270). The method of claim 2, The current consumption compensation means 260 is And a transistor configured between a power supply voltage terminal (VDD) and an input terminal of the second inverter (270) and turned on / off by an output of the second inverter (270). The method of claim 3, wherein And the transistor is a P-type MOS transistor. The method of claim 1, And the first and second transistors (240, 250) are configured as N-type pass transistors.

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