KR100449178B1 - Initializing circuit of semiconductor device to simplify constitution of circuit and reduce layout area - Google Patents

Abstract

PURPOSE: An initializing circuit of a semiconductor device is provided to simplify constitution of a circuit and reduce a layout area by outputting an initialization signal of a high potential state for a predetermined interval of time by the operation of a delay part even if a power supply voltage increases rapidly and by having a low voltage detecting ability with respect to the variation of the power supply voltage. CONSTITUTION: A delay part(1) induces a gradual increase of a power supply voltage in an initial power supply. A voltage dividing part(2) divides and outputs a power supply voltage according to the voltage and the state signal outputted from the delay part. An initializing circuit operates according to an inversion signal of the division voltage and the state signal outputted from the voltage dividing part so as to output an initialization signal.

Description

Initialization circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initialization circuit of a semiconductor device, and more particularly, to an initialization circuit of a semiconductor device that enables initialization and low voltage detection of a semiconductor memory device.

In general, the initial operation of a semiconductor memory device such as a flash EEPROM starts from a read mode. This is because the operating mode is designed to maintain the read mode when the power supply voltage is applied to the device for the first time. At this time, the state machine for detecting the state of the device is divided into parts such as latches and registers. Detect their initial value. When the detected initial value is different from the set initial value, the device is initialized. An initialization circuit is provided in the device for such initialization.

In addition, the semiconductor memory device is configured to generate the high voltage and the negative voltage necessary for the program and erase operations by using the power supply voltage. Therefore, since the fluctuation of the power supply voltage is deeply related to the reliability of the memory device, the low voltage detection circuit is provided in the memory device. The low voltage detection circuit serves to continuously detect the level of the power supply voltage. When the power supply voltage is lowered below a certain level, a signal is generated to initialize the device to prevent abnormal operation of the device.

By the way, since the conventional semiconductor memory element is provided with the initialization circuit and the low voltage detection circuit, respectively, the circuit structure becomes complicated. As a result, it occupies a large layout area, which makes it difficult to increase the device integration.

Accordingly, an object of the present invention is to provide an initialization circuit of a semiconductor device which can solve the above-mentioned disadvantages by allowing an initialization signal to be output by a voltage detector operated according to an output voltage and a state signal of the voltage divider.

The present invention for achieving the above object is a delay unit for inducing a gradual increase of the power supply voltage at the time of initial power supply, and is operated according to the voltage and the state signal output from the delay unit, the voltage for outputting a distributed power supply And a divider and a voltage detector for outputting an initialization signal according to the output voltage and the state signal of the voltage divider. And the delay unit is connected between a power supply voltage and a first node, a transistor having a gate connected to ground, a transistor connected between the first node and ground, and configured to operate as a capacitor, a power supply voltage and a connection between the first node. And a gate having a transistor connected to the first node, wherein the voltage divider is connected between a first resistor having one terminal connected to a power supply voltage, another terminal of the first resistor and a second node, and a gate Is connected between a transistor connected to the first node, a second resistor connected to one terminal of the second node, another terminal of the second resistor, and a ground, and a gate connected to a state signal input terminal. Wherein the voltage detector is connected between a power supply voltage and a third node, the transistor is connected to a fourth node by a gate thereof, and the third node is in contact with the third node. A transistor connected to the ground, the gate connected to the second node, the first and second inverters connected in series between the third node and the output terminal, the third node and the ground, and a gate connected to the second node. And a third inverter connected between the transistor connected to the four nodes, the state signal input terminal, and the fourth node.

1 is a circuit diagram for explaining an initialization circuit of a semiconductor device according to the present invention.

2 and 3 are graphs for explaining the operation of the initialization circuit according to the present invention.

<Explanation of symbols for main parts of the drawing

1: delay unit 2: voltage divider unit

3: voltage detector

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a circuit diagram illustrating an initialization circuit of a semiconductor device according to the present invention.

As shown in FIG. 1, an initialization circuit of a semiconductor device according to the present invention includes a delay unit 1 for inducing a gradual increase in power supply voltage during initial power supply and a voltage and state signal output from the delay unit 1. And a voltage detector 3 for outputting the divided power supply voltage and a voltage detector 3 for outputting an initialization signal according to the output voltage of the voltage divider 2 and the state signal.

The delay unit 1 includes a PMOS transistor P1 having a gate connected to ground between a power supply voltage Vcc and the first node K1, and an NMOS transistor N1 having a gate connected to the first node K1. An NMOS transistor N2 connected in parallel and configured to operate as a capacitor is connected between the first node K1 and ground.

The voltage divider 2 includes an NMOS transistor N3 having a resistor R1 and a gate connected to the first node K1 in series between a power supply voltage Vcc and a second node K2. The NMOS transistor N4 having the resistor R2 and the gate connected to the state signal REFEN input terminal is configured to be connected in series between the two nodes K2 and the ground. In this case, a voltage drop circuit including a MOS diode instead of the resistors R1 and R2 may be used to divide the voltage of the voltage divider 2.

The voltage detector 3 is connected to a PMOS transistor P2 having a gate connected to a fourth node K4 between a power supply voltage Vcc and a third node K3, and is connected between the third node K3 and ground. An NMOS transistor N5 having a gate connected to the second node K2 is connected, and the first and second inverters I1 and I2 are connected in series between the third node K3 and the output terminal OUT. It is composed. A third inverter I3 is connected between the status signal REFEN input terminal and the fourth node K4, and a gate is connected between the third node K3 and the ground to the fourth node K4. The NMOS transistor N6 is configured to be connected. The operation of the initialization circuit configured as described above will now be described.

When the power supply voltage Vcc is applied to the semiconductor memory device, the state machine detects the device state and outputs a state signal REFEN. In this case, when the device maintains the initialization state, that is, the read mode, the device outputs a low potential signal, and when the device does not maintain the read mode, the device outputs a high potential signal.

First, when the semiconductor memory device does not maintain the read mode,

The transistor N4 and the transistor P2 are each turned on by the state signal REFEN input to the high potential state, and the potential of the first node K1 is gradually raised. . At this time, when the ramping time of the power supply voltage Vcc is short, the potential of the first node K1 is gradually raised by the transistor N2 configured to operate as a capacitor. Until the potential of K1 reaches the threshold voltage of the transistor N3, the second node K2 is maintained at a low potential state by the turn-off of the transistor N3. The third node K3 is in a high potential state and an initialization signal of a high potential state is output through the output terminal OUT. Next, when the potential of the first node K1 becomes higher than the threshold voltage of the transistor N3, the resistors R1 and R2 are applied to the second node K2 by the turn-on of the transistor N3. The voltage divided by is applied. In addition, the transistor N5 is turned on by the voltage distributed by the resistors R1 and R2 so that the third node K3 is changed to a low potential state. Therefore, the low-potential initialization signal is output through the output terminal OUT. That is, even when the power supply voltage Vcc rises rapidly, the initialization signal of the high potential state is outputted through the output terminal OUT for a predetermined time by the operation of the delay unit 1, and the delay time is the transistor ( P1) and the size of the transistor N2.

Second, when the semiconductor memory device maintains the read mode,

The transistor N4 and the transistor P2 are turned off by the state signal REFEN input in the low potential state, and the transistor N3 is turned off by the voltage output from the delay unit 1. On, the second node K2 remains at a high potential state. In addition, the transistor N5 is turned on by the potential of the second node K2, so that the third node K3 is in a low potential state, whereby the third terminal K3 is in a low potential state through the output terminal OUT. An initialization signal is output.

In addition, the initialization circuit according to the present invention also has a low voltage detection function for detecting a change in the power supply voltage (Vcc) generated during the operation of the device. For example, when the potential of the power supply voltage Vcc is lowered below a predetermined level, that is, when the potential of the second node K2 is lowered below the threshold voltage of the transistor N5, the transistor N5 is turned off. Is off. At this time, since the state signal REFEN is input in the high potential state, the third node K3 is in the high potential state and the initialization signal of the high potential is output through the output terminal OUT.

For reference, FIGS. 2 and 3 are graphs illustrating a change in voltage according to a change in time, and FIG. 2 is a diagram illustrating the first node K1 when a ramping-up time of the power supply voltage Vcc is short. Shows the process of increasing the voltage of the second node (K2) by the voltage of), wherein the potential rise of the second node (K2) appears with a predetermined time delay, and through the output terminal (OUT) The potential of the output initialization signal persists to 4.5V. In addition, FIG. 3 shows the potential of the second node K2 when the power supply voltage Vcc is ramped down, wherein the potential change of the second node K2 occurs without time delay. Can be.

As described above, the initialization circuit according to the present invention can output the initialization signal of the high potential state for a predetermined time by the operation of the delay unit even if the power supply voltage rises quickly, and has a fast low voltage detection function against the change of the power supply voltage. In addition, when implementing the initialization circuit of the semiconductor device according to the present invention, the configuration of the circuit is simplified, the layout area is reduced, there is an effect that the degree of integration of the device can be improved.

Claims (4)

A delay unit for inducing a gradual increase in power supply voltage during initial power supply; A voltage divider for dividing a power supply voltage according to a voltage and a state signal output from the delay unit; And And a voltage detector configured to output an initialization signal in response to a divided voltage output from the voltage divider and an inverted signal of the state signal. The method of claim 1, wherein the delay unit, A transistor connected between the power supply voltage and the first node and having a gate connected to ground; A transistor connected between the first node and ground and configured to operate as a capacitor; And And a transistor connected between a power supply voltage and the first node and whose gate is connected to the first node. The method of claim 1, wherein the voltage divider, A first resistor having one terminal connected to the power supply voltage; A transistor connected between the other terminal of the first resistor and a second node, the gate of which is connected to the first node; A second resistor having one terminal connected to the second node; And And a transistor connected between the other terminal of the second resistor and a ground, the transistor of which a gate is connected to a state signal input terminal. The method of claim 1, wherein the voltage detector, A transistor connected between a power supply voltage and a third node, the gate of which is connected to the fourth node: A transistor connected between the third node and ground and whose gate is connected to the second node; First and second inverters connected in series between the third node and the output terminal; A transistor connected between the third node and ground and whose gate is connected to the fourth node; And And a third inverter connected between the state signal input terminal and the fourth node.

Images