KR100446391B1 - Driver circuit of liquid crystal display device and its driving method, especially preventing generation of main clock signal - Google Patents

Driver circuit of liquid crystal display device and its driving method, especially preventing generation of main clock signal Download PDF

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KR100446391B1
KR100446391B1 KR1019970071887A KR19970071887A KR100446391B1 KR 100446391 B1 KR100446391 B1 KR 100446391B1 KR 1019970071887 A KR1019970071887 A KR 1019970071887A KR 19970071887 A KR19970071887 A KR 19970071887A KR 100446391 B1 KR100446391 B1 KR 100446391B1
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signal
clock signal
liquid crystal
driver
clock
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KR1019970071887A
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Korean (ko)
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KR19990052423A (en
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이건호
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비오이 하이디스 테크놀로지 주식회사
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: A driver circuit of a liquid crystal display device and its driving method are provided to reduce power consumption by proving a power saving clock signal to a liquid crystal panel driver IC disabled during an inactive period of an image signal. CONSTITUTION: A liquid crystal display device comprises a driver IC driving a liquid crystal panel by generating a control signal using a main clock signal(MLCK). In a clock generation unit(100), A clock signal preventing the generation of the main clock signal is provided by a horizontal synchronous signal(H) and a vertical synchronous signal(V) or a data enable signal. And the driver IC is disabled during an inactive period of an image signal. The inactive period of the image signal is an inactive period of the data enable signal.

Description

액정표시소자의 구동회로 및 구동방법Driving circuit and driving method of liquid crystal display device

본 발명은 액정표시소자에 관한 것으로서, 특히 소비전력이 낮은 액정표시소자의 구동회로 및 그의 구동방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device having low power consumption and a driving method thereof.

최근 액정화면을 구비한 휴대용 컴퓨터, 휴대용 통신기기등에 대한 수요가 증폭하고 있다. 이들 휴대용 기기들은 일반적으로 건전지 또는 충전지로 구동되는데, 건전지 또는 충전지는 공급할 수 있는 전력이 제한되어있기 마련이다.Recently, the demand for portable computers, portable communication devices, and the like with LCD screens is increasing. These portable devices are usually powered by batteries or rechargeable batteries, which have a limited power supply.

따라서, 전기적 효율을 높여 소비전력을 줄인 액정패널이 요망되고 있다.Accordingly, there is a demand for a liquid crystal panel that has increased electrical efficiency and reduced power consumption.

액정패널을 구동시키는 드라이버 IC는, 외부로부터 제공되는 주클락신호(이하 MCLK라고 칭함), 영상신호에 포함되어 있는 수평동기신호와 수직동기신호, 및 데이터 인에이블 신호(DTMG)를 입력받아 상기 액정패널의 각각의 화소에 구동제어신호를 제공한다.The driver IC for driving the liquid crystal panel receives a main clock signal (hereinafter referred to as MCLK), a horizontal sync signal and a vertical sync signal included in an image signal, and a data enable signal DTMG. A drive control signal is provided to each pixel of the panel.

일반적으로, 액정화면에 제공되는 영상신호는 직렬방식이기 때문에, 수평 및 수직동기신호를 제어신호로 하여, 영상신호를 수평 및 수직방향으로 주사시킴으로써 하나의 영상을 구현하는 주사선 방식이 사용되고 있다.In general, since the video signals provided on the liquid crystal display are in series, a scanning line method for realizing a single image by scanning the video signals in the horizontal and vertical directions using the horizontal and vertical synchronization signals as the control signals is used.

직렬방식의 영상신호가 액정패널의 시작점에서 종점에 도달한 후, 다음 시작점으로 복귀하는 시간을 귀선시간이라고 하는데, 상기 귀선시간동안 액정패널은 블랭킹(Blanking) 되어야 정상적인 디스플레이된다.After the serial image signal reaches the end point from the start point of the liquid crystal panel, the return time to the next start point is called a return time. During the return time, the liquid crystal panel should be blanked before being displayed normally.

상기 블랭킹 시간을 보장하기 위해서 영상신호에 귀선소거시간을 설정한다. 즉, 수평귀선시간을 수평주사시간의 약 17%, 수직귀선시간을 수직주사시간의 8%정도를 차지하는 귀선소거시간을 설정해줌으로서, 정상적인 영상을 구현한다.In order to guarantee the blanking time, a blanking time is set in the video signal. In other words, the normal return time is set so that the horizontal return time takes about 17% of the horizontal scanning time and the vertical return time takes about 8% of the vertical scanning time.

또한, 데이터 인에이블 신호(DTMG)는 영상신호 이외의 노이즈 또는 간섭신호에 의한 액정패널의 오동작을 예방하기 위해서 사용된다. 이것은 상기 데이터 인에이블 신호가 주기적으로 액정패널 드라이버 IC에 디스에이블 신호를 제공하여, 상기 디스에이블 구간동안 어떠한 데이터도 받아들이지 않게하므로써 이루어진다.In addition, the data enable signal DTMG is used to prevent malfunction of the liquid crystal panel due to noise or interference signals other than the video signal. This is done by the data enable signal periodically providing a disable signal to the liquid crystal panel driver IC so that no data is accepted during the disable period.

종래의 일반적인 경우, 액정패널의 드라이버 IC는 주클락신호(MCLK)에 의해 직접적으로 제어되며, 따라서 드라이버 IC는 액정화면에 계속적으로 전력을 제공한다.In the conventional general case, the driver IC of the liquid crystal panel is directly controlled by the main clock signal MCLK, and thus the driver IC continuously provides power to the liquid crystal display.

그러나, 귀선소거시간 및 데이터 인에이블 신호(DTMG)의 디스에이블 구간에는 액정패널의 블랭킹되기 때문에 사실상 액정표시소자가 구동될 필요가 없다.However, since the liquid crystal panel is blanked in the blanking time and the disable period of the data enable signal DTMG, the liquid crystal display does not actually need to be driven.

따라서 본 발명은 귀선소거시간 동안에도 MCLK이 항상 드라이버 IC에 공급되는 기존의 설계방식 대신, 수평 및 수직 귀선소거시간 또는 데이터 인에이블 신호 (DTMG)의 디스에이블 구간과 같은 영상신호의 비활성구간동안 MCLK을 비동작상태로 되게하므로써, 소비전력을 감소시킬 수 있는 액정표시소자의 구동방법 및 구동회로를 제공하는데 그 목적이 있다.Therefore, in the present invention, instead of the conventional design method in which MCLK is always supplied to the driver IC even during the blanking time, the MCLK during the inactive period of the video signal such as the horizontal and vertical blanking time or the disable period of the data enable signal (DTMG) It is an object of the present invention to provide a driving method and a driving circuit of a liquid crystal display element that can reduce power consumption by making the non-operating state.

도 1a 내지 도 1c 는 본 발명의 제1실시예를 설명하기 위한 도면,1a to 1c are views for explaining a first embodiment of the present invention,

도 2a 내지 도 2c 는 본 발명의 제1실시예를 설명하기 위한 도면,2a to 2c are views for explaining the first embodiment of the present invention,

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

100, 200 : 클럭발생수단 11 : 버퍼100, 200: clock generating means 11: buffer

12, 13, 22 : 앤드 게이트 21 : 버퍼12, 13, 22: end gate 21: buffer

MCLK : 주클럭신호 V : 수직동기신호MCLK: Main clock signal V: Vertical synchronization signal

H : 수평동기신호 DTMG : 데이터 인에이블신호H: Horizontal sync signal DTMG: Data enable signal

Ma, Mb : 클럭신호Ma, Mb: Clock signal

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 드라이버 IC를 구비하는 액정표시소자에 있어서, 상기 드라이버 IC에 제공되는 클락신호가, 영상신호의 비활성구간 동안 상기 드라이버 IC를 디스에이블시키는 것을 특징으로 하는 액정표시소자의 구동방법을 제공한다.In order to achieve the above object of the present invention, the present invention provides a liquid crystal display device comprising a driver IC, wherein the clock signal provided to the driver IC disables the driver IC during an inactive period of the video signal. A driving method of a liquid crystal display device is provided.

또한 본발명은 상기 구동방법을 구현하는 회로로서, 수평동기신호, 수직동기신호, 및 주클락신호를 그 입력으로 하여, 상기 수평동기신호 및 수직동기신호의 귀선소거시간동안 비활성구간이 되는 클락신호를 출력하는 클락발생수단을 포함하는 것을 특징으로 하는 액정표시소자의 구동회로를 제공한다.In addition, the present invention is a circuit for implementing the driving method, the clock signal which becomes inactive during the retrace time of the horizontal synchronization signal and the vertical synchronization signal, the horizontal synchronous signal, the vertical synchronous signal, and the main clock signal as inputs thereof. It provides a driving circuit of the liquid crystal display device comprising a clock generating means for outputting.

또한, 데이터 인에이블신호, 및 주클락신호를 그 입력으로 하여, 상기 데이터 인에이블신호의 비활성구간에 비활성구간이 되는 클락신호를 출력하는 클락발생수단을 포함하는 것을 특징으로 하는 액정표시소자의 구동회로를 제공한다.And a clock generating means for inputting a data enable signal and a main clock signal as its inputs, and outputting a clock signal which becomes an inactive section to an inactive section of the data enable signal. To serve.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 액정표사소자의 구동회로는 수평동기신호(H), 수직동기신호(V), 데이터 인에이블 신호(DTMG), 및 주클락신호(MCLK)에 의해 입력 데이터를 제어하여, 액정패널에 영상을 디스플레이시켜 주는 드라이버 IC(도면상에 도시되지 않음)와, 데이터 인에이블 신호(DTMG) 또는 수직동기신호(V), 수평동기신호(H)를 이용하여, 데이터 디스에이블시간 또는 귀선소거시간동안 주클락신호를 비활성화 시켜주기 위한 클락신호를 상기 드라이버로 발생하는 클락신호발생부로 구성된다.The driving circuit of the liquid crystal display element of the present invention controls the input data by the horizontal synchronizing signal (H), the vertical synchronizing signal (V), the data enable signal (DTMG), and the main clock signal (MCLK). Data disable time or blanking time using a driver IC (not shown) for displaying an image, a data enable signal DTMG, a vertical sync signal V, or a horizontal sync signal H And a clock signal generator for generating a clock signal for deactivating the main clock signal.

도 1a는 제 1실시예에 따른 액정표시소자의 구동회로에 있어서, 클락신호발생부(100)를 설명하기 위한 블록도이다.FIG. 1A is a block diagram illustrating the clock signal generator 100 in the driving circuit of the liquid crystal display device according to the first embodiment.

도 1a에 도시된 바와 같이, 제 1 실시예에 따른 클락신호발생부(100)는 수직동기신호(V), 수평동기신호(H), 및 주클락신호(MCLK)를 입력으로 하여, 도 1b에 도시된 바와 같이 데이터 인에이블 신호의 비활성구간에 드라이버 IC를 디스에이블 시켜, 소비전력을 감소시켜주기 위한 클락신호(Ma)를 드라이버 IC(도면에는 도시되지 않음)으로 출력시킨다.As shown in FIG. 1A, the clock signal generator 100 according to the first embodiment receives the vertical synchronization signal V, the horizontal synchronization signal H, and the main clock signal MCLK as input signals, and FIG. 1B. As shown in FIG. 6, the driver IC is disabled in the inactive period of the data enable signal, thereby outputting a clock signal Ma for reducing power consumption to the driver IC (not shown).

도 1c는 제 1 실시예에 따른 클락신호발생부(100)의 상세회로도를 도시한 것이다.1C shows a detailed circuit diagram of the clock signal generator 100 according to the first embodiment.

도 1c에 도시된 바와 같이 클락신호발생부(100)는 수직 및 수평동기신호(V, H)를 입력으로 하는 제 1 앤드 게이트(11), 상기 제 1 앤드게이트의 출력과 주클락신호(MCLK)을 입력으로하는 버퍼(12)의 출력을 두 입력으로 하는 제 2 앤드 게이트 (13)로 구성되어 있다.As illustrated in FIG. 1C, the clock signal generator 100 may include the first and gate 11 inputting the vertical and horizontal synchronization signals V and H, the output of the first and gate, and the main clock signal MCLK. Is composed of a second end gate 13 having two inputs as an output of the buffer 12 as an input.

도 1c를 참조하면, 수직 또는 수평동기신호(V, H)중 어느 하나의 신호가 비활성인 로우상태, 즉 귀선소거시간에 들어가게되면 도 1b에 도시된 바와 같이 로우상태로 되는 클락신호(Ma)를 드라이버 IC로 출력시킨다. 따라서, 귀선소거시간동안 주클럭신호(MCLK)를 입력하여 클락신호발생부(100)로 부터의 클럭신호(Ma)에 의해 비활성상태로 만들어 주게되고, 주클럭신호에 의해 드라이버 IC에서 발생되는 액정 디스플레이용 게이트 및 소오스 콘트롤 신호도 비활성상태로 된다.Referring to FIG. 1C, when any one of the vertical or horizontal synchronization signals V and H enters an inactive low state, that is, a blanking time, the clock signal Ma that becomes low as shown in FIG. 1B. Output to the driver IC. Therefore, the main clock signal MCLK is inputted during the retrace time to make it inactive by the clock signal Ma from the clock signal generator 100, and the liquid crystal generated by the driver IC by the main clock signal. The display gate and source control signals are also inactive.

도 1b에 도시된 바와 같이, 주클락신호(MCLK)와, 본 실시예에 따른 클락신호 (Ma)를 비교하면, 클락신호(Ma)의 로직로우상태, 즉 비활성구간이 주클락 신호 (MCLK)의 비활성구간 보다 약 25% 증가되었음을 알 수 있다.As shown in FIG. 1B, when the main clock signal MCLK is compared with the clock signal Ma according to the present embodiment, the logic low state of the clock signal Ma, that is, the inactive section is the main clock signal MCLK. It can be seen that about 25% more than the inactive period of.

이것은, 수평주사시간의 약 17%, 수직주사시간의 약 8% 정도를 차지하는 귀선소거시간동안, 도 1a 및 도 1b에 도시된 바와 같은 클락신호발생부(100)에 로우상태가 입력되기 때문이다.This is because a low state is inputted to the clock signal generator 100 as shown in FIGS. 1A and 1B during the blanking time, which accounts for about 17% of horizontal scanning time and about 8% of vertical scanning time. .

도 2a는 본 발명의 제 2실시예에 따른 클락신호발생부(200)를 설명하기 위한 블록도이다.2A is a block diagram illustrating a clock signal generator 200 according to a second embodiment of the present invention.

도 2a에 도시된 바와 같이, 제 2 실시예에 따른 클락신호발생부(200)는 데이터 인에이블신호(DTMG) 및 주클락신호(M)를 입력으로 하여, 도 2b와 같은 클락신호 (Mb)를 출력시킨다.As shown in FIG. 2A, the clock signal generation unit 200 according to the second embodiment receives the data enable signal DTMG and the main clock signal M as inputs, and the clock signal Mb as shown in FIG. 2B. Outputs

도 2c는 제 2 실시예에 따른 클락신호발생부(200)의 상세회로도를 도시한 것이다.2C shows a detailed circuit diagram of the clock signal generator 200 according to the second embodiment.

도 2c에 도시된 바와 같이 클락신호발생부(200)는 데이터 인에이블 신호 (DTMG)와, 주클락(MCLK)을 입력으로 하는 버퍼(21)의 출력을 그 두 입력으로 하는 앤드 게이트(22)로 구성되어 있다.As shown in FIG. 2C, the clock signal generation unit 200 uses the AND gate 22 having the two inputs as the data enable signal DTMG and the output of the buffer 21 as the main clock MCLK. Consists of

도 2c를 참조하면, 클락신호발생부(200)는 데이터인에이블 신호(DTMG)가 로직로우, 즉 비활성상태가 되면 그 출력도 로직로우상태를 갖게됨을 알 수 있다.Referring to FIG. 2C, when the data enable signal DTMG becomes logic low, that is, in an inactive state, the clock signal generator 200 may have a logic low state.

도 2b에 도시된 바와 같이, 주클락(MCLK)신호와, 본 실시예에 따른 클락신호 (Mb)를 비교하면, 클락신호(Mb)의 비활성구간이 주클락 신호의 비활성구간 보다 증가되었음을 알 수 있다.As shown in FIG. 2B, when the main clock MCLK signal is compared with the clock signal Mb according to the present embodiment, it can be seen that the inactive section of the clock signal Mb is larger than the inactive section of the main clock signal. have.

상기 제 1 , 제 2 실시예의 클락신호(Ma, Mb)는, 도시되지는 않았지만 액정패널 드라이버 IC의 입력단에 공급된다. 따라서, 액정화면은 클락신호(Ma, Mb)의 활성구간동안만 구동되게 된다.The clock signals Ma and Mb of the first and second embodiments are supplied to input terminals of the liquid crystal panel driver IC although not shown. Therefore, the liquid crystal display is driven only during the active period of the clock signals Ma and Mb.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 종래의 일반적인 경우와 같이 주클락신호가 액정패널 드라이버 IC를 직접적으로 제어하는 것이 아니라, 영상신호의 비활성구간동안에 디스에이블 되는 절전형 클락신호를 액정패널 드라이버 IC에 제공하므로써, 소비전력을 감소시킬 수 있다.As described in detail above, according to the present invention, the main clock signal does not directly control the liquid crystal panel driver IC as in the conventional case. Instead, the liquid crystal panel uses a power saving type clock signal that is disabled during an inactive period of the video signal. By providing the driver IC, power consumption can be reduced.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

주클락신호를 이용하여 제어신호를 발생하여 액정패널을 구동하는 드라이버 IC를 구비하는 액정표시소자에 있어서,A liquid crystal display device comprising a driver IC for driving a liquid crystal panel by generating a control signal using a main clock signal. 수평동기신호와 수직동기신호, 또는 데이터 인에이블신호에 의해 상기 주클럭신호의 발생을 차단하는 클럭신호를 상기 드라이버 IC에 제공하여, 영상신호의 비활성구간 동안 상기 드라이버 IC를 디스에이블시키며, 상기 영상신호의 비활성구간은 데이터 인에이블신호의 비활성구간인 것을 특징으로 하는 액정표시소자의 구동방법.Providing the driver IC with a clock signal that blocks the generation of the main clock signal by a horizontal synchronization signal, a vertical synchronization signal, or a data enable signal, thereby disabling the driver IC during an inactive period of the video signal; The inactive section of the signal is an inactive section of the data enable signal. 수평동기신호, 수직동기신호, 및 주클락신호를 그 입력으로 하여, 상기 수평동기신호 및 수직동기신호의 귀선소거시간동안 비활성구간이 되는 클락신호를 발생하는 클럭발생수단과;Clock generation means for inputting a horizontal synchronizing signal, a vertical synchronizing signal, and a main clock signal as inputs thereof to generate a clock signal which becomes an inactive section during the blanking time of the horizontal synchronizing signal and the vertical synchronizing signal; 상기 클럭발생수단으로부터 발생된 클럭신호에 의해 영상신호의 비활성구간동안 디스에이블되는 액정패널 드라이버 IC를 포함하는 것을 특징으로 하는 액정표시소자의 구동회로.And a liquid crystal panel driver IC which is disabled during an inactive period of the video signal by the clock signal generated from the clock generating means. 제 2 항에 있어서,The method of claim 2, 상기 클락신호발생수단은 수평동기신호 및 수직동기신호를 그 입력으로 하는 제 1 앤드 게이트;The clock signal generating means includes: a first AND gate which receives, as its input, a horizontal synchronous signal and a vertical synchronous signal; 주클락신호를 그 입력으로 하는 버퍼; 및A buffer having the main clock signal as its input; And 상기 제 1 앤드 게이트 및 상기 버퍼를 그 입력으로 하여, 그 출력으로서 상기 클락신호발생수단의 출력으로 하는 제 2 앤드 게이트를 포함하는 것을 특징으로 하는 액정표시소자의 구동회로.And a second AND gate serving as the input of the first AND gate and the buffer, and serving as an output of the clock signal generating means. 데이터 인에이블신호, 및 주클락신호를 그 입력으로 하여, 상기 데이터 인에이블신호의 비활성구간에 비활성구간이 되는 클락신호를 발생하는 클럭발생수단과;Clock generation means for inputting a data enable signal and a main clock signal as inputs thereof to generate a clock signal that becomes an inactive period in an inactive period of the data enable signal; 상기 클럭발생수단에서 발생된 클럭신호에 의해 영상신호의 비활성구간동안 디스에이블되는 액정패널 드라이버 IC를 포함하는 것을 특징으로 하는 액정표시소자의 구동회로.And a liquid crystal panel driver IC which is disabled during the inactive period of the video signal by the clock signal generated by the clock generating means. 제 4 항에 있어서,The method of claim 4, wherein 상기 클락발생수단은 주클락신호를 그 입력으로 하는 버퍼; 및The clock generating means includes a buffer having a main clock signal as its input; And 데이터 인에이블 신호 및 상기 버퍼의 출력을 그 입력으로 하는 앤드 게이트를 포함하는 것을 특징으로 하는 액정표시소자의 구동회로.And an AND gate having a data enable signal and an output of the buffer as an input thereof.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11948514B2 (en) 2021-09-16 2024-04-02 Samsung Display Co., Ltd. Display device and a method of operating the display device

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02192275A (en) * 1989-01-20 1990-07-30 Fujitsu Ltd Display controller
JPH02207299A (en) * 1989-02-07 1990-08-16 Fujitsu Ltd Display control circuit
JPH08305316A (en) * 1995-05-12 1996-11-22 Sharp Corp Image display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02192275A (en) * 1989-01-20 1990-07-30 Fujitsu Ltd Display controller
JPH02207299A (en) * 1989-02-07 1990-08-16 Fujitsu Ltd Display control circuit
JPH08305316A (en) * 1995-05-12 1996-11-22 Sharp Corp Image display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11948514B2 (en) 2021-09-16 2024-04-02 Samsung Display Co., Ltd. Display device and a method of operating the display device

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