KR100446319B1 - Image sensor and method for fabricating the same - Google Patents

Abstract

The present invention is to provide an image sensor and a method of manufacturing the same to prevent a reduction in the driving range according to the reduction of the area of the photodiode, the image sensor of the present invention is disposed at a predetermined distance on the semiconductor layer, the semiconductor layer A first gate electrode and a second gate electrode, a spacer in contact with both sidewalls of the first gate electrode and the second gate electrode, a photodiode in the semiconductor layer aligned with one edge of the first gate electrode, and the first gate electrode And a floating diffusion region in the semiconductor layer having one side overlapped by a spacer width in contact with the other side wall of one gate electrode and the other side spaced by the spacer width from an edge of the spacer in contact with one side wall of the second gate electrode.

Description

Image sensor and method for manufacturing the same {Image sensor and method for fabricating the same}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an image sensor and a method for manufacturing the same.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and a charge coupled device (CCD) is located at a position where individual metal-oxide-silicon (MOS) capacitors are very close to each other. Charge carriers are stored and transported in capacitors, and CMOS image sensors use CMOS technology that uses control circuits and signal processing circuits as peripheral circuits. It is a device that adopts a switching method that makes transistors and sequentially detects output using them.

1 shows that a unit pixel of a conventional CMOS image sensor includes one photodiode (PD) and four NMOSs (Tx, Rx, Sx, and Dx), and four NMOSs (Tx, Rx, Sx and Dx are transfer transistors (Tx) for transporting photo-generated charges concentrated in a photodiode (PD) to a floating diffusion region (FD), and a node of a node at a desired value. Reset transistor (Rx), source follower buffer amplifier (Source Follower Buffer Amplif ier) to set the potential and discharge the charge (C _pd ) to reset the floating diffusion region (FD) A drive transistor (Dx), and a select transistor (Sx) for addressing (Addressing) by switching.

Here, the transfer transistor (Tx) and the reset transistor (Rx) use a native transistor (Native NMOS), the drive transistor (Dx) and the select transistor (Sx) use a common transistor (Normal NMOS), and the reset transistor (Rx) A transistor for correlated double sampling (CDS).

The unit pixel of the CMOS image sensor flows the detected photogenerated charge after detecting the light of the visible wavelength band in the photodiode region PD using a native transistor. The amount transferred to the TD diffusion region FD, that is, the gate of the drive transistor Dx, is output as an electrical signal at the output terminal Vout.

In recent years, as the line width of the image sensor is reduced, that is, the size of the unit pixel and the size of the photodiode in the 0.13 占 퐉 image sensor are also reduced. As the size of the photodiode decreases, the capacitance of the photodiode decreases.

Accordingly, there is a problem in that a dynamic range of the image sensor is lowered as a result of the reduction of the charge capacity stored in the photodiode.

In other words, the charge capacity is proportional to the size of the depletion layer of the photodiode. As the size of the photodiode decreases, the depletion layer decreases, so that the charge capacity of the photodiode decreases and the driving range of the output terminal decreases.

On the other hand, the magnitude (ΔV) of the voltage change in the floating diffusion region represents voltage sensitivity (Voltagesensitivity), which determines the size of the driving range of the unit pixel output terminal, and this driving range determines the discriminating power of the electrical signal due to incident light. However, in a unit pixel having a small size, the magnitude of the voltage change in the floating diffusion region cannot be large, so that the driving range of the unit pixel output terminal is limited.

For example, the magnitude ΔV of the voltage change in the floating diffusion region representing the driving range is expressed as follows.

here, Represents charge capacity, Denotes the capacitance of the floating diffusion region.

According to Equation 1, when the area of the photodiode decreases, the charge capacity ( ), And accordingly the magnitude of the voltage change ( ), The driving range is lowered.

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide an image sensor and a method of manufacturing the same suitable for preventing a reduction in driving range due to the reduction of the area of the photodiode.

1 is an equivalent circuit diagram of a unit pixel of a conventional CMOS image sensor;

2 is a structural cross-sectional view of a CMOS image sensor according to an embodiment of the present invention;

3A to 3E are cross-sectional views illustrating a method of manufacturing the CMOS image sensor shown in FIG. 2;

4 a plan view according to FIG. 3e;

* Explanation of symbols for the main parts of the drawings

21: p ⁺⁺ -substrate 22: p- epi layer

23: field oxide film 24: gate oxide film

25a: First gate electrode Tx 25b: Second gate electrode Rx

26: n ^-- diffusion layer 27: nitride film spacer

29: n ⁺ -floating diffusion region 31: n ⁺ -source / drain

35: metal contact

The image sensor for achieving the above object is in contact with the semiconductor layer, the first gate electrode and the second gate electrode disposed at a predetermined distance on the semiconductor layer, respectively contacting both side walls of the first gate electrode and the second gate electrode. A spacer, a photodiode in the semiconductor layer aligned with one edge of the first gate electrode, and one spacer overlapping with a spacer width in contact with the other side wall of the first gate electrode and a spacer in contact with one side wall of the second gate electrode And a floating diffusion region in the semiconductor layer having the other side spaced apart from the edge by the spacer width.

In addition, the method of manufacturing the image sensor of the present invention comprises the steps of simultaneously forming a first gate electrode and a second gate electrode arranged at a predetermined distance on the semiconductor layer, aligned on one side edge of the first gate electrode in the semiconductor layer Forming a photodiode, forming a spacer in contact with both side walls of the first gate electrode and the second gate electrode, and overlapping one side and the second overlapping with a spacer width in contact with the other side wall of the first gate electrode And forming a floating diffusion region in the semiconductor layer, the floating diffusion region having the other side spaced apart from the edge of the spacer in contact with one side wall of the gate electrode by the spacer width.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a cross-sectional view of an element of a CMOS image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a p-epitaxial layer 22 is epitaxially grown on a p ⁺⁺ substrate 21, a field oxide film 23 is formed on a predetermined portion of the p-epi layer 22, and a field oxide film is formed. The first gate electrode 25a and the second gate electrode 25b are formed at a predetermined distance on the active region of the p- epi layer 22 defined by (23), and the first gate electrode 25a The buried photodiode 26 is formed in the p-epitaxial layer 22 while being aligned at one edge.

Here, the first gate electrode 25a is the gate electrode of the transfer transistor, the second gate electrode 25b is the gate electrode of the reset transistor, and the buried photodiode 26 is not shown in the figure, but the p-epi layer 22 is shown. and a deep n ^_ formed in a deep portion in the p- epitaxial layer (22) diffusion layer and p ^_ - epitaxial layer 22, a shallow p ^o formed near the surface of the diffusion layer has a pnp structure.

In addition, an n ⁺ -floating diffusion region 29 is formed in the p-epitaxial layer 22 between the first gate electrode 25a and the second gate electrode 25b, where n ⁺ -floating diffusion region. Reference numeral 29 is overlapped a predetermined width x below the first gate electrode 25a by the shadow effect and spaced apart from the edge x of the second gate electrode 25b by the width x. Here, the width x spaced apart is the distance from the nitride film spacer 27 to be described later.

As a result, the effective area of the n ⁺ -floating diffusion region 29 decreases.

The nitride film spacer 27 is provided on both sidewalls of the first gate electrode 25a and the second gate electrode 25b, and the interlayer insulating layer 32 is covered on the entire surface including the first and second gate electrodes. The metal contact 35 is connected to the n ⁺ -floating diffusion region 29 through the interlayer insulating film 32.

3A to 3E are cross-sectional views illustrating a method of manufacturing the CMOS image sensor shown in FIG. 2.

As shown in FIG. 3A, after epitaxially growing the low concentration p- epi layer 22 on the p ⁺⁺ substrate 21 doped with the high concentration p-type impurity, a predetermined portion of the p- epi layer 22 is formed. A field oxide film 23 is formed for isolation between devices.

Subsequently, the gate oxide film 24 is formed on the active region of the p-epitaxial layer 22 defined by the field oxide film 23, and the transfer transistor Tx and the reset transistor Rx are formed on the gate oxide film 24. Gate electrodes 25a and 25b are simultaneously formed.

At this time, when the gate electrodes 25a and 25b are formed, the gate electrodes of the drive transistor Dx and the select transistor Sx, which form the unit pixels of the CMOS image sensor, are also formed at the same time, and the gate electrode of the transfer transistor is referred to as a 'first gate electrode. 25a ', and the gate electrode of the reset transistor is abbreviated as' second gate electrode 25b'.

Next, photodiodes PD and 26 are formed in the p-epitaxial layer 22 while being aligned with one side edge of the first gate electrode 25a and the edge of the field oxide film 23.

Here, the photodiode 26 is typically p- epitaxial layer (22) / n ^{- -} diffusion layer / p ^o - buried diffusion layer made of a pnp photodiode; a (Buried Photodiode DBPD), The forming method will be omitted .

Next, a nitride film is deposited on the entire surface of the p-epitaxial layer 22 on which the photodiode 26 and the first and second gate electrodes 25a and 25b are formed, and then the entire surface is etched to form the first and twenty-second gate electrodes 25a, The nitride film spacers 27 are formed on both side walls of 25b).

At this time, the nitride film spacer 27 is formed to a thickness of 1500 kPa to 2500 kPa, preferably 2000 kPa.

The reason why the nitride film, not the oxide film, is used as the insulator for the spacer is that the nitride film has a better selectivity than the oxide film in the self aligned contact etching (SAC) exposing the floating diffusion region FD.

As shown in FIG. 3B, a first mask 28 for forming a floating fusion region is formed on the resultant formed nitride layer spacer 27. In this case, the first mask 28 exposes the surface of the p-epitaxial layer 22 having the floating diffusion region formed at both sides thereof aligned with the centers of the first gate electrode 25a and the second gate electrode 25b.

Next, a high concentration n-type impurity is ion-implanted while giving a tilt angle θ to the p-epi layer 22 exposed by the first mask 28 in a uni-direction to n ⁺ -floating diffusion. Area 29 is formed.

At this time, the tilt angle θ is an angle inclined at a predetermined angle from the ion implantation angle of 0 ° perpendicular to the surface of the p- epi layer 22 to the p- epi layer 22.

Therefore, when the impurity ion is implanted with a tilt angle θ in one direction, the n ⁺ − floating diffusion region 29 is opposite to one edge where the photodiode 26 of the first gate electrode 25a is formed, that is, the other edge. And overlap with a predetermined width and are spaced apart from one edge of the second gate electrode 25b by a width overlapping with the first gate electrode 25a.

In other words, the effective channel length of the transfer transistor is reduced.

The process of ion implantation while giving the tilt angle θ in one direction described above is called a shadow effect, and the length (x) at which the shadow effect is generated is one edge of the second gate electrode 25b and n ⁺ -floating. This is the distance where the diffusion region 29 is spaced apart.

Here, the shadow effect refers to a phenomenon in which a total amount of ion implantation is performed at one fixed ion implantation angle or a certain amount of ion implantation is adjusted at a next non-contiguous ion implantation angle after being implanted at a predetermined amount at one ion implantation angle. It is called.

On the other hand, the above-described ion implantation does not rotate (rotation), the tilt angle (θ) can be adjusted according to the depth (x) of the shadow.

The n ⁺ -floating diffusion region 29 formed by the above-described process reduces the effective area.

As shown in FIG. 3C, after removing the first mask 28, the photoresist film is coated on the entire surface and patterned by exposure and development to cover the entire area except for the n ⁺ -floating diffusion region 29. 30 is formed. In this case, the second mask 30 exposes the surface of the p- epi layer 22 exposed on the other side of the second gate electrode.

Next, a high concentration n-type impurity (n ⁺ ) is ion-implanted without a tilt angle perpendicularly to the surface of the p-epitaxial layer 22 exposed by the second mask 30 to form the n ⁺ -source / drain region 31. Form.

Here, although the source / drain and the floating diffusion region are formed at the same time by ion implantation of high concentration n-type impurity (n ⁺ ), in the present invention, the ion implantation mask process is performed twice, and the n ⁺ -source / drain region An LDD (Lightly Doped Drain) structure (not shown) in contact with (31) is formed in the transistors except the floating diffusion region and the photodiode before the nitride film spacer 27 is formed.

As shown in FIG. 3D, after the second mask 30 is removed, an interlayer insulating film 32 is formed on the entire surface. A method of forming the interlayer insulating film 32 is formed by depositing TEOS (Tetra Ethyl Ortho Silicate) and TEOS. After depositing BPSG (Boro Phospho Silicate Glass) on the BPSG flow to planarize.

Next, a photoresist film is applied on the planarized interlayer insulating film 32 and patterned by exposure and development to form a contact mask 33. At this time, the contact mask 33 is for forming a contact between the n ⁺ -floating diffusion region 29 and the metal wiring.

Next, the interlayer insulating layer 32 exposed by the contact mask 33 is wet-etched or dry-etched to form a contact hole 34 exposing a part of the surface of the n ⁺ -floating diffusion region 29.

At this time, since the interlayer insulating film 32 uses an oxide film such as TEOS and BPSG, and the nitride film spacer 27 is a nitride film, the nitride film spacer 27 at the time of etching to form the contact hole 34 has a sufficient selection ratio and has a magnetic selectivity. Alignment contact etching (SAC) is possible.

If the oxide film is used as a spacer, the area of the bottom of the contact hole exposed by a predetermined portion of the spacer when the interlayer insulating film 32 for forming the contact hole 34 is etched will be large, but a sufficient selectivity for the oxide film as in the present invention. When used as the nitride film spacer 27, the area of the bottom of the contact hole 34 exposed is narrower than when the oxide film is used as a spacer.

As a result, it is advantageous to secure an overlay margin for the contact mask 33, and because of the narrowness of the bottom of the exposed contact hole 34, the area of n ⁺ -floating diffusion region 29 is reduced, so that n ⁺ - The capacitance C _FD of the floating diffusion region 29 can be reduced.

Moreover, the shadow effect is used to form the n ⁺ -floating diffusion region 29, thereby substantially reducing the area S _FD of the effective n ⁺ -floating diffusion region 29.

finally, Given n ⁺ a-floating di capacitance of the diffusion region (29) (C _FD) is valid effective n ⁺ - area of the floating diffusion region (29) (S _FD) decreases as decreases and, according to equation (1) Magnitude of voltage change ) Increases the driving range and increases the driving range.

As shown in FIG. 3E, after the contact mask 33 is removed, pre-cleaning is performed before the metal deposition, and the metal is connected to the n ⁺ -floating diffusion region 29 through the contact hole 34. The contact 35 is formed.

In this case, the metal contact 35 is formed by first depositing Ti / TiN as a barrier metal and then depositing a metal film such as tungsten (W) on the barrier metal. The above method of forming the metal contact 35 is commonly known as a tungsten plug (W-plug) process.

FIG. 4 is a plan view of FIG. 3E. In the case of the metal contact 35, the periphery of the metal contact 35 is surrounded by the first and second gate electrodes 25a and 25b, so that the self-aligned contact is easily manufactured by the nitride film spacer 27.

The image sensor to which the above-described embodiment is applied has an excellent driving range or saturation signal margin even when the area of the photodiode is reduced on the layout, and accordingly, a design margin that can further reduce the area of the photodiode ( design margin).

In addition, since the floating diffusion region of the conventional CMOS image sensor is surrounded by the gate electrode, the present invention using the nitride spacer and the shadow effect is applicable to all CMOS image sensors.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The present invention described above has the effect of increasing the driving range by reducing the capacitance of the floating diffusion region.

In addition, in the highly integrated image sensor, the capacitance is reduced when the area of the photodiode is reduced, so that the magnitude of the voltage change ( ) Has the effect of suppressing the decrease.

In addition, by applying self-aligned contact etching using a spacer made of a nitride film, it is possible to secure an overlay margin of the contact mask to stabilize the process.

In addition, it is possible to secure a design margin that can further reduce the area of the photodiode.

Claims (6)

A semiconductor layer; First and second gate electrodes disposed on the semiconductor layer at a predetermined distance; A spacer in contact with both sidewalls of the first gate electrode and the second gate electrode; A photodiode in the semiconductor layer aligned with one edge of the first gate electrode; And A floating diffusion region in the semiconductor layer having one side overlapped by a spacer width in contact with the other side wall of the first gate electrode and the other side spaced apart from the edge of the spacer in contact with the side wall of the second gate electrode by the spacer width Image sensor comprising a. The method of claim 1, And a spacer in contact with both sidewalls of the first and second gate electrodes is a nitride film spacer. Simultaneously forming a first gate electrode and a second gate electrode disposed at a predetermined distance on the semiconductor layer; Forming a photodiode aligned in one edge of the first gate electrode in the semiconductor layer; Forming a spacer in which the first gate electrode and the second gate electrode are in contact with both sidewalls; And Forming a floating diffusion region in the semiconductor layer, the floating diffusion region having one side overlapped with a spacer width in contact with the other side wall of the first gate electrode and the other side spaced apart from the edge of the spacer in contact with the side wall of the second gate electrode by the spacer width; Steps to Method of manufacturing an image sensor comprising a. The method of claim 3, Forming the floating diffusion region, Forming a mask exposing a surface of the semiconductor layer between the first gate electrode and the second gate electrode; And Forming the floating diffusion region by implanting impurities in one direction while giving a tilt angle to the semiconductor layer exposed by the mask. Method of manufacturing an image sensor comprising a. The method of claim 3, Forming the spacers, Depositing a nitride film on the entire surface including the first gate electrode and the second gate electrode; And Etching the entire surface of the nitride film to form a nitride film spacer on both sidewalls of the first gate electrode and the second gate electrode; Method of manufacturing an image sensor characterized in that it further comprises. The method of claim 3, After forming the floating diffusion region, Forming a source / drain in the semiconductor layer exposed on the other side of the second gate electrode on the entire surface including the floating diffusion region; Forming an interlayer insulating film on the entire surface including the semiconductor layer; Selectively etching the interlayer insulating layer to form a contact hole self-aligned in the floating diffusion region; And Forming a metal contact to fill the contact hole Method of manufacturing an image sensor comprising a.