KR20030052639A - Image sensor with improved dark current and saturation characteristic and the method for fabricating the same - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to reduce dark current and to improve saturation property by forming a p0 region using a buffer layer. CONSTITUTION: A gate electrode(44) is formed on a semiconductor layer(41) having a field oxide layer(42). An n- doping region(45) is formed in the semiconductor layer(41) to arrange one edge of the gate electrode and edge of the field oxide layer. A spacer(46) is formed at both sidewalls of the gate electrode. A floating diffusion region(47) is formed in the semiconductor layer to arrange the spacer located at the other side of the gate electrode. A buffer layer(48) is formed on the resultant structure adjacent to the field oxide layer(42). Then, a p0 doping region(50) is formed on the n- doping region(45) to surround the field oxide layer.

Description

Image sensor with improved dark current and saturation characteristic and the method for fabricating the same}

BACKGROUND OF THE INVENTION ^1. Field of the Invention The present invention relates to an image sensor, and more particularly, to an improvement in characteristics of an image sensor by controlling a thickness of a p ⁰ region by using a buffer layer when forming a p ⁰ region.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. It is a device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and the CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. It is a device that adopts switching method to make MOS transistor and detect output by using it.

CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years.

The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel (Pixel) and sequentially detects a signal in a switching method. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor. have.

FIG. 1 is a schematic diagram of a unit pixel circuit of a CMOS image sensor, and includes one photodiode (PD) and four NMOS transistors, and four NMOS transistors float and spread photocharges collected at the photodiode (PD). A transfer gate Tx for transporting to the area FD, a reset gate Rx for resetting the floating diffusion area FD by setting a potential of the floating diffusion area and discharging electric charges to a desired value, and a source follower A drive gate Dx serving as a buffer source (Source Follower Buffer Amplifier) and a select gate Sx enabling addressing in a switching role. Outside the unit pixel, a load transistor is formed to read an output signal.

FIG. 2 is a diagram showing the cross-sectional structure of the photodiode region and the transfer gate Tx, wherein the photodiode is composed of p / n / p type photodiodes. Referring to FIG. 2, the p / n / p type photodiode has a p-type epitaxial layer 21 epitaxially grown on a p ⁺ substrate 20, and an n ⁻ region 25 inside the p-type epitaxial layer 21. ) Is formed, and the p ⁰ region 28 is formed above the n ⁻ region 25 and below the surface of the p-type epilayer 21.

If a reverse bias is applied between the n ⁻ region 25 and the p region (p ⁰ region, p type epi layer) of the photodiode of the above structure, when the impurity concentrations of the n ⁻ region 25 and the p region are properly combined, n ^- region 25 p-type epitaxial layer present on the lower 21 and the n ^{- -} region 25 is fully depleted n as presented (fully depletion) in region 25 p ⁰ region 28 present in the upper depletion As the region is expanded, more depletion layer expansion occurs to the p-type epi layer 21 having a relatively low dopant concentration.

Such a depletion region can accumulate and store photocharges generated by incident light and use the same to reproduce an image.

A transfer gate 24 and a gate spacer 26 are formed on the p-type epitaxial layer 21 having the field insulating layer 22 and the channel stop region 23 formed therein, and floating diffusion is formed on the other end substrate of the transfer gate Tx. Floating Diffusion (FD) 27 is formed. The channel stop region 23 formed below the field insulating film 22 is formed using B ₁₁ .

As described above, in the conventional image sensor, performance degradation and charge storage capability due to dark current have been pointed out as problems.

The dark current is generated by electrons moving from the photodiode to the floating diffusion region even in the absence of light, and these dark currents are mainly distributed at the bottom of the silicon surface, at p ⁰ / n ^- boundaries, or n ^- regions. point defects, etc.) or dangling bonds, and dark currents can cause serious problems in low-illumination environments.

A portion 29 indicated in the CMOS image sensor shown in FIG. 2 indicates a boundary between the field insulating film and the active region that causes the dark current. This area is the main area where dark current is induced because of the large number of defects or dangling bonds, and dark current is one of the main factors that lower the yield of current CMOS image sensor.

If the p ⁰ region 28 is deeply formed, the p ⁰ region 28 is formed to surround the defective portion of the edge portion of the field insulating layer 22, thereby reducing the dark current. The size of the n ⁻ region 25 is reduced (y decreases) by the p ⁰ region (x → x ′).

As the n− region 25 decreases, the size of the depletion layer also decreases, thereby lowering the charge storage capacity capable of storing photocharges generated by light (decreased saturation characteristics).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method of manufacturing an image sensor which reduces dark current and improves charge storage capability.

1 is a unit pixel circuit diagram of a CMOS image sensor;

2 is a cross-sectional view of a conventional transfer gate and photodiode portion, FIG.

3 to 6 are views illustrating a manufacturing process of an image sensor according to the present invention;

7A illustrates a doping profile of a p ⁰ region according to the prior art;

7B illustrates a doping profile of a p ⁰ region in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

40: p-type substrate 41: p epi layer

42: field insulating film 43: channel stop region

44 gate electrode 45 n ^- region

46: spacer 47: floating diffusion area

48: buffer layer 49: mask

50: p ⁰ region

The present invention for achieving the above object, the step of forming a gate electrode on a semiconductor layer formed with a field insulating film; Forming a first doped region of a second conductivity type in the semiconductor layer aligned with one edge of the gate electrode and an edge of the field insulating film; Forming spacers on both sidewalls of the gate electrode; Forming a second doped region of a second conductivity type in the semiconductor layer aligned with a spacer formed on the other side of the gate electrode; And forming a third doped region of a first conductivity type formed in the first doped region while surrounding the edge of the field insulating layer.

The present invention is an invention in which, unlike the formation of a thick p ⁰ ion implantation region using an ion implantation p ⁰ when the buffer layer at the same time to improve the dark current characteristic and charge storage capacity.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

3 to 6 are views illustrating a manufacturing process of an image sensor according to the present invention, and FIGS. 7A and 7B illustrate a doping profile of a p ⁰ region formed according to the prior art and the present invention, respectively, and will be described with reference to the drawings. First, as shown in FIG. 3, the transfer gate 44, the n-region 45, the spacer 46, and the floating diffusion region 47 are formed.

That is, polysilicon and tungsten silicide are successively coated and etched on the p-type semiconductor layer 41 having the field insulating layer 42 and the channel stop ion implantation region 43 to form the transfer gate 44.

At this time, the semiconductor layer is composed of a low concentration p-type epi layer 41 on the high concentration p-type substrate (40). The reason for this configuration is, firstly, that there is a low concentration of p-type epilayer, which can increase the depletion region in a large and deep low voltage photodiode, thereby increasing the ability of the low voltage photodiode to collect photocharges. The light sensitivity can be improved.

After the transfer gate 44 is formed, the n ⁻ region 45 is formed and the gate spacer 46 and the floating diffusion region 47 are formed. Until the floating diffusion region 47 is formed, the same technique as in the prior art is used.

Subsequently, a buffer layer 48 is formed on the entire surface of the substrate, as shown in FIG. Alternatively, the oxynitride film and the oxide film may be laminated and used.

In the case of p ⁰ ion implantation, when the ion implantation energy is 100 KeV, since the projection range (Rp) is about 1000 Hz, the depth of the p ⁰ region under the buffer layer 48 is about 100 to 200 Hz. The thickness of 48) is set to about 800 to 900 kPa.

Conventionally, ion implantation energy is about 30 KeV at the time of p ⁰ ion implantation. However, in the present invention, a high energy ion implantation process of about 100 KeV is performed to cover a defect portion near the field insulating layer to form a p ⁰ region. .

Since the buffer layer 48 serves as a full layer in the remaining portion except the field insulating film 42, the depth of the subsequently formed p ⁰ region is 100 to 200 占 so that the size of the n ⁻ region 45 is not reduced. do.

Next, as shown in FIG. 4, a mask 49 is formed to remove only a portion of the buffer layer from among the buffer layers 48 formed on the front surface of the substrate. As shown in FIG. 5, the buffer layer 48 at a portion about 0.1 to 0.15 mu m away from the edge portion of the field insulating film 42 is removed.

When the mask of this portion is removed, the depth of the p ⁰ region is deepened at the edge portion of the field insulating film 42 during subsequent p ⁰ ion implantation so as to cover the defective portion where dark current may occur.

Next, as shown in Fig. 6, p ⁰ ion implantation to form the region 50, a field insulating film (42) p ⁰ ion implantation area 50 is formed in the vicinity, since the buffer acts as a buffer layer 48, channel stop regions Together with (43), it is formed while covering the vicinity of the field insulating film 42 in which defect portions such as dangling binds are present.

p ⁰ ion implantation, is formed by blanking the ion implantation, it means to carry out the blanking (Blanking) ion implantation is ion implanted into the wafer surface without a mask, appropriate adjustment of the ion concentration and ion implantation energy by other than the zone The area can be adjusted to have little effect.

Thereafter, the buffer layer 48 is removed through a subsequent process and the rest of the process for manufacturing the image sensor is performed.

7A to 7B illustrate a doping profile of an area p ⁰ according to the prior art and a doping profile of an area p ⁰ according to the present invention. Compared with the prior art, in the photodiode region except for the vicinity of the field insulating film, FIGS. It can be seen that the depth of the p ⁰ ion implantation region according to the invention is shallow.

As described above, the p ⁰ region near the field insulating film is formed to be thick enough to cover the field insulating film, and the other portions are formed thin using the buffer layer, thereby improving the dark current characteristics and the charge storage capability.

In an embodiment of the present invention, the CMOS image sensor has been described as an example, but the present invention may be applied to all image sensors using a photodiode.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied to the image sensor, it is possible to achieve reduction of dark current and improvement of charge storage capacity at the same time, thereby preventing the deterioration of saturation characteristics due to high energy ion implantation and improving the characteristics of the image sensor.

Claims (9)

A semiconductor layer on which a field insulating film is formed; A first doped region of a second conductivity type formed in the semiconductor layer while being aligned with an edge of the field insulating film; A first region surrounding the edge of the field insulating layer and a second region having a smaller depth to the surface of the semiconductor layer than the first region, and a second doped region of a first conductivity type formed in the first doped region. Including, And an image depletion in the first doped region. Forming a gate electrode on the semiconductor layer on which the field insulating film is formed; Forming a first doped region of a second conductivity type in the semiconductor layer aligned with one edge of the gate electrode and an edge of the field insulating film; Forming spacers on both sidewalls of the gate electrode; Forming a second doped region of a second conductivity type in the semiconductor layer aligned with a spacer formed on the other side of the gate electrode; And Forming a third doped region of a first conductivity type formed in the first doped region while surrounding an edge of the field insulating layer; Method of manufacturing an image sensor comprising a. The method of claim 2, Forming a third doped region of a first conductivity type formed in the first doped region while surrounding an edge of the field insulating layer. Forming a buffer layer on the front surface of the substrate; Selectively etching the buffer layer so that only the buffer layer spaced apart from the edge of the field insulating layer remains; And And forming an ion implantation region of a first conductivity type on the resultant product. The method of claim 3, The buffer layer is a manufacturing method of the image sensor, characterized in that the thickness of 800 ~ 900Å. The method of claim 3, The buffer layer is an oxide film or an oxynitride film or a method of manufacturing an image sensor, characterized in that to use them laminated. The method of claim 3, In the step of forming the ion implantation region of the first conductivity type Ion implantation energy is 80 to 120 keV manufacturing method of the image sensor, characterized in that. The method of claim 3, A predetermined distance spaced apart from the edge of the field insulating film is 0.1 ~ 0.15㎛ manufacturing method of the image sensor. The method of claim 2, And the semiconductor layer is a semiconductor layer epitaxially grown on a semiconductor substrate having a dopant having a higher concentration than that of the semiconductor layer. The method of claim 2, The first conductive type to the second conductive type is a manufacturing method of the image sensor, characterized in that the complementary p-type or n-type.