KR100445027B1 - Method and apparatus for driving plasma display panel in which reset discharge is selectively performed - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a plasma display panel that selectively performs reset discharge in consideration of the wall charge distribution of discharge cells. The present invention relates to a cell having a condition in which a recording discharge can occur due to an address voltage in a recording period. In this case, a reset signal is not generated in the cell, and a reset signal is applied in the reset period so that a reset discharge occurs in a cell that is not, and the dark part can be further darkened by suppressing unnecessary discharge, thereby greatly improving contrast. In addition, the time required for the reset period can be reduced.

Description

Method and apparatus for driving plasma display panel in which reset discharge is selectively performed

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a plasma display panel for use in displaying an image on a television receiver or a computer monitor, and more particularly, to driving a plasma display panel selectively performing reset discharge in consideration of wall charge distribution of discharge cells. A method and apparatus therefor.

The panel driving timing can be divided into a reset (initialization) period, a write period, a sustain period, and an erase period. The reset period initializes the state of each cell so that the addressing operation can be performed smoothly on the cell, and the write period selects cells on the panel and cells not on the panel to accumulate wall charges. The sustain period performs a discharge for actually displaying an image on the addressed cell, and the erase period reduces the wall charge of the cell to terminate the sustain discharge.

Among the various quality-related items of the plasma display panel, it is very important to improve the contrast. Contrast is expressed as the brightness ratio of the bright and dark portions in the image displayed on the panel, where the bright portion is mainly composed of sustain discharge and the dark portion is composed of light generated by the reset discharge. To improve the contrast, you need to make the brighter parts brighter or the darker parts darker.

1 is a partial perspective view of an AC plasma display panel. On the first glass substrate 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 are paired and arranged in parallel. A plurality of address electrodes 8 covered with the insulator layer 7 are provided on the second glass substrate 6. On the insulator layer 7 between the address electrodes 8, partition walls 9 are formed in parallel with the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The first glass substrate 1 and the second glass substrate 6 have a discharge space 11 therebetween so that the scan electrode 4 and the address electrode 8 and the sustain electrode 5 and the address electrode 8 are orthogonal to each other. They are arranged to face each other. Discharge cells 12 are formed at the intersections of the address electrode 8 and the pair of the scan electrodes 4 and the sustain electrodes 5.

2 shows an electrode arrangement diagram of the panel. The electrodes have a matrix configuration of m columns x n rows. Address electrodes A1 to Am are arranged in the column direction, and n rows of scanning electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn are arranged in the row direction. The discharge cell shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

3 shows a drive waveform timing diagram of a panel driving method according to the prior art. In this driving method, one frame period is composed of eight subfields for display of 256 gray levels, and each subfield is composed of an initialization period, a recording period, a sustain period, and an erase period. The operation in the first subfield will be described.

In the reset period, all address electrodes A1 to Am and all sustain electrodes SUS1 to SUSn are held at 0V in the first half. The ramp voltage gradually rising from the voltage Vp (V) below the discharge start voltage to the sustain electrodes SUS1 to SUSn is applied to all the scan electrodes SCN1 to SCNn toward the voltage Vr (V) over the discharge start voltage. While this ramp voltage is rising, the first weak reset discharge occurs from the scan electrodes to the address electrodes and sustain electrodes in all the discharge cells. As a result, negative wall charges are accumulated on the surface of the protective film on the scan electrode. At the same time, positive wall charges are accumulated on the surface of the insulator on the address electrode and the surface of the protective film on the sustain electrode.

Then, in the second half of the reset period, all the sustain electrodes are held at the constant voltage Vh (V). All the scanning electrodes are supplied with a ramp voltage which falls gently toward 0 (V) over the discharge start voltage from the voltage Vq (V) which is less than or equal to the discharge start voltage. While the ramp voltage falls, the second weak reset discharge occurs from the sustain electrode to the scan electrode again in all the discharge cells. As a result, the negative wall voltage of the protective film surface on the scan electrode and the positive wall voltage of the protective film surface on the sustain electrode are weakened. Further, a weak discharge occurs between the address electrode and the scan electrode, and the positive wall voltage on the surface of the insulator layer on the address electrode is adjusted to a value suitable for the write operation. In this way, the reset operation of the reset period is completed.

In the next writing period, all scan electrodes are held at Vs (V) first. The positive write pulse voltage + Vw (V) is applied to the predetermined address electrode Aj (an integer of j = 1 to m) corresponding to the discharge cell to be displayed on the first row of the address electrodes, and the scan electrode SCN1 of the first row is provided. Scan pulse voltages of 0 (V) are applied simultaneously. At this time, the voltage between the surface of the insulator layer at the intersection of the predetermined address electrode Aj and the scan electrode SCN1 and the surface of the protective film on the scan electrode SCN1 is a positive wall of the surface of the insulator layer on the address electrode at the write pulse voltage + Vw (V). The voltage is added up. Therefore, at the intersection thereof, a write discharge occurs between the predetermined address electrode Aj and the scan electrode SCN1 and between the sustain electrode SUS1 and the scan electrode SCN1. Therefore, a positive wall voltage is accumulated on the surface of the protective film on the scanning electrode SCN1 at this intersection, a negative wall voltage is accumulated on the surface of the protective film on the sustain electrode SUS1, and a negative wall voltage is accumulated on the surface of the insulator layer on the address electrode Dj. do. This writing process is performed for every row.

When the recording period ends, the retention period continues. In the sustain period, all scan electrodes and sustain electrodes are set to 0 (V), and a positive sustain pulse + Vm (V) is applied to all scan electrodes. At this time, the voltage between the surface of the protective film on scan electrode SCNi (an integer of i = 1 to n) and the surface of the protective film on sustain electrode in the discharge cell that caused the recording discharge is the sustain pulse voltage and the scan electrode accumulated in the recording period. The positive wall voltage accumulated on the surface of the protective film on the SCN1 and the negative wall voltage accumulated on the surface of the protective film on the sustain electrode SUS1 are added, and the discharge start voltage is exceeded. For this reason, sustain discharge occurs between the scan electrode and sustain electrode in the discharge cell which caused the write discharge. A negative wall voltage is accumulated on the surface of the protective film on the scan electrode in the discharge cell which caused this sustain discharge, and a positive wall voltage is accumulated on the surface of the protective film on the sustain electrode. Thereafter, the sustain pulse voltage applied to the scan electrode returns to 0 (V). Subsequently, a positive sustain pulse voltage + Vm (V) is applied to all sustain electrodes, and sustain discharge occurs between the scan electrode and the sustain electrode in the discharge cell which has undergone the write discharge as described above. Thereafter, sustain discharge is performed by alternately inputting a positive sustain pulse voltage to all the scan electrodes and all sustain electrodes in the same manner. Visible light from the phosphor excited by the sustain discharge is used for display.

When the sustain period ends, a ramp voltage that rises slowly from 0 (V) to + Ve (V) is applied to all sustain electrodes in the erase period. At this time, in the discharge cell that caused the sustain discharge, the voltage between the protective film surface on the scan electrode and the protective film surface on the sustain electrode is the negative wall voltage of the protective film surface on the scan electrode appearing at the end of the sustain period and the protective film surface on the sustain electrode. This lamp voltage is added to the positive wall voltage. As a result, a weak erase discharge is generated between the sustain electrode and the scan electrode in the discharge cell causing the sustain discharge, and the negative wall voltage of the protective film surface on the scan electrode and the positive wall voltage of the protective film surface on the sustain electrode are weakened. The discharge is stopped. In this way, the erase operation is completed.

According to the prior art, the dark portion of the plasma display panel is composed of light generated by the reset discharge, which is generated in all cells starting one subfield. Accordingly, since reset discharge is generated in the discharge cells that should be turned off, light generated by the reset discharge is generated, thus reducing the contrast.

An object of the present invention is to provide a plasma display panel driving method and apparatus for improving contrast by performing a selective reset discharge during a panel display driving process so that darker portions are displayed darker.

1 is a partial perspective view of an AC plasma display panel.

2 shows an electrode arrangement diagram of the panel.

3 shows a drive waveform timing diagram of a panel driving method according to the prior art.

4 is a diagram showing a wall charge structure of a discharge cell provided with an addressing condition.

5A to 5C show an example in which the discharge cell does not satisfy the addressing condition.

6A and 6B illustrate the case where the discharge cells satisfy the addressing condition.

7 is a driving waveform timing diagram related to a method of driving a plasma display panel according to an embodiment of the present invention.

8 is a driving waveform timing diagram related to a method of driving a plasma display panel according to another exemplary embodiment of the present invention.

9 is a block diagram of an apparatus for driving a plasma display panel according to an embodiment of the present invention.

In order to achieve the above object, a method of driving a plasma display panel according to the present invention includes a reset period for initializing the state of each cell, a write period for selecting and addressing a cell to be turned on and an address cell which are not to be turned on during a sustain period, and an addressed cell. A method of driving a plasma display panel including a sustain period for discharging the light source, the method comprising: in the reset period, reset discharge does not occur in a cell having a condition in which a write discharge can occur due to an address voltage in the write period; In the uncelled cell, a reset signal is applied to cause a reset discharge. In the wall charge structure of the cell at the start of the reset period, even if an address voltage is applied in the write period, the wall charge cannot occur. Recording discharge in a cell or recording period having In born cells having a wall charge holding structure which causes a discharge in the sustain period even though the reset discharge in the reset period, it is preferable to raise up.

In order to achieve the above object, another method of driving a plasma display panel according to the present invention includes a reset period for initializing the state of each cell, a write period for selecting and addressing a cell to be turned on and a cell not to be turned on during a sustain period, and an addressed address. A method of driving a plasma display panel including a sustain period for discharging a cell, the method comprising applying a reset waveform in the reset period, applying a reset pulse of a predetermined voltage level in the early part of the reset period, and the voltage level in the latter part. It is characterized by applying a gradually decreasing ramp pulse, and based on the wall charge structure of the cell at the start of the reset period, the reset discharge does not occur in the cell where the write discharge can occur by the address voltage in the write period. Preferably, the voltage level of the reset pulse is set so that The.

In order to achieve the above object, a driving apparatus of a plasma display panel according to the present invention includes a reset signal generator for generating a reset signal for initializing the state of each cell; An address signal generator for generating an address signal for selecting and addressing cells to be turned on and cells not to be turned on during the sustain period; And a sustain signal generator for generating a sustain signal for discharging the cell addressed by the address signal generator, wherein the reset signal generator resets in a cell having a condition that address discharge by the address signal can be normally performed. Wherein the reset signal is generated such that a reset discharge occurs in a cell not otherwise discharged, and the reset signal generator applies a reset pulse of a predetermined voltage level at the beginning of the reset period, It is preferable to apply a ramp pulse whose level gradually decreases.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention provides a method of improving contrast by suppressing unnecessary reset discharge in a plasma display panel, wherein a reset discharge does not occur in a cell that satisfies an addressing condition during the reset period, and a reset discharge occurs only in a cell that does not satisfy the addressing condition. By minimizing the light generated in the dark part of the panel to improve the contrast. The reset time is a period in which the distribution of the wall charges is adjusted so that the write operation in the writing period can be performed smoothly by forming wall charges at appropriate polarities and amounts in the address electrodes, the sustain electrodes, and the scan electrodes, respectively. Here, the "addressing condition" refers to a condition under which a recording operation can be performed with high accuracy to distinguish a cell that should be turned on and a cell that should not be turned on during a sustain discharge period in a recording period. Therefore, a cell having a wall charge state capable of normal operation in a writing period and a sustaining period even without a reset discharge in the reset period is called a cell that satisfies the addressing condition, and a cell that does not satisfy the addressing condition is not. It is called.

In order for the discharge cell to satisfy the addressing condition, a large amount of negative charges are accumulated in the scan electrode, a large amount of positive charges are stored in the address electrode, and a suitable amount is applied to the sustain electrode according to the bias voltage applied to the sustain electrode during the writing period. A negative charge or a small amount of positive charge must be accumulated. In addition, the sustain electrodes and the scan electrodes must have wall charges that do not emit light during the sustain period when no recording discharge occurs in the discharge cells in the write period. Therefore, the reset discharge is not generated in the discharge cells satisfying the addressing conditions as described above, and the reset discharge is generated in the discharge cells not satisfying the addressing conditions, thereby changing the discharge cells to the discharge cells satisfying the addressing conditions.

4 is a diagram showing a wall charge structure of a discharge cell provided with an addressing condition. A large amount of negative charges are stored in the scan electrode Y, and a large amount of positive charges are stored in the address electrode A. The charges accumulated in these electrodes are applied to the address electrode during the writing period and the scan voltage is applied to the scan electrode. At this time, the address (write) discharge may occur or the wall voltage higher than that may be formed. At this time, an appropriate amount of negative charges or a small amount of positive charges may be stored in the sustain electrode X depending on the bias voltage applied to the sustain electrode during the recording period.

On the other hand, some examples of the case where the discharge cell does not satisfy the addressing conditions are as follows. That is, the wall voltage formed by the positive charge stored in the scan electrode and the negative charge accumulated in the address electrode (see FIG. 5A) or the negative charge accumulated in the scan electrode and the positive charge accumulated in the address electrode is lower than a predetermined reference value. This is the case where address (write) discharge does not occur even when the address voltage is applied to the electrode (see Fig. 5B). In addition, the case where a large amount of negative charges are accumulated in the sustain electrode and sustain discharge is generated during the sustain period even though the address discharge does not occur in the write period is also included in a broad sense (see FIG. 5C).

In the present invention, as shown in FIG. 4, the reset discharge is not generated in the discharge cell that satisfies the addressing condition, and the reset discharge is caused in the discharge cell that does not satisfy the addressing condition as in FIGS. 5A-5C. Such selective reset discharge can be achieved by applying the same reset pulse signal using the wall charge distribution of the discharge cells that satisfy the addressing condition and the discharge cells that do not, so that they have different discharge characteristics.

7 is a driving waveform timing diagram related to a method of driving a plasma display panel according to an embodiment of the present invention. One frame is composed of a plurality of subfields, and each subfield is divided into a reset period, a write period, a sustain period, and an erase period. Of course, the present embodiment may be applied to the case in which the frame has the subfield structure. However, the present embodiment may be similarly applied.

In the reset period, a square wave "reset pulse" is applied in the first half of the reset period, and in the second half, a "lamp pulse" that decreases linearly is applied. The sustain electrode is supplied with a constant voltage Vb, which may be set equal to or higher than the sustain discharge voltage Vm in the reset period, or set higher than or equal to the sustain discharge voltage Vm in the write period. . Then, 0 (V) is applied to the address electrode.

When the square wave reset pulse is applied to the scan electrode, no reset discharge occurs in the discharge cell that satisfies the addressing condition, but reset discharge occurs in the cell that does not satisfy the addressing condition, and a large amount of negative charge is applied to the scan electrode and a large amount of the negative charge to the address electrode. Positive charges can accumulate, and the amount of charge is such that an address discharge can occur when an address voltage is applied or can form a wall voltage higher than that (see FIG. 6A). Applying a ramp pulse that decreases linearly in the charge distribution of the electrode to the scan electrode maintains the voltage difference between the sustain electrode and the scan electrode properly, and the discharge cell has a wall charge structure that satisfies the addressing condition as shown in FIG. 6B. . A reset period having such a pulse structure may be performed at each start of each subfield, and in some cases, may be selectively performed or not selectively performed in a specific frame or a specific subfield.

When one frame is divided into a plurality of subfields to drive a panel, the voltage of the reset pulse applied in the reset period of the first subfield or some subfields of each frame, or in some of the frames of the plurality of frames. The voltage of the reset pulse applied in the reset period of one or a plurality of subfields can be set relatively higher than the voltage of the reset pulse applied in the other subfields. In other words, the voltage of the reset pulse in the reset period of each subfield can be the same in all subfields, but can be different depending on the position of the subfield. For example, the voltage of the reset pulse in the first subfield of every frame can be made relatively larger than that in the other subfields.

Next, the operation in the discharge cell in the reset period will be described separately for each case.

As shown in FIG. 4, when a square wave reset pulse is applied to a scan electrode of a discharge cell that satisfies an addressing condition, it is offset by a wall voltage formed between a scan electrode in which a large amount of negative charges are accumulated and an address electrode in which a large amount of positive charges are accumulated. The voltage actually applied between the scan electrode and the address electrode inside the discharge cell is lower than the voltage of the square wave reset pulse, and no discharge occurs in the discharge cell.

As in the case of FIG. 5A, in the case of a discharge cell in which positive charges are accumulated in the scan electrode and negative charges are stored in the address electrode, and the addressing condition is not satisfied, when the square wave reset pulse is applied to the scan electrode, the scan electrode and the address inside the discharge cell are applied. Since an electric field having the same polarity as that of the square wave reset pulse is formed between the electrodes, the voltage actually applied between the scan electrode and the address electrode in the discharge cell is equal to the sum of the square wave reset pulse voltage and the voltage formed by the wall charge. Therefore, a reset discharge may occur between the scan electrode and the address electrode, and as a result, a positive charge is accumulated at the address electrode and a negative charge is accumulated at the scan electrode. Next, when the lamp pulse is applied to the scan electrode, the discharge cell has a wall charge structure that satisfies the addressing condition.

As shown in FIG. 5B, in the case of a discharge cell in which the wall voltage formed between the scan electrode and the address electrode is lower than the reference value and no address (write) discharge occurs even when the address voltage is applied, the square wave wall voltage between the scan electrode and the address electrode is reduced. An internal electric field is formed, but its value is in a small state. When a voltage is applied to the scan electrode by the reset pulse, the voltage applied between the scan electrode and the address electrode is canceled by the wall voltage formed between the electrodes. However, the voltage level of the square wave reset pulse applied to the scan electrode is taken into consideration in consideration of the magnitude of the wall voltage. If it is larger than a certain level, reset discharge may occur between the scan electrode and the address electrode even if offset by the wall voltage occurs. As a result, a sufficient amount of positive charges are stored in the address electrode and a sufficient amount of negative charges in the scan electrode. Next, when the lamp pulse is applied to the scan electrode, the discharge cell has a wall charge structure that satisfies the addressing condition. In the above case, since the wall charges formed in the scan electrode and the address electrode are formed in the direction of canceling the electric field of the reset pulse, the reset pulse of the present invention, which must generate the reset discharge in a cell that does not satisfy the addressing condition, performs the reset discharge. It can be said to be a relatively difficult condition to generate. In FIG. 5B, the cell is reset even in other cases in which the addressing condition is not satisfied, that is, when the scan electrode and the address electrode have no wall charge or a wall charge of the same polarity is formed. It can generate a discharge.

Next, as shown in FIG. 5C, when a large amount of negative charge is accumulated in the sustain electrode and there is a possibility of malfunction, when a square wave reset pulse is applied to the scan electrode, a reset discharge is generated between the scan electrode and the sustain electrode by the reset pulse. Is generated, so that the negative charge accumulated in the sustain electrode excessively decreases. In the second half of the reset period, the wall charges at each electrode are appropriately adjusted by the lamp pulses applied to the scan electrodes, so that the discharge cells have a wall charge structure satisfying the addressing conditions.

When the reset period ends, the recording period and the sustain period are performed, and are driven in substantially the same manner as described in FIG. 3, and a detailed description thereof will be omitted. An erase operation is performed to erase the wall voltage formed by the sustain discharge in the sustain period in one subfield. As shown in FIG. 7, a ramp pulse that increases in advance in the erase period can be used, and the erase pulse can also be used. As a narrow pulse, a pulse lower than the sustain discharge voltage and wider than the width of the sustain discharge pulse, or a pulse of a logarithmic waveform may be used. Alternatively, the wall charges formed by the sustain discharge may not be erased.

8 is a driving waveform timing diagram related to a method of driving a plasma display panel according to another exemplary embodiment of the present invention. The signal waveform in the reset period is basically the same as in FIG. 7, but the sour pulse in the erase period is applied to the scan electrode in FIG. 7 but is applied to the scan electrode in FIG. 8. Except for this difference, the driving waveforms of FIGS. 7 and 8 are substantially the same, and the driving operation of the panel is also substantially the same.

9 is a block diagram of an apparatus for driving a plasma display panel according to an embodiment of the present invention. The analog image signal to be displayed on the panel 97 is converted into digital data and recorded in the frame memory 91. The frame generator 92 divides the digital data stored in the frame memory 91 as necessary and outputs them to the scanning circuit 94. For example, in order to display gradations on the panel, one frame of pixel data stored in the frame memory 91 is divided into a plurality of subfields according to the gradation level, and the data of each subfield is output.

The scanning circuit 94 scans the scan electrode Y drive 96 and the sustain electrode X drive 95 of the panel 97 and applies them to each electrode in the reset period, the write period, the sustain period and the erase period. A reset signal generator 942, a write pulse generator 943, a sustain pulse generator 944, and an erase pulse generator 941, which generate a signal waveform to be divided, are provided. That is, the reset signal generator 942 generates a reset signal for initializing the state of each cell, and the write pulse generator 943 generates an address signal for selecting and addressing a cell to be turned on and a cell that is not, and a sustain pulse generator. 944 generates a sustain signal for discharging the cells addressed by the write pulse generator 943, and the erase pulse generator 941 generates an erase pulse for erasing wall charges accumulated on the electrodes by the sustain discharge. In addition, a synthesizing circuit 945 for synthesizing these signals and supplying the respective signals is provided. The timing controller 94 generates various timing signals necessary for the operation of the frame generator 92 and the scanning circuit 94.

Next, the operation required for driving the panel according to the embodiment of the present invention, in particular, the operation in the reset period will be described in detail, and since it is possible to operate in the usual method in the remaining period, the detailed description thereof will be omitted.

The reset signal generator 942 applies the reset signal to the scan electrodes in the reset period as shown in FIG. 7 or 8. The reset signal generator 942 generates a reset discharge in a cell that satisfies an addressing condition, that is, a cell capable of accurately performing a recording operation during a recording period for distinguishing between a cell that should be turned on and a cell that should not be turned on in a sustain period. Does not occur, and a reset signal is generated so that reset discharge occurs in a cell that is not.

In order to perform such a function, it is preferable to apply a reset pulse of a predetermined voltage level in the early part of the reset period, and to apply a ramp pulse whose voltage level gradually decreases in the latter part. By doing so, in the wall charge structure of the cell at the start of the reset period, the sustain period even though no record discharge occurs in the cell or the write period having the wall charge structure in which the write discharge cannot occur even if an address voltage is applied in the write period. In a cell having a wall charge structure that causes a sustain discharge at, a reset discharge may occur in a reset period.

In the embodiment shown in Fig. 7 or 8, Vs = 170V (initial voltage of the reset period), V _set1 = 210V (voltage of the reset pulse in the first subfield), V _set2 = 200V (other than the first subfield) Voltages of reset pulses in other subfields), Vb = 180V (voltage of sustain electrode in reset period and write period), Va = 75V (address voltage), and Vsc = 70V (dielectric voltage) The operation of the will be described.

(a) First, in the case of a discharge cell that satisfies the addressing condition, the discharge is not generated by the reset pulse as follows.

Discharge there cell, the service charge is formed to enable the write discharge, the wall voltage due to wall charges accumulate wall voltage due to wall charges accumulated in this time the address electrode to V _aw1, the scan electrode as V _yw1 and address The discharge start voltage at which discharge can occur between the electrode and the scan electrode is defined as V _fay . During the writing period, the scan electrode maintains the ground voltage and assumes that the voltage applied to the address electrode is Va.

When the reset pulse is applied to the scan electrode, the internal voltage between the address electrode and the scan electrode is equal to the left side of the equation (1). Since the discharge cell has a wall charge structure that satisfies the addressing condition, the voltage between the two electrodes must not exceed the discharge start voltage and can be expressed by the following equation. That is, the value obtained by subtracting the wall voltage between the sustain electrode and the address electrode from the reset pulse voltage is smaller than the discharge start voltage.

On the other hand, since the wall charge structure of the discharge cell satisfies the addressing condition, the discharge is generated when an address voltage is applied to the discharge cell. Therefore, the voltage relationship at this time is expressed by the following equation.

Here, the value of the above equation is binarized to the right side and the left side minus the right side is alpha ( ) Can be written as:

Substituting Equation 4 into Equation 2, the relation for the reset pulse voltage can be expressed as follows.

(b) In the case of having a wall charge structure in which address discharge cannot occur in the writing period as shown in Fig. 5A or 5B, the wall voltage caused by the discharging charge of the scan electrode immediately before the reset pulse of the reset period is applied is set to V _yw2 . The wall voltage caused by the wall charge is called V _aw2 , and other variables are the same as in the case of (a). When the reset pulse is applied, the internal electric field between the address electrode and the scan electrode becomes as shown in the left side of the following equation, and the following conditions must be satisfied for the reset discharge to occur between the address electrode and the scan electrode due to the reset pulse in the reset period. do. That is, the value obtained by adding the reset pulse voltage to the wall voltage between the scan electrode and the address electrode is equal to or larger than the discharge start voltage.

On the other hand, in the current wall charge structure, since recording discharge cannot occur in the recording period, the following conditions are satisfied during the recording period. That is, even when the address voltage is applied to the address electrode in the writing period, the voltage between the scan electrode and the address electrode is smaller than the discharge start voltage.

Substituting Equation 9 into Equation 7, the expression for the reset pulse voltage can be expressed as follows.

(c) In the case of having a wall charge structure as shown in FIG. 5C, that is, when the potential of the sustain electrode becomes ground at the end of the recording period, excessive negative charge is formed on the sustain electrode so that a discharge occurs between the address electrode and the sustain electrode. Look for cases of malfunction. In the case of having such a wall charge structure, in the present invention, discharge is generated between the sustain electrode and the scan electrode by the reset pulse to remove excess negative charge accumulated in the sustain electrode. Then, positive charges accumulate on the sustain electrodes, and since the positive charges accumulated on the sustain electrodes can be erased by the lamp pulses during the reset period, they do not affect the recording operation. Rather, an appropriate electric field is formed between the sustain electrodes and the scan electrodes. It may also act in favor of operation.

The wall voltage due to the _subordinate charge of the scan electrode immediately before the reset pulse is applied during the reset period is referred to as V _yw3 , and the wall voltage due to the wall charge of the address electrode is referred to as V _aw3 . When falling to ground, the wall voltage caused by the change of the sustain electrode to allow discharge between the address electrode and the sustain electrode is Vxx, the discharge start voltage between the address electrode and the sustain electrode is V _fax , and the discharge start voltage between the scan electrode and the sustain electrode. In the case of V _fxy , the conditions when an _error discharge occurs between the address electrode and the sustain electrode are as follows.

In order to generate a discharge between the sustain electrode and the scan electrode by the reset pulse, the following conditions must be satisfied.

Substituting Equation 12 into Equation 13 results in the following.

E.g, Then, from the equation (5), the voltage condition of the reset pulse is expressed as follows. That is, the condition that no reset discharge occurs in the discharge cell that satisfies the addressing condition is expressed by Equation (15).

Next, as shown in FIG. 5A or 5B, a condition for causing a reset discharge to occur in a discharge cell that does not satisfy the addressing condition is as follows from Equation 10.

In addition, in the case of a discharge cell in which discharge malfunction may occur, as shown in FIG. 5C, when discharge is generated by a reset pulse in the discharge cell under the assumption that V _aw1 = 70 V and V _yw2 = _-80 V, the following conditions must be satisfied. do.

When the voltage of the reset pulse is set according to the condition of Equation 15-17, the reset discharge does not occur in the cell that satisfies the addressing condition, but the reset discharge occurs in the cell that does not satisfy the addressing condition. That is, under the premise that the voltage of the reset pulse is smaller than the value on the right side of Equation 15, the conditions of Equation 16 in FIGS. 5A and 5B and 17 in FIG. 5C must be satisfied. Therefore, the voltage range of the reset pulse is set in consideration of the structure of the electrode, the distribution of the discharging charges, and the like, and the condition of the above equation so that the selective charge discharge is made even if the wall charge structure of the discharge cell is different from that shown in FIGS. 4 or 5A-5C. In this range, the voltage of the reset pulse may be appropriately selected and applied.

However, consider the case where the wall voltage of a cell satisfying the addressing condition deviates from the addressing condition due to the natural wall charge loss over time, or the discharge start voltage varies slightly from cell to cell due to the variation of the physical characteristics of the cell. By securing a certain range of α, β, and γ in Equation 15, Equation 16, and Equation 17, it is advantageous to secure the operation range of the waveform. In the subfield of, the voltage of the reset pulse is set slightly higher than that in the other subfields. In the subfield, even if the reset discharge occurs in some of the cells that satisfy the addressing condition, It is in terms of panel operation that the reset discharge occurs in ambiguous cells with a boundary level condition. It may be advantageous.

When the reset period was performed according to the conventional method shown in FIG. 3, the contrast was about 500: 1. However, when the reset period was performed according to the embodiment of the present invention, the contrast was improved to 15000: 1. . In the reset period, the conventional method is about 290 * 12 = 3480us, but in the embodiment of the present invention, it is about 120 * 12 = 1440 us, and according to the present invention, since the reset discharge occurs selectively, the time required for the reset period is set. It can be reduced to about 41%.

As described above, according to the method and apparatus for driving a plasma display panel according to the present invention, while reset discharge does not occur in a cell having an addressing condition in a reset period, a reset discharge is caused only in a cell that is not, thereby suppressing unnecessary discharge. To darken dark areas. Therefore, the contrast can be greatly improved, and the time required for the reset period can also be reduced.

Claims (14)

A method of driving a plasma display panel comprising a reset period for initializing the state of each cell, a writing period for selecting and addressing cells that should be turned on in the sustain period, and a sustaining period for discharging the addressed cells, the method comprising: In the reset period, a reset signal is applied so that a reset discharge does not occur in a cell having a condition where a write discharge can occur due to an address voltage in the write period, and a reset discharge occurs in a cell that does not. How to drive the display panel. 2. The wall charge structure of a cell at the start of a reset period, wherein a write discharge does not occur in a cell or a recording period having a wall charge structure in which write discharge cannot occur even if an address voltage is applied in the write period. And a reset discharge occurs in the reset period in a cell having a wall charge structure which causes a sustain discharge in the sustain period even though it is not. The method according to claim 1, wherein a large amount of negative charges are stored in the scan electrode, a large amount of negative charges are stored in the address electrode, and a small amount of negative charges or an appropriate amount of positive charges are stored in the sustain electrode. A method of driving a plasma display panel, wherein a reset discharge does not occur in a cell where a write discharge can occur when an address voltage is applied to the electrode. 2. The drive of a plasma display panel according to claim 1, wherein a positive discharge is generated in the scan electrode and a negative charge is accumulated in the address electrode so that reset discharge occurs in a cell in which no write discharge occurs even when an address voltage is applied in the write period. Way. 2. The reset discharge of claim 1, wherein the wall voltage formed by the negative charges accumulated in the scan electrode and the positive charges accumulated in the address electrode is lower than a predetermined reference value so that the reset discharge is not generated even when the address discharge is applied even in the writing period. And a plasma display panel driving method. The method of driving a plasma display panel according to claim 1, wherein reset discharge occurs in a cell in which the wall charges are substantially not formed on the scan electrode and the address electrode or the wall charges of the same polarity are formed. The method of driving a plasma display panel according to claim 1, wherein a reset discharge occurs in a cell in which sustain discharge occurs in the sustain period even though no address discharge occurs in the write period. The method according to claim 1, wherein when one frame is divided into a plurality of subfields to drive a panel, the first subfield or part of a subfield of each frame, and one or more subfields in a part of a plurality of frames. And the voltage of the reset pulse applied in the reset period of the field is set relatively higher than the voltage of the reset pulse applied in the other subfield. A method of driving a plasma display panel comprising a reset period for initializing the state of each cell, a write period for selecting and addressing cells that are to be turned on in the sustain period, and a sustain period for discharging the addressed cells, the method comprising: A reset waveform is applied in the reset period, wherein a reset pulse of a predetermined voltage level is applied at an early part of the reset period, and a ramp pulse of gradually decreasing voltage level is applied at a later part of the reset period. 10. The voltage of the reset pulse in the reset period of the other subfield when the frame is driven by dividing one frame into a plurality of subfields. A driving method of a plasma display panel, characterized in that it is larger than the level. 10. The plasma display panel as claimed in claim 9, wherein in the reset period, the voltage level of the reset pulse is set so that reset discharge does not occur in a cell in which write discharge can occur due to an address voltage in the write period. Driving method. A reset signal generator for generating a reset signal for initializing the state of each cell; An address signal generator for generating an address signal for selecting and addressing cells to be turned on and cells not to be turned on; And A sustain signal generator for generating a sustain signal for discharging the cells addressed by the address signal generator, The reset signal generator generates a reset signal such that a reset discharge does not occur in a cell having a condition in which an address discharge by the address signal can be normally performed, and a reset discharge occurs in a cell not otherwise. Drive of display panel. The method of claim 12, wherein the reset signal generator A driving device for a plasma display panel, wherein a reset pulse of a predetermined voltage level is applied at the beginning of the reset period, and a lamp pulse of gradually decreasing voltage level is applied at the later part. The method of claim 12, wherein the reset signal generator A driving apparatus of a plasma display panel, wherein a state of a cell at the start of a reset period causes a reset discharge to occur in a cell having a condition in which a sustain discharge can occur even though a write discharge has not occurred in the write period.