KR100437452B1 - Phase changeable memory cells and methods of fabricating the same - Google Patents

Abstract

Phase change memory cells and methods of manufacturing the same are provided. These phase conversion memory cells have a plurality of first and second information storage elements arranged two-dimensionally on a semiconductor substrate. The first information storage elements are located at points where even rows and even columns intersect and points where odd rows and odd columns intersect, and second information storage. The elements are located at points where odd rows and even columns intersect and points where even rows and odd columns intersect. A plurality of parallel plate lines are arranged to pass over the first and second information storage elements. The plate lines consist of first and second plate lines. The first plate lines are electrically connected with the first information storage elements but arranged parallel to the diagonal, and the second plate lines are disposed between the first plate lines and electrically connected with the second information storage elements.

Description

Phase changeable memory cells and methods of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to phase change memory cells and a method of manufacturing the same.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power supply is cut off. Such nonvolatile memory devices mainly employ flash memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode sequentially stacked on a channel. Therefore, in order to improve the reliability and program efficiency of the flash memory cells, the film quality of the tunnel oxide film should be improved and the coupling ratio of the cells should be increased.

Instead of the flash memory devices, new nonvolatile memory devices such as phase change memory devices have recently been proposed.

1 shows an equivalent circuit diagram of a unit cell of the phase change memory devices.

Referring to FIG. 1, the phase change memory cell includes one access transistor T _A and one variable resistor C. Referring to FIG. The variable resistor C includes a lower electrode, an upper electrode, and a phase changeable material layer interposed therebetween. The upper electrode of the variable resistor C is connected to the plate electrode PL. In addition, the access transistor T _A includes a source region connected to the lower electrode, a drain region spaced apart from the source region, and a gate electrode positioned on a channel region between the source region and the drain region. do. The gate electrode and the drain region of the access transistor T _A are connected to a word line WL and a bit line BL, respectively. As a result, the equivalent circuit diagram of the phase change memory cell is similar to the equivalent circuit diagram of the DRAM cell. However, the nature of the phase change material film is completely different from that of the dielectric film employed in the DRAM cell. That is, the phase change material film has two stable states according to temperature.

2 is a graph for explaining a method of programming and erasing the phase change memory cells. Here, the horizontal axis represents time T, and the vertical axis represents temperature TMP applied to the phase change material film.

Referring to FIG. 2, when the phase change material film is heated after cooling for a first duration T1 at a temperature higher than a melting temperature Tm, the phase change material film is in an amorphous state. (See curve ①). In contrast, the phase change material film is heated for a second duration T2 longer than the first period T1 at a temperature lower than the melting temperature Tm and higher than a crystallization temperature Tc. Upon cooling, the phase change material film changes to a crystalline state (see curve ②). Here, the specific resistance of the phase change material film having an amorphous state is higher than that of the phase change material film having a crystalline state. Accordingly, by detecting the current flowing through the phase change material film in the read mode, it is possible to discriminate whether the information stored in the phase change memory cell is a logic "1" or a logic "0". As the phase change material film, a compound material layer (hereinafter, referred to as a 'GTS film') containing germanium (Ge), tellurium (Te), and stevilium (Sb) is widely used.

3 is a cross-sectional view showing conventional phase change memory cells.

Referring to FIG. 3, an isolation layer 13 defining an active region is disposed in a predetermined region of the semiconductor substrate 11. A pair of parallel word lines 15 are disposed across the active region. Impurity regions are formed in the active region positioned at both sides of the pair of word lines 15. An impurity region formed in an active region between the pair of word lines 15 corresponds to a common drain region 17d, and impurity regions adjacent to both sides of the common drain region 17d correspond to source regions 17s. do. The entire surface of the semiconductor substrate having the source / drain regions 17s and 17d, the word lines 15, and the device isolation layer 13 is covered with a first interlayer insulating layer 19. A bit line 21 electrically connected to the common drain region 17d is disposed on the first interlayer insulating layer 19. Although only a portion of the bit line 21 is shown in the figure, the bit line 21 crosses the upper portion of the word lines 15.

The entire surface of the semiconductor substrate including the bit line 21 is covered with a second interlayer insulating film 23. A pair of contact plugs 25 electrically connected to the respective source regions 17s are disposed in the second interlayer insulating layer 23. A pair of phase changeable material layer patterns 27 is disposed on the second interlayer insulating layer 23. Each of the phase change material layer patterns 27 covers the contact plugs 25. Upper electrodes 29 are stacked on the phase change material layer patterns 27. The gap regions between the phase change material layer patterns 27 are filled with the planarized interlayer insulating layer 31. The planarized interlayer insulating film 31 and the upper electrodes 29 are covered with a plate electrode 33.

When a program voltage is selectively applied to the contact plug 25 of the cell A to program one cell A of the pair of phase change memory cells, the phase change material film pattern of the cell A Heat is generated at the interface between the 27 and the contact plug 25. Accordingly, a portion 27a of the phase change material film pattern 27 of the selected cell A is changed to an amorphous state. In this case, heat generated in the selected cell A is transferred to the phase change material film pattern 27 of the unselected cell B through the conductive plate electrode 33 and / or the planarized interlayer insulating layer 31. Can be delivered. In this case, a portion 27b of the phase change material film pattern 27 of the unselected cell B also changes to an amorphous state. As a result, the unselected cell B can be weakly programmed due to a thermal interference phenomenon. This thermal interference phenomena (appear) is more severe as the gap between the pair of cells (A, B) becomes narrower.

As described above, conventional phase change memory cells are formed at the same level with each other. Thus, when selectively programming one phase change memory cell, an unselected cell neighboring the selected cell can be programmed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide phase change memory cells suitable for minimizing thermal interference between neighboring cells and manufacturing methods thereof.

Another object of the present invention is to provide phase change memory cells suitable for increasing thermal transmission paths between neighboring cells and methods of manufacturing the same.

Another object of the present invention is to provide phase change memory cells suitable for highly integrated phase change memory devices and methods of manufacturing the same.

1 is an equivalent circuit diagram of a unit cell of a typical typical phase changeable memory device.

2 is a graph for explaining the characteristics of the phase change material employed in the phase change memory cell.

3 is a cross-sectional view showing conventional phase change memory cells.

4 is a plan view of phase change memory cells according to the present invention.

5 is a cross-sectional view of a phase change memory cell according to an exemplary embodiment of the present invention, which corresponds to a cross-sectional view taken along the line I-I of FIG. 4.

6 is a cross-sectional view of a phase change memory cell according to another exemplary embodiment of the present invention, which corresponds to a cross-sectional view taken along the line I-I of FIG. 4.

7A to 9A are cross-sectional views illustrating a method of manufacturing phase change memory cells according to an embodiment of the present invention according to I-I of FIG. 4.

7B to 9B are cross-sectional views illustrating a method of manufacturing phase change memory cells according to an embodiment of the present invention in accordance with II-II of FIG. 4.

FIG. 10A is a cross-sectional view illustrating a method of manufacturing a phase change memory cell according to another embodiment of the present invention in accordance with FIG.

FIG. 10B is a cross-sectional view for describing a method of manufacturing a phase change memory cell according to another embodiment of the present invention according to II-II of FIG. 4.

According to one aspect of the present invention, phase-change memory cells are provided. The phase change memory cells include a plurality of data storage elements arranged two-dimensionally along rows and columns on a semiconductor substrate. The information storage elements may include first information storage elements formed at points where even rows and even columns intersect, and points where odd rows and odd columns intersect. And second information storage elements formed at points where even rows and odd columns intersect and points where odd rows and even columns intersect. . A plurality of plate lines parallel to a diagonal line are disposed on the information storage elements. The plate lines are composed of a plurality of first plate lines electrically connected to the first information storage elements and a plurality of second plate lines electrically connected to the second information storage elements. Each of the information storage elements includes a phase change material film pattern and an upper electrode stacked in sequence. That is, each of the first information storage elements includes a first phase change material film pattern and a first upper electrode that are sequentially stacked, and each of the second information storage elements each includes a second phase change material film pattern and It includes a second upper electrode.

The first and second plate lines are located at the same level. Alternatively, the second plate lines may be located at a higher level than the first plate lines.

According to another aspect of the present invention, a method of manufacturing phase change memory cells is provided. This method includes forming a plurality of information storage elements arranged two-dimensionally on a semiconductor substrate. The information storage elements may include first information storage elements formed at points where even rows and even columns intersect, and points at which odd rows and odd columns intersect, as well as points and odd rows where even and odd columns intersect. And second information storage elements formed at points where even columns intersect. A plurality of plate lines are formed across the top of the information storage elements and parallel to the diagonal. The plate lines are electrically connected to the first and second information storage elements.

The forming of the plate lines may include forming a first interlayer insulating film on an entire surface of the semiconductor substrate having the plurality of information storage elements, and patterning the first interlayer insulating film to expose the first and second information storage elements, respectively. And forming second contact holes, forming a conductive film on the entire surface of the resultant, and patterning the conductive film.

Alternatively, forming the plate lines may include forming a middle interlayer insulating film on a front surface of the semiconductor substrate having the plurality of information storage elements, and patterning the interlayer insulating film to expose the first information storage elements. Forming a plurality of first parallel plate lines parallel to a diagonal line and covering the first contact holes on the intermediate interlayer insulating film, and forming an upper interlayer insulating film on a front surface of the semiconductor substrate having the first plate lines. Form second contact holes exposing the second information storage elements by successively patterning the upper interlayer insulating film and the intermediate interlayer insulating film, and parallel to the first plate lines on the upper interlayer insulating film. Forming a plurality of second parallel plate lines covering the second contact holes It may also include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents can be thorough and complete, and the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

4 is a plan view illustrating a portion of a cell array region of a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a plurality of active regions 53a arranged two-dimensionally on a semiconductor substrate are disposed. A plurality of parallel word lines 55 are disposed across the active regions 53a. The word lines 55 run parallel to the x axis. Each of the active regions 53a intersects a pair of word lines 55. Accordingly, each of the active regions 53a is divided into three regions by the pair of word lines 55. The active region 53a between the pair of word lines 55 corresponds to a common drain region, and active regions positioned at both sides of the common drain region correspond to source regions. The source regions are located at positions where rows parallel to the x-axis and columns parallel to the y-axis intersect. The common drain regions are electrically connected to the bit lines 63 through the bit line contact holes 61. The bit lines 63 run parallel to the y axis.

A plurality of data storage elements are arranged two-dimensionally on the source regions. The information storage elements include first information storage elements 74a and second information storage elements 74b. The first information storage elements 74a are located at points where even rows and even columns intersect and points where odd rows and odd columns intersect. The second information storage elements 74b may be formed at intersections of even rows and odd columns and intersections of odd rows and even columns. Located. The first and second information storage elements 74a and 74b are electrically connected to the source regions through storage node contact holes 69a.

A plurality of plate lines are disposed across the top of the first and second information storage elements 74a and 74b. The plate lines are arranged parallel to the diagonal and consist of first plate lines 81a or 81a 'and second plate lines 81b or 89. Each of the first plate lines 81a or 81a 'is electrically connected to the first information storage elements 74a arranged diagonally through the first contact holes 77a or 77a'. Similarly, each of the second plate lines 81b or 89 is electrically connected to second information storage elements 74b arranged diagonally through second contact holes 77b or 85. Here, the first and second plate lines 81a and 81b are located at the same level as each other. In this case, the first plate lines 81a are electrically connected to the first information storage elements 74a through the first contact holes 77a and the second plate lines 81b. Is electrically connected to the second information storage elements 74b through the second contact holes 77b.

The second plate lines 89 may be located at a level higher than the first plate lines 81a '. In this case, the first plate lines 81a 'are electrically connected to the first information storage elements 74a through the first contact holes 77a', and the second plate lines 81a 'are electrically connected to each other. 89 is electrically connected to the second information storage elements 74b through the second contact holes 85.

As a result, a pair of information storage elements adjacent to each other are connected by a plate line parallel to the diagonal. Accordingly, the distance D between the pair of information storage elements adjacent to each other through the plate line may be expressed by the following equation.

Here, R denotes a distance between rows adjacent to each other, and C denotes a distance between columns adjacent to each other.

As can be seen from the above equation, the spacing D between a pair of information storage elements neighboring each other through the plate line is increased as compared with the prior art. Therefore, even if heat is generated in the storage node contact plug of the selected cell to selectively program one cell, the phenomenon that the unselected cell adjacent to the selected cell is programmed can be significantly suppressed.

FIG. 5 is a cross-sectional view of a phase change memory cell according to an exemplary embodiment of the present invention, and corresponds to a cross-sectional view taken along the line I-I of FIG. 4.

Referring to FIG. 5, a lower interlayer insulating film 68 is disposed on the semiconductor substrate 51. The lower interlayer insulating layer 68 may include a lower insulating layer 66 and a chemical mechanical polishing stop layer 67 that are sequentially stacked. The lower insulating film 66 is preferably a silicon oxide film, and the chemical mechanical polishing blocking film 67 is preferably a silicon nitride film. The lower interlayer insulating layer 68 is penetrated by the plurality of storage node contact plugs 69. The storage node contact plugs 69 are in contact with predetermined regions of the semiconductor substrate 51 and are two-dimensionally disposed along rows and columns. The storage node contact plugs 69 are covered by a plurality of information storage elements. The information storage elements include first information storage elements 74a and second information storage elements 74b. The first information storage elements 74a cover the storage node contact plugs 69 positioned at points where even rows and even columns intersect and points where odd rows and odd columns intersect. Further, the second information storage elements 74b cover the storage node contact plugs 69 positioned at points where even rows and odd columns intersect and points where odd rows and even columns intersect. Each of the first information storage elements 74a includes a first phase change material film pattern 71a and a first upper electrode 73a that are sequentially stacked, and each of the second information storage elements 74b. Includes a second phase change material layer pattern 71b and a second upper electrode 73b that are sequentially stacked.

An entire surface of the semiconductor substrate having the first and second information storage elements 74a and 74b is covered by an intermediate interlayer insulating film 75. A plurality of plate lines parallel to the diagonal line are disposed on the intermediate interlayer insulating film 75 (see FIG. 4). The plate lines may include a plurality of first plate lines 81a electrically connected to the first upper electrodes 73a and a plurality of second plate lines electrically connected to the second upper electrodes 73b. (81b). The first plate lines 81a are electrically connected to the first upper electrodes 73a through a plurality of first contact holes 77a passing through the intermediate interlayer insulating layer 75. The plate lines 81b are electrically connected to the second upper electrodes 73b through the plurality of second contact holes 77b passing through the intermediate interlayer insulating layer 75. In addition, the first and second contact holes 77a and 77b may be filled by the first and second contact plugs 79a and 79b, respectively.

Although not shown in the drawing, the intermediate interlayer insulating film 75 may fill only a gap region between the first and second information storage elements 74a and 74b. In this case, the first and second plate lines 81a and 81b are in direct contact with the first and second upper electrodes 73a and 73b, respectively.

FIG. 6 is a cross-sectional view of a phase change memory cell according to another embodiment of the present invention and corresponds to a cross-sectional view taken in accordance with II of FIG. 4.

Referring to FIG. 6, first and second information storage elements 74a and 74b are two-dimensionally disposed on the semiconductor substrate 51 as in the first embodiment of FIG. 5. The first and second information storage elements 74a and 74b have the same form as those of the first embodiment described in FIG. The front surface of the semiconductor substrate having the first and second information storage elements 74a and 74b is covered with an intermediate interlayer insulating film 75. A plurality of first plate lines 81a ′ are disposed on the intermediate interlayer insulating layer 75 to be parallel to the diagonal lines (see FIG. 4). The first plate lines 81a 'are electrically connected to the first upper electrodes 73a through a plurality of first contact holes 77a' passing through the intermediate interlayer insulating layer 75. In addition, the first contact holes 77a 'may be filled with first contact plugs 79a'.

An entire surface of the semiconductor substrate having the first plate lines 81a 'is covered with an upper interlayer insulating layer 83. A plurality of second plate lines 89 parallel to the first plate lines 81a ′ are disposed on the upper interlayer insulating layer 83. The second plate lines 89 are electrically connected to the second upper electrodes 73b through second contact holes 85 passing through the upper interlayer insulating layer 83 and the intermediate interlayer insulating layer 75. do. The second contact holes 85 may be filled with second contact plugs 87.

As a result, according to the second embodiment of the present invention, the second plate lines are located at a higher level than the first plate lines. Accordingly, the alignment margin may be increased in the gap between the first and second plate lines.

Next, a method of manufacturing phase change memory cells according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7A to 9A and 7B to 9B. 7A to 9A are cross-sectional views taken along the line II of FIG. 4, and FIGS. 7B to 9B are cross-sectional views taken along the line II-II of FIG. 4.

4, 7A, and 7B, an isolation layer 53 is formed in a predetermined region of the semiconductor substrate 51 to define a plurality of active regions 53a. The active regions 53a are two-dimensionally arranged as shown in FIG. 4. A plurality of parallel word lines 55 are formed to cross the upper portions of the active regions 53a. The word lines 55 are insulated from the active regions 53a by a gate insulating layer (not shown). In addition, the word lines 55 are formed to be parallel to the x-axis, that is, a row, as shown in FIG. 4. Impurity ions are implanted into the active regions 53a using the word lines 55 and the device isolation layer 53 as ion implantation masks. As a result, a pair of source regions 57s are formed in each of the active regions 53a, and a common drain region 57d is formed between the pair of source regions 57s. The source regions 57a are formed at points where rows and columns intersect. Accordingly, the source regions 57a are formed to be two-dimensionally arranged.

A first lower insulating layer 59 is formed on the entire surface of the semiconductor substrate having the common drain regions 57d and the source regions 57s. The first lower insulating film 59 is preferably formed of a silicon oxide film. The first lower insulating layer 59 is patterned to form a plurality of bit line contact holes (61 in FIG. 4) exposing the common drain regions 57d. A conductive film is formed on the entire surface of the semiconductor substrate having the bit line contact holes 61, and the conductive film is patterned to form a plurality of parallel bit lines 63 covering the bit line contact holes 61. do. The bit lines 63 are formed to be parallel to the y-axis, that is, a column, as shown in FIG. 4. In addition, the bit lines 63 are electrically connected to the common drain regions 57d through the bit line contact holes 61.

A second lower insulating layer 65 and a chemical mechanical polishing stop layer 67 are sequentially formed on the entire surface of the semiconductor substrate having the bit lines 63. The second lower insulating film 65 is preferably formed of a silicon oxide film. The chemical mechanical polishing stop layer 67 is preferably formed of a silicon nitride film. The first lower insulating layer 59 and the second lower insulating layer 65 constitute a lower insulating layer 66. In addition, the lower insulating layer 66 and the chemical mechanical polishing stop layer 67 constitute a lower interlayer dielectric layer 68.

4, 8A, and 8B, the lower interlayer insulating layer 68 is patterned to form a plurality of storage node contact holes (69a of FIG. 4) exposing the source regions 57s. A conductive film is formed on the entire surface of the semiconductor substrate having the storage node contact holes 69a. The conductive film is preferably formed of a titanium nitride film (TiN), a titanium aluminum nitride film (TiAlN), a titanium silicon nitride film (TiSiN), a tantalum aluminum nitride film (TaAlN), or a tantalum silicon nitride film (TaSiN). Next, the conductive layer is planarized until the chemical mechanical polishing stop layer 67 is exposed to form storage node contact plugs 69 in the storage node contact holes 69a. The planarization process can be carried out using a chemical mechanical polishing technique.

The storage node contact plugs 69 include storage node contact plugs of a first group and storage node contact plugs of a second group. The storage node contact plugs of the first group are formed at points where even rows and even columns intersect, and points where odd rows and odd columns intersect, and the storage node of the second group. Contact plugs are formed at points where even rows and odd columns intersect and points where odd rows and even columns intersect. A phase change material film and an upper electrode film are sequentially formed on the entire surface of the semiconductor substrate having the storage node contact plugs 69. The phase change material film may be formed of a GTS film. In addition, the upper electrode layer may be formed of a titanium nitride layer (TiN).

The upper electrode layer and the phase change material layer are successively patterned to form a plurality of information storage elements covering the storage node contact plugs 69. The information storage elements include first information storage elements 74a covering the first group of storage node contact plugs and second information storage elements 74b covering the second group of storage node contact plugs. Each of the first information storage elements 74a includes a first phase change material film pattern 71a and a first upper electrode 73a that are sequentially stacked, and each of the second information storage elements 74b. The second phase conversion material film pattern 71b and the second upper electrode 73b are sequentially stacked. An intermediate interlayer insulating film 75 is formed on the entire surface of the semiconductor substrate having the first and second information storage elements 74a and 74b.

4, 9A, and 9B, the first contact holes 77a and the second upper electrodes 75 may be formed by patterning the intermediate interlayer insulating layer 75 to expose the first upper electrodes 73a. Second contact holes 77b exposing 73b) are formed. The first contact plugs 79a and the second contact plugs 79b may be formed in the first and second contact holes 77a and 77b using a conventional method, respectively. A plate film is formed on the entire surface of the semiconductor substrate having the first and second contact plugs 79a and 79b. The plate film is patterned to form a plurality of plate lines parallel to the diagonal line. The plate lines are composed of first and second plate lines 81a and 81b. Each of the first plate lines 81a is in contact with first contact plugs 79a arranged on the diagonal, and each of the second plate lines 81b is in the first plate lines 81a. A contact between the second contact plugs 79b.

Although not shown in the drawings, the intermediate interlayer insulating layer 75 is planarized before the first and second contact holes 77a and 77b are formed to form the first and second upper electrodes 73a and 73b. You can also expose it. In this case, processes for forming the first and second contact holes 77a and 77b and the first and second contact plugs 79a and 79b are omitted.

As described above, according to an embodiment of the present invention, the first and second information storage elements 74a and 74b adjacent to each other along the row direction or the column direction are not connected by one plate line, and thus heat transfer therebetween. No path is formed. Also, the spacing between a pair of neighboring information storage elements connected to each other via the first or second plate line is increased compared to the prior art. Therefore, it is possible to prevent the unselected cells from being programmed during the program operation.

10A and 10B are cross-sectional views illustrating a method of manufacturing phase change memory cells according to another exemplary embodiment of the present invention. FIG. 10A corresponds to a cross sectional view taken in accordance with II of FIG. 4, and FIG. 10B corresponds to a cross sectional view taken in accordance with II-II in FIG. 4. In this embodiment, all processes except for the processes for forming the first and second contact plugs and the first and second plate lines are the same as in the first embodiment of the present invention described above. Therefore, hereinafter, processes for forming the first and second contact plugs and the first and second plate lines will be described in detail.

4, 10A, and 10B, the device isolation layer 53, the word lines 55, the common drain regions 57d, and the source are formed on the semiconductor substrate 51 using the same methods as in the first embodiment. The regions 57s, the bit lines 63, the lower interlayer insulating layer 68, and the storage node contact plugs 69 are formed. Thus, the storage node contact plugs 69 include the first and second groups of storage node contact plugs as in the first embodiment. A plurality of information storage elements are formed on the semiconductor substrate having the storage node contact plugs 69 using the same method as in the first embodiment. Accordingly, the information storage elements include first and second information storage elements 74a and 74b.

An intermediate interlayer insulating film 75 is formed on the entire surface of the semiconductor substrate having the first and second information storage elements 74a and 74b. The intermediate interlayer insulating layer 75 is patterned to form a plurality of first contact holes 77a 'exposing the first upper electrodes 73a of the first information storage elements 74a. The first contact plugs 79a 'may be formed in the first contact holes 77a' using a conventional method. As a result, the first contact plugs 79a 'are electrically connected to first information storage elements formed at points where even rows and even columns intersect and points where odd rows and odd columns intersect.

Alternatively, although not shown in the drawing, the intermediate interlayer insulating film 75 is planarized before the first contact holes 77a 'are formed to expose the first and second upper electrodes 73a and 73b. It may be. In this case, processes for forming the first contact holes 77a 'and the first contact plugs 79a' are omitted.

Forming a first conductive film on the entire surface of the semiconductor substrate having the first contact plugs (79a '); The first conductive layer is patterned to form a plurality of first plate lines 81 a ′ parallel to the diagonal line. Accordingly, each of the first plate lines 81a 'contacts the first contact plugs 79a' arranged along a diagonal line. An upper interlayer insulating layer 83 is formed on the entire surface of the semiconductor substrate having the first plate lines 81a '. The plurality of second contact holes 85 exposing the second upper electrodes 73b of the second information storage elements 74b by successively patterning the upper interlayer insulating layer 83 and the intermediate interlayer insulating layer 75. ). The second contact plugs 87 may be formed in the second contact holes 85 using a conventional method.

A second conductive film is formed on the entire surface of the semiconductor substrate having the second contact plugs 87. The second conductive layer is patterned to form a plurality of second plate lines 89 parallel to the first plate lines 81a '. Each of the second plate lines 81a ′ is formed to contact the second contact plugs 87 arranged along a diagonal line.

As described above, according to embodiments of the present invention, a pair of information storage elements neighboring each other along a diagonal line is connected through one plate line. In addition, a pair of information storage elements adjacent to each other along rows and columns are not connected through one plate line. Therefore, it is possible to remarkably suppress the phenomenon that the unselected cells adjacent to the selected cells are programmed while selectively programming one cell.

Claims (10)

Arranged two-dimensionally on the semiconductor substrate, at positions where even rows and even columns intersect and points where odd rows and odd columns intersect. A plurality of first data storage elements; Two-dimensionally arranged on the semiconductor substrate, the intersections of odd rows and even columns and the intersections of even rows and odd columns A plurality of second information storage elements located; A plurality of first plate lines disposed to pass over the first information storage elements and electrically connected to the first information storage elements, the plurality of first plate lines arranged parallel to the diagonal line; And And a plurality of second plate lines disposed between the first plate lines and electrically connected to the second information storage elements. The method of claim 1, And the first plate lines and the second plate lines are located at the same level. The method of claim 2, First contact plugs interposed between the first plate lines and the first information storage elements; And And second contact plugs interposed between the second plate lines and the second information storage elements. The method of claim 1, And the second plate lines are located at a level higher than the first plate lines. The method of claim 4, wherein First contact plugs interposed between the first plate lines and the first information storage elements; And And further comprising second contact plugs interposed between the second plate lines and the second information storage elements, wherein the height of the second contact plugs is greater than the height of the first contact plugs. Cells. Forming a plurality of information storage elements two-dimensionally arranged on the semiconductor substrate, wherein the information storage elements comprise first information formed at points where even rows and even columns intersect and points where odd rows and odd columns intersect. Storage elements together with second information storage elements formed at points where even rows and odd columns intersect and points where odd rows and even columns intersect, Forming a plurality of plate lines parallel to the diagonal while passing over the information storage elements, wherein the plate lines are electrically connected to the first and second information storage elements. Method of Making Cells. The method of claim 6, Forming the plate lines An intermediate interlayer insulating film is formed on the entire surface of the semiconductor substrate having the information storage elements; Patterning the intermediate interlayer insulating film to form first contact holes exposing the first information storage elements and second contact holes exposing the second information storage elements, A conductive film is formed on the entire surface of the semiconductor substrate having the first and second contact holes, Patterning the conductive layer to form a plurality of first parallel plate lines covering the first contact holes arranged on a diagonal line and a plurality of second parallel plate lines covering second contact holes between the first plate lines. A method of manufacturing a phase change memory cell, characterized in that forming. The method of claim 7, wherein Before forming the conductive film, And forming first contact plugs and second contact plugs in the first and second contact holes, respectively. The method of claim 6, Forming the plate lines An intermediate interlayer insulating film is formed on the entire surface of the semiconductor substrate having the information storage elements; Patterning the intermediate interlayer insulating film to form first contact holes exposing the first information storage elements, Forming a first conductive film on an entire surface of the semiconductor substrate having the first contact holes, Patterning the first conductive layer to form a plurality of first parallel plate lines covering the first contact holes arranged on a diagonal line, Forming an upper interlayer insulating film on the entire surface of the semiconductor substrate having the first plate lines, Successively patterning the upper interlayer insulating film and the intermediate interlayer insulating film to form second contact holes exposing the second information storage elements; Forming a second conductive film on an entire surface of the semiconductor substrate having the second contact holes, And patterning the second conductive film to form a plurality of second parallel plate lines covering the second contact holes arranged on a diagonal line. The method of claim 9, Before forming the first conductive layer, first contact plugs are formed in the first contact holes, And forming second contact plugs in the second contact holes before forming the second conductive layer.