KR20050076115A - Phase change memory devices and methods of forming the same - Google Patents

Abstract

A phase conversion memory device and a method of forming the same are provided. The device includes a lower interlayer insulating film formed on a substrate, a plurality of phase change material film patterns formed on the lower interlayer insulating film, an upper interlayer insulating film covering the phase change material film patterns, and a lower conductive layer disposed under each phase change material film pattern. The upper conductive patterns may be disposed on the patterns and the phase change material layer patterns.

Description

Phase change memory devices and methods of forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a phase change memory device and a method of forming the same.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power supply is cut off. Such nonvolatile memory devices mainly employ flash memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode sequentially stacked on a channel. Therefore, in order to improve the reliability and program efficiency of the flash memory cells, the film quality of the tunnel oxide film should be improved and the coupling ratio of the cells should be increased.

Instead of the flash memory devices, new nonvolatile memory devices such as phase change memory devices have recently been proposed.

1 shows an equivalent circuit diagram of a unit cell of the phase change memory devices.

Referring to FIG. 1, the phase change memory cell includes one access transistor TA and one variable resistor C. Referring to FIG. The variable resistor C includes a lower electrode, an upper electrode, and a phase changeable material layer interposed therebetween. The upper electrode of the variable resistor C is connected to the plate electrode PL. In addition, the access transistor TA includes a source region connected to the lower electrode, a drain region spaced apart from the source region, and a gate electrode positioned on a channel region between the source region and the drain region. . The gate electrode and the drain region of the access transistor TA are connected to a word line WL and a bit line BL, respectively. As a result, the equivalent circuit diagram of the phase change memory cell is similar to the equivalent circuit diagram of the DRAM cell. However, the nature of the phase change material film is completely different from that of the dielectric film employed in the DRAM cell. That is, the phase change material film has two stable states according to temperature.

2 is a graph for explaining a method of programming and erasing the phase change memory cells. Here, the horizontal axis represents time T, and the vertical axis represents temperature TMP applied to the phase change material film.

Referring to FIG. 2, when the phase change material film is heated after cooling for a first duration T1 at a temperature higher than a melting temperature Tm, the phase change material film is in an amorphous state. (See curve ①). In contrast, the phase change material film is heated for a second duration T2 longer than the first period T1 at a temperature lower than the melting temperature Tm and higher than a crystallization temperature Tc. Upon cooling, the phase change material film changes to a crystalline state (see curve ②). Here, the specific resistance of the phase change material film having an amorphous state is higher than that of the phase change material film having a crystalline state. Accordingly, by detecting the current flowing through the phase change material film in the read mode, it is possible to discriminate whether the information stored in the phase change memory cell is a logic "1" or a logic "0". As the phase change material film, a compound material layer (hereinafter, referred to as a 'GTS film') containing germanium (Ge), tellurium (Te), and stevilium (Sb) is widely used.

3 is a cross-sectional view showing conventional phase change memory cells.

Referring to FIG. 3, an isolation layer 13 defining an active region is disposed in a predetermined region of the semiconductor substrate 11. A pair of parallel word lines 15 are disposed across the active region. Impurity regions are formed in the active region positioned at both sides of the pair of word lines 15. An impurity region formed in an active region between the pair of word lines 15 corresponds to a common drain region 17d, and impurity regions adjacent to both sides of the common drain region 17d correspond to source regions 17s. do. The entire surface of the semiconductor substrate having the source / drain regions 17s and 17d, the word lines 15, and the device isolation layer 13 is covered with a first interlayer insulating layer 19. In the first interlayer insulating layer 19, contact plugs 21 electrically connected to the source / drain regions 17s and 17d are disposed. Conductive pads 23p and bit lines 23b are formed on the contact plugs 21, respectively. The conductive pad 23p and the bit line 23b are electrically connected to the source region 17s and the drain region 17d, respectively. Although only a portion of the bit line 23b is shown in the figure, the bit line 23b crosses the upper portion of the word lines 15.

The entire surface of the semiconductor substrate including the conductive pads 23p is covered with a second interlayer insulating film 25. First plugs 27 electrically connected to the respective conductive pads 23p are disposed in the second interlayer insulating layer 25. Phase changeable material layer patterns 29 are disposed on the second interlayer insulating layer 25. Each of the phase change material layer patterns 29 covers the first plugs 27. The front surface of the semiconductor substrate including each of the phase change material layer patterns 29 is covered with a third interlayer insulating layer 31. In the third interlayer insulating layer 31, second plugs 33 electrically connected to the phase change material layer patterns 29 are disposed. The second plugs 33 are connected to the plate electrode 35.

Meanwhile, as described with reference to FIG. 2, the information stored in the phase change memory device changes under a condition that a current of a predetermined size or more passes through the phase change material film pattern. Accordingly, the access transistor TA that selects a predetermined cell must have a current transfer capability capable of flowing a current equal to or greater than the predetermined size during the first or second period T1 or T2. However, the current transfer capability of the access transistor is decreasing due to the miniaturization of the word line 15 or the source / drain regions 17s and 17d due to the high integration of the semiconductor device. This necessity of securing the current transfer capability is a factor that hinders the miniaturization of the phase conversion memory device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a phase change memory device capable of reducing the need for current transfer capability of an access transistor.

Another object of the present invention is to provide a method of manufacturing a phase change memory device capable of reducing the need for the current transfer capability of an access transistor.

In order to achieve the above technical problem, the present invention provides a phase change memory device characterized in that it comprises auxiliary heating means. The device includes a lower interlayer insulating film formed on a substrate, a plurality of phase change material film patterns formed on the lower interlayer insulating film, an upper interlayer insulating film covering the phase change material film patterns, and disposed under each of the phase change material film patterns. Lower conductive patterns and upper conductive patterns disposed on the phase change material layer patterns.

Preferably, the lower conductive patterns intersect the upper conductive patterns at an angle of 45 to 135 degrees. In addition, the lower conductive patterns and the upper conductive patterns may be spaced apart from the phase change material layer patterns to pass through the lower interlayer insulating layer and the upper interlayer insulating layer, respectively. In addition, the lower plug is electrically connected to the lower surfaces of the phase change material layer patterns and the lower plug is electrically connected to the upper surfaces of the phase change material layer patterns. An upper plug may be further provided. In this case, the lower conductive pattern and the upper conductive pattern are preferably spaced apart from the lower plug and the upper plug, respectively.

Preferably, the lower conductive pattern includes heating parts surrounding the lower plugs and connection parts connecting the heating parts. In addition, the upper conductive pattern includes heating parts surrounding the upper plugs and connection parts connecting the heating parts. In each case, it is preferable that the heat generating portion have a narrower cross-sectional area than the connecting portion. In addition, the upper conductive pattern and the lower conductive pattern may be formed of at least one selected from tungsten, copper, aluminum, cobalt, and polycrystalline silicon.

In order to achieve the above another technical problem, the present invention provides a method of manufacturing a phase change memory device, characterized in that it comprises auxiliary heating means. In this method, lower conductive patterns including a heating part and a connection part are formed on a predetermined region of a semiconductor substrate, and phase change material layer patterns are formed on the heating part of the lower conductive patterns, and then the phase conversion material layer patterns are formed. And forming upper conductive patterns having a heating part and a connection part thereon.

The lower conductive pattern and the upper conductive pattern are formed to be electrically insulated from the phase change material layer pattern. Preferably, before forming the phase change material layer pattern, forming a lower interlayer insulating layer covering an entire surface of the semiconductor substrate including the lower conductive patterns, and then forming a lower plug penetrating the lower interlayer insulating layer. The lower plug may be formed to be electrically insulated from the lower conductive pattern. In addition, the lower plug is formed to pass through the heat generating portion of the lower conductive pattern and to be electrically connected to the phase change material film pattern.

Meanwhile, before forming the upper conductive pattern, a first upper insulating layer covering the entire surface of the semiconductor substrate including the phase change material layer patterns is formed, and after forming the upper conductive pattern, the entire upper surface of the resultant is formed. The method may further include forming a second upper insulating film. In addition, after forming the second upper insulating film, the method may further include forming upper plugs electrically connected to the upper surface of the phase change material film pattern through the first and second upper interlayer insulating films. In this case, the upper plug is formed to pass through the heat generating portion of the upper conductive pattern.

Preferably, the upper conductive pattern is formed to cross at an angle of 45 to 135 degrees with respect to the lower conductive pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

4 through 8 are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the device isolation layer 110 is formed in a predetermined region of the semiconductor substrate 100 to define a plurality of active regions. The active regions are defined to be two-dimensionally arranged on the semiconductor substrate 100. A plurality of word lines 120 are formed to cross the upper portions of the active regions. Each of the active regions is divided into three regions by a pair of word lines 120. Impurity regions are formed by implanting impurity ions into the active regions using the word lines 120 and the device isolation layer 110 as ion implantation masks. As a result, a common drain region 130d and two source regions 130s are formed in each of the active regions.

A first lower insulating layer 140, for example, a silicon oxide layer, is formed on the entire surface of the semiconductor substrate having the common drain regions 130d and the source regions 130s. Subsequently, a plurality of contact plugs 145 passing through predetermined regions of the first lower insulating layer 140 are formed. The contact plugs 145 are formed to contact the source region 130s. The contact plugs 145 may be formed of polysilicon or tungsten. Contact pads 155 are formed on the contact plugs 145. Although not illustrated, a bit line crossing the word lines 120 is disposed on the first lower insulating layer 140. The bit line is electrically connected to the common drain region 130d by a predetermined contact plug (not shown) passing through the first lower insulating layer 140. In this case, the contact pad 155 and the bit line are formed through the same process.

Referring to FIG. 5, a second lower insulating layer 160 is formed on the entire surface of the semiconductor substrate including the contact pad 155. The second lower insulating layer 160 may be formed of the same material layer as the first lower insulating layer 140. A plurality of lower conductive patterns 165 are formed on the second lower insulating layer 160.

The lower conductive patterns 165 may be made of a conductive material having a high melting temperature. For example, the lower conductive pattern 165 may be formed of one of tungsten, copper, and cobalt, but in some cases, a material such as aluminum or polysilicon may be used. In addition, the lower conductive patterns 165 may be formed of a heat generating portion and a connecting portion, and preferably, a cross section of the heat generating portion is narrower than a cross section of the connecting portion. Accordingly, heat generated by the current flowing through the lower conductive pattern 165 may be selectively generated only in the heat generating unit. In this regard, the heat generating unit is preferably disposed under the phase change material film pattern to be formed in a subsequent process.

Referring to FIG. 6, a third lower insulating layer 170 is formed on the entire surface of the semiconductor substrate including the lower conductive patterns 165. The third lower insulating layer 170 may be formed of the same material layer as the first and second lower insulating layers 140 and 160. The first, second, and third lower insulating layers 140, 160, and 170 constitute a lower interlayer insulating layer.

A lower plug 175 is formed through the third and second lower insulating layers 170 and 160 to be electrically connected to the contact pad 155. The lower plug 175 may be formed to penetrate the heat generating portion of the lower conductive pattern 165. In this case, the lower plug 175 must be electrically insulated from the lower conductive pattern 165. To this end, the heat generating portion of the lower conductive pattern 165 preferably has an empty closed curve in the center area, and the lower plug 175 is formed to pass through the center area of the heat generating part.

Referring to FIG. 7, phase change material layer patterns 300 are formed on the lower interlayer insulating layer to contact the upper surface of the lower plug 175. As a result, the phase change material layer patterns 300 are disposed on the vertical regions of the source region 130s and the contact pad 155. The phase change material layer pattern 300 may include a GTS layer and an upper electrode layer, which are sequentially stacked, wherein the upper electrode layer is a titanium nitride layer (TiN), a titanium aluminum nitride layer (TiAlN), a titanium silicon nitride layer (TiSiN), It is preferable to form a tantalum nitride film (TaN), a tantalum aluminum nitride film (TaAlN), or a tantalum silicon nitride film (TaSiN).

Subsequently, a first upper insulating layer 180 covering the phase change material layer patterns 300 is formed. Upper conductive patterns 185 may be formed on the first upper insulating layer 180 to pass over the phase change material layer patterns 300. The upper conductive patterns 185 may be formed to cross at an angle of 45 to 135 degrees with respect to the lower conductive patterns 165, and are preferably vertically formed. In addition, like the lower conductive pattern 165, the upper conductive patterns 185 may be made of a conductive material having a high melting temperature. For example, the upper conductive pattern 185 may be formed of one material selected from tungsten, copper, cobalt, aluminum, and polysilicon. In addition, the upper conductive patterns 185 may include a heat generating portion and a connecting portion, and preferably, a cross section of the heat generating portion is narrower than a cross section of the connecting portion.

As described above, the changing of the information stored in the predetermined memory cell is performed by heating the phase change material film pattern 300. In this case, heat generated by the current flowing through the lower and upper conductive patterns 165 and 185 may be used to reduce the amount of current passing through the phase change material layer pattern 300. As a result, the required current transfer capability is reduced, making it possible to form the access transistors more finely. As a result, a more highly integrated phase change memory element can be manufactured.

Meanwhile, the upper conductive pattern 185 and the lower conductive pattern 165 are formed to have different directions as described above to minimize interference with other memory cells. In this case, the method of selecting a predetermined cell includes flowing a predetermined current through the upper and lower conductive patterns 185 and 155 passing through the cell, and respectively the upper and lower conductive patterns 185 and 165. The heat generated at may be large enough not to heat the phase change material film pattern 300 to the crystallization temperature Tc.

According to another embodiment of the present invention, the lower conductive pattern 165 and the upper conductive pattern 185 may be formed using a damascene technique. In addition, the lower conductive pattern 165 and the upper conductive pattern 185 may be formed of a material having a high resistivity.

Referring to FIG. 8, a second upper insulating layer 190 is formed on the entire surface of the semiconductor substrate including the upper conductive patterns 185. The second upper insulating layer 190 may be formed of the same material as the first upper insulating layer 180. In this case, the first and second upper insulating layers 180 and 190 constitute an upper interlayer insulating layer.

An upper plug 195 is formed through the upper interlayer insulating layer and connected to an upper surface of the phase change material layer pattern 300. The upper plug 195 is electrically insulated from the upper conductive pattern 185. To this end, the upper plug 195 is disposed to pass through an empty area in the middle of the heat generating portion of the upper conductive pattern 185. Subsequently, an upper electrode 200 for electrically connecting the upper plugs 195 is disposed.

9 is a perspective view showing the main part of the phase change memory device according to the preferred embodiment of the present invention.

Referring to FIG. 9 and FIG. 8, which shows a cross section corresponding thereto, device isolation layers 110 defining an active region are disposed on the semiconductor substrate 100. A pair of word lines 120 intersect the upper portion of each active region. Accordingly, the active region under the word line 120 becomes a channel region of the transistor, and an impurity region is formed in the active region other than the channel region. The impurity region formed in the active region between the word lines 120 becomes the common drain region 130d, and the two impurity regions disposed next to each other become the source region 130s. As a result, two transistors sharing the common drain region 130d are disposed in one active region.

The front surface of the semiconductor substrate on which the transistors are formed is covered by the first lower insulating layer 140 having the contact plug 145. The contact pads 155 contacting the upper surface of the contact plug 145 are disposed on the first lower insulating layer 140. The front surface of the semiconductor substrate including the contact pad 155 is covered by the second lower insulating layer 160 made of the same material as the first lower insulating layer 140.

A lower conductive pattern 165 is disposed on the second lower insulating layer 160, and a third lower insulating layer 170 is disposed on the semiconductor substrate including the lower conductive pattern 165. The phase change material layer patterns 300 electrically connected to the contact pads 155 through the lower plug 175 are disposed on the third lower insulating layer 170. To this end, the lower plug 175 is disposed to pass through the second and third lower insulating layers 160 and 170.

The entire surface of the semiconductor substrate including the phase change material layer patterns 300 is covered by the first upper insulating layer 180. Upper conductive patterns 185 are disposed on the first upper insulating layer 180 to intersect the lower conductive pattern 165 at an angle of 45 to 135 degrees. The entire surface of the semiconductor substrate including the upper conductive patterns 185 is covered by the second upper insulating layer 190. The first and second upper insulating layers 180 and 190 constitute an upper interlayer insulating layer. On the upper interlayer insulating layer, an upper electrode 200 electrically connected to the phase change material film pattern 300 is disposed by an upper plug 195. To this end, the upper plug 195 penetrates the first and second upper insulating layers 180 and 190.

The lower conductive pattern 165 and the upper conductive pattern 185 may include a heating part and a connection part. The heating part is disposed above or below the vertical of the phase change material layer pattern 300, and the connection part is disposed to connect the heating parts. In particular, the heat generating portion is a position where electrical heat energy is generated, and for this purpose, the cross-sectional area of the heat generating portion is preferably narrower than the cross-sectional area of the connection portion. In addition, the lower conductive pattern 165 and the upper conductive pattern 185 are disposed to be electrically insulated from the upper plug 195, the lower plug 175, and the phase change material layer pattern 300.

According to the present invention, an upper conductive pattern and a lower conductive pattern for selecting and heating a predetermined phase change material film pattern are provided. Accordingly, the magnitude of the current supplied through the access transistor can be reduced. As a result, the current transfer capability can be reduced, and the semiconductor device can be further integrated.

1 is an equivalent circuit diagram of a unit cell of a typical typical phase changeable memory device.

2 is a graph for explaining the characteristics of the phase change material employed in the phase change memory cell.

3 is a cross-sectional view showing conventional phase change memory cells.

4 through 8 are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

9 is a perspective view showing the main part of the phase change memory device according to the preferred embodiment of the present invention.

Claims (14)

A lower interlayer insulating film formed on the substrate; A plurality of phase change material film patterns formed on the lower interlayer insulating film; An upper interlayer insulating layer covering the phase change material layer patterns; Lower conductive patterns disposed under each of the phase change material layer patterns; And And an upper conductive pattern disposed on each of the phase change material layer patterns. The method of claim 1, And the lower conductive patterns intersect the upper conductive patterns at an angle of 45 to 135 degrees. The method of claim 1, And the lower conductive patterns and the upper conductive patterns are spaced apart from the phase change material layer patterns to penetrate the lower interlayer insulating layer and the upper interlayer insulating layer, respectively. The method of claim 1, A lower plug penetrating the lower interlayer insulating film and electrically connected to lower surfaces of the phase change material film patterns; And A top plug penetrating the upper interlayer insulating film and electrically connected to upper surfaces of the phase change material film patterns, And the lower conductive pattern and the upper conductive pattern are spaced apart from the lower plug and the upper plug, respectively. The method of claim 4, wherein The lower conductive pattern is Heating parts surrounding the lower plugs; And Including connection parts connecting the heating parts, And the heat generating portion has a smaller cross-sectional area than the connecting portion. The method of claim 4, wherein The upper conductive pattern is Heating parts surrounding the upper plugs; And Including connection parts connecting the heating parts, And the heat generating portion has a smaller cross-sectional area than the connecting portion. The method of claim 4, wherein And the upper conductive pattern and the lower conductive pattern are formed of at least one selected from tungsten, copper, aluminum, cobalt, and polycrystalline silicon. Forming lower conductive patterns on the predetermined region of the semiconductor substrate, the lower conductive patterns including a heating part and a connection part; Forming phase change material layer patterns on the heating parts of the lower conductive patterns; And And forming upper conductive patterns on the phase change material layer patterns, the upper conductive patterns including a heating part and a connection part. The method of claim 8, And the lower conductive pattern and the upper conductive pattern are electrically insulated from the phase change material film pattern. The method of claim 8, Before forming the phase change material film pattern, Forming a lower interlayer insulating film covering an entire surface of the semiconductor substrate including the lower conductive patterns; And Forming a lower plug penetrating the lower interlayer insulating film, And the lower plug is electrically insulated from the lower conductive pattern. The method of claim 10, And the lower plug penetrates through the heat generating portion of the lower conductive pattern and is electrically connected to the phase change material film pattern. The method of claim 8, Before forming the upper conductive pattern, a first upper interlayer insulating layer covering the entire surface of the semiconductor substrate including the phase change material layer patterns is formed; And forming a second upper interlayer insulating film covering the entire surface of the resultant after forming the upper conductive pattern. The method of claim 12, After forming the second upper interlayer insulating film, Forming upper plugs electrically connected to upper surfaces of the phase change material film patterns through the first and second upper interlayer insulating films, And the upper plug is formed to pass through a heat generating portion of the upper conductive pattern. The method of claim 8, And the upper conductive pattern is formed to cross at an angle of 45 to 135 degrees with respect to the lower conductive pattern.