KR20060118178A - Phase change ram device and method of manufacturing the same - Google Patents

Abstract

A phase change storage device and a method for manufacturing the same are provided to prevent the size of a cell from being increased by forming power lines at edges of both sides of a cell array while forming only bit lines inside the cell array. Active regions are formed in a semiconductor substrate by a device isolation film. A plurality of word lines are formed on the active regions and the device isolation film. Sources and drains are formed in the active regions of the substrate at both sides of the word lines. A plurality of hole type first plugs(7) are formed to contact with the respective drains. A bar type second plug(8) is formed to contact with a plurality of sources, which are arranged along a formation direction of the word lines. A bar type third plug(9) is formed perpendicular to the bar type second plug(8). A plurality of GST cells include a lower electrode, a GST film, and an upper electrode. A plurality of bit lines are formed to contact with the hole type first plugs. Power lines formed on the respective bar type third plugs.

Description

Phase change RAM device and method of manufacturing the same

1A to 1E are plan views for each step for explaining a method of manufacturing a phase change memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 active region

3: active line 4: device isolation film

5: word line 6: first oxide film

7: first tungsten plug 8: second tungsten plug

9: third tungsten plug 10: third oxide film

11: bit line 12: power line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device and a method for manufacturing the same so that an increase in cell size is prevented.

Generally, a memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a ROM that keeps the input data stored even when the power is cut off. ) Are largely divided into elements. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM is a very good memory device as is well known, high charge storage capability is required for periodic refresh operation, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased.

In addition, the flash memory device requires a higher operating voltage than a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies have been conducted to develop new memory devices having characteristics of non-volatile memory devices and simple structures. For example, a phase change RAM device is proposed. It became.

The phase change memory device uses a difference in resistance between crystalline and amorphous phases because a phase change film interposed between the electrodes through a current flow between the lower electrode and the upper electrode occurs from a crystal state to an amorphous state. It is a storage element for determining the information stored in the.

In other words, the phase-conversion memory device uses a chalcogenide film as a phase-conversion film, which is a compound film composed of germanium (Ge), stevidium (Sb), and tellurium (Te). GST film), a phase change occurs between an amorphous state and a crystalline state by an applied current, that is, Joule heat, wherein the resistivity of the phase change film having an amorphous state is in a crystalline state. Since it is higher than the specific resistance of the phase change film having a value, the current flowing through the phase change film in the read mode is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

On the other hand, in the above-described phase conversion memory device, a plurality of metal wirings are formed for use of a bit line for selecting a GST cell and a power line for applying a ground voltage. The power lines are bundled in pairs to allow for multiple pairs.

However, according to the conventional phase conversion memory device in which several bit lines and power lines are alternately arranged in the cell array, the pitch between the bit lines and the power lines, that is, the pitch between adjacent metal lines is inevitable. As the cell size increases, the device size increases.

Accordingly, an object of the present invention is to provide a phase change memory device and a method of manufacturing the same, which are devised to solve the above-mentioned conventional problems and to prevent the cell size from increasing.

In order to achieve the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate in which active regions are defined by an isolation layer; Several word lines formed on the substrate active region and the isolation layer; Sources and drains formed in the substrate active regions on both sides of the word line; A plurality of hole type first plugs formed to contact the drains; A bar type second plug formed to contact a plurality of sources arranged along the word line forming direction; A bar type third plug formed together with the bar type second plug and perpendicular to the second plug formed to interconnect both ends of the bar type first plugs; A plurality of GST cells formed on a portion of the bar-type second plug and composed of a lower electrode, a GST film and an upper electrode stacked thereon; A plurality of bit lines formed to contact the hole type first plugs arranged along a direction perpendicular to the bar type second plug; And a power line formed on each bar type third plug at both ends of the bit lines.

Here, the semiconductor substrate is characterized in that an active line is formed at both ends of the active regions to protect the main cell and to apply a ground voltage.

The first plug to the third plug is characterized in that made of tungsten.

In addition, the present invention includes forming a plurality of word lines on a semiconductor substrate in which active lines are defined in each of the active regions and opposite ends of the active regions; Forming a source and a drain in the substrate active region on both sides of the wordline; Forming a first oxide film on an entire surface of the substrate on which the word line, the source, and the drain are formed; Forming a plurality of first plugs in a hole type in portions of the first oxide layer on each drain; A plurality of second plugs are formed in a bar type to contact several sources arranged along a gate forming direction in the first oxide film, and both ends of the second plugs are respectively connected in the first oxide film on a substrate active line. Forming a bar type third plug; Forming a second oxide film on the substrate resultant; Forming several GST cells in contact with the bar type second plug on the second oxide layer, the GST layer and the upper electrode stacked on the lower electrode; Forming a third oxide film on the second oxide film including the GST cell; And forming a plurality of bit lines on the third oxide layer to contact the hole type first plugs arranged along a direction perpendicular to the second plug, and forming the bar type third plug at both ends of the bit lines. It provides a method of manufacturing a phase change memory device comprising a; forming a power line to contact.

Here, the first plug to the third plug is characterized in that formed of tungsten.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. Instead of forming a tungsten plug in a hole shape in each of the GST cell portion and the ground voltage applying portion, the present invention provides an active line for applying the ground voltage to the edge of the cell array. By limiting, the bit lines are formed so that several are arranged in the cell array and the power lines are arranged only at the edge of the cell array.

In this way, the power line is formed only at the edge of the cell array while only the bit lines are formed in the cell array, and the increase in cell size can be effectively suppressed while increasing the pitch between the bit lines and the power lines.

In addition, the present invention solves the difficulty of forming a bar type and a hole type at the time of etching to form a tungsten plug by opening the source to the hole type and opening the drain to the bar type in terms of process. Yes, of course, can minimize the etching damage.

In detail, FIGS. 1A to 1E are plan views according to processes for explaining a method of manufacturing a phase change memory device according to the present invention.

Referring to FIG. 1A, an isolation layer 4 is formed in a semiconductor substrate 1 to define active regions 2 according to a known shallow trench isolation (STI) process. At this time, when defining the active regions 2, the active lines 3 are defined at both ends thereof, that is, at both edges of the cell array to apply the ground voltage Vss. Here, the active line 3 serves to protect the main cell of the cell array as well as to apply a ground voltage.

Referring to FIG. 1B, several word lines 5 extending in one direction are formed on a semiconductor substrate 1 in which active regions 2 and active lines 3 are defined according to a known process.

Referring to FIG. 1C, a high concentration ion implantation process is performed on a substrate product on which a word line is formed to form a source and a drain (not shown) in active regions on both sides of the word line. At this time, impurities are also implanted into the exposed active line portion to which the ground voltage is applied.

Next, after the first oxide layer 6 is formed on the entire surface of the word line, the source and the drain, the first oxide layer is etched to form several first contact holes exposing each drain. Then, a conductive film, such as a tungsten film, is embedded in the first contact hole to form several hole-type first tungsten plugs 7 that are individually contacted with each drain.

Referring to FIG. 1D, the first oxide layer 6 is etched again to form a bar-type second contact hole exposing several sources arranged along the gate formation direction. In this case, when the second contact hole is formed, a bar type third contact hole is also formed on the active line at both edges of the cell array.

Subsequently, a second tungsten plug 8 of a bar type is formed in the second and third contact holes by filling a conductive film, such as a tungsten film, to interconnect several sources arranged along the gate forming direction. A bar type third tungsten plug 9 is formed on the active line. At this time, both ends of the second tungsten plugs 8 are formed such that the third tungsten plugs 9 are connected to each other.

Referring to FIG. 1E, a second oxide film (not shown) is formed on the entire surface of the substrate resultant up to this step. Then, after forming a lower electrode in contact with the bar-type second tungsten plug on the second oxide film, a GST film and an upper electrode are sequentially stacked thereon to form several GST cells. Then, a third oxide film 10 is formed on the second oxide film including the GST cell.

Next, the third oxide film 10 is etched to expose the third tungsten plug, and line-shaped holes are formed to expose the first tungsten plugs arranged in a direction orthogonal to the gate forming direction. Then, a metal film is deposited on the third oxide layer to fill the holes, and then patterned to form several bit lines 11 inside the cell array, and through a third tungsten plug disposed on both sides of the cell array. The power line 12 is contacted with the substrate active line to form a ground voltage.

Thereafter, a series of known subsequent processes are carried out to complete the manufacture of the phase change memory device according to the present invention.

As described above, the present invention can reduce the pitch between the lines by forming a power line at both edges of the cell array while forming only the bit lines inside the cell array, thereby increasing the cell size compared to the conventional art. It can be effectively suppressed.

In addition, the present invention can solve the difficulty in the etching process by proceeding the source and drain open at the same time, by proceeding the opening of the source to the hole type and the opening of the drain to the bar type through a separate process, so, The device reliability can be improved by minimizing etching damage.

As mentioned above, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (5)

A semiconductor substrate in which active regions are defined by an isolation layer; Several word lines formed on the substrate active region and the isolation layer; Sources and drains formed in the substrate active regions on both sides of the word line; A plurality of hole type first plugs formed to contact the drains; A bar type second plug formed to contact a plurality of sources arranged along the word line forming direction; A bar type third plug formed together with the bar type second plug and perpendicular to the second plug formed to interconnect both ends of the bar type first plugs; A plurality of GST cells formed on a portion of the bar-type second plug and composed of a lower electrode, a GST film and an upper electrode stacked thereon; A plurality of bit lines formed to contact the hole type first plugs arranged along a direction perpendicular to the bar type second plug; And And a power line formed on each bar type third plug at both ends of the bit lines. The phase change memory device of claim 1, wherein an active line is formed at each of both ends of the active regions to protect the main cell and to apply a ground voltage. The phase change memory device as claimed in claim 1, wherein the first to third plugs are made of tungsten. Forming several word lines on a semiconductor substrate in which active lines are defined in each of the active regions and opposite ends of the active regions; Forming a source and a drain in the substrate active region on both sides of the wordline; Forming a first oxide film on an entire surface of the substrate on which the word line, the source, and the drain are formed; Forming a plurality of first plugs in a hole type in portions of the first oxide layer on each drain; A plurality of second plugs are formed in a bar type to contact several sources arranged along a gate forming direction in the first oxide film, and both ends of the second plugs are respectively connected in the first oxide film on a substrate active line. Forming a bar type third plug; Forming a second oxide film on the substrate resultant; Forming several GST cells in contact with the bar type second plug on the second oxide layer, the GST layer and the upper electrode stacked on the lower electrode; Forming a third oxide film on the second oxide film including the GST cell; And A plurality of bit lines are formed on the third oxide layer to contact the hole type first plugs arranged in a direction perpendicular to the second plug, and the bar type third plug and the contacts are formed at both ends of the bit lines. And forming a power line. The method of claim 4, wherein the first to third plugs are made of tungsten.

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