KR101041742B1 - Resistance change memory device, method of operating and manufacturing the same - Google Patents

Abstract

PURPOSE: A resistance change memory device, a method for manufacturing the same, and a method for driving the same are provided to improve the operational reliability of the device by uniformly forming patterns in the device. CONSTITUTION: A plurality of first wirings(100) is arranged to one direction. A plurality of conductive patterns(200) is in connection with the first wirings. A variable resistance layer(300) is formed on the conductive patterns. A plurality of second wirings(400) is arranged to a direction crossing the first wirings and crosses a part of the conductive patterns on the variable resistance layer. A plurality of third wirings(500) is arranged to a direction crossing the first wirings and crosses remained part of the conductive patterns on the variable resistance layer.

Description

Resistance change memory device, method and method of driving the same {Resistance change memory device, method of operating and manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistive change memory device, and more particularly, to a resistive change memory device having a fine pattern formed by using double patterning and sidewall spacers, a manufacturing method, and a driving method thereof.

Recently, next-generation nonvolatile memory devices having low power consumption and high integration compared to flash memory devices have been studied. Such next-generation nonvolatile memory devices include phase change RAM (PRAM) using a state change of a phase change material such as a chalcogenide alloy, and a magnetic tunnel junction (MTJ) thin film according to the magnetization state of a ferromagnetic material. Magnetic change memory (MRAM) using a change in resistance of a ferroelectric material, ferroelectric memory using polarization of a ferroelectric material, resistance change memory (ReRAM) using a change in resistance of a variable resistance material, and the like. .

Among them, the resistance change memory device includes a resistance change memory cell in which a variable resistance material is formed between an upper electrode and a lower electrode, and the resistance of the variable resistance material changes according to a voltage applied to the upper electrode and the lower electrode. Such resistive memory devices are fabricated to form filaments in the variable resistive material by applying a fairly high level of filament forming voltage to the resistive change memory cells. The filament becomes a current path of cell current flowing between the upper electrode and the lower electrode. After the filament is formed, the variable resistance material may be reset by applying a reset voltage, or the variable resistance material may be set by applying a set voltage.

Such a resistance change memory device has a filament-type switching mechanism, which has advantages such as fast switching characteristics and stable retention characteristics.However, it is possible to secure stable switching characteristics due to randomly formed filaments. it's difficult. However, forming the metal tip in the variable resistance material may improve the uniformity of the switching characteristics. To this end, research was conducted on resistance change memories with sharp metal tips similar to lightning rods.

However, due to the limitation of the lithography process in the current semiconductor device manufacturing process, it is difficult to implement a device having a feature size (1F) or less. 1F is the minimum size to which the photographic process can be applied. For example, in the case of a device having a width and a distance of 30 nm, 30 nm becomes 1F. When calculating the unit area of the device, the width and the distance of the wire are considered in the unit of pitch. On the other hand, if the unit area of the memory element is very small, for example 30 nm x 30 nm, the size of the metal tip to be formed here should be less than 10 nm. In addition, in order to ensure uniform switching characteristics of Gbit and terabit (Tbit) devices, all metal tips must be uniform on an atomic scale. However, in the case of using the conventional semiconductor technology, it is almost impossible to manufacture a uniform 10 nm class device, and it is almost impossible to uniformly form a metal tip.

The present invention provides a variable resistance memory device capable of forming a pattern of 1F or less, a driving method and a manufacturing method thereof.

The present invention provides a variable resistance memory device capable of forming a pattern of 1F or less using a double patternig and a sidewall spacer, a driving method thereof, and a manufacturing method thereof.

The present invention provides a variable resistance memory device capable of storing multi-bit data in a predetermined area by forming a plurality of unit devices in a predetermined area, a driving method thereof, and a manufacturing method thereof.

The present invention provides a variable resistance memory device having a three-dimensional structure that can improve the degree of integration by stacking a plurality of device layers in which a plurality of unit devices are formed in a predetermined area, and a driving method and a manufacturing method thereof.

On the other hand, the technical problems of the present invention are not limited to the technical problems mentioned above, other technical problems that are not mentioned can be clearly understood by those skilled in the art from the following description.

A variable resistance memory device according to an aspect of the present invention includes a plurality of first wirings arranged in one direction; A plurality of conductive patterns connected to the first wirings; A variable resistance layer formed on the conductive pattern; A plurality of second wirings arranged in a direction crossing the first wiring so as to pass a portion of the conductive pattern on the variable resistance layer; And a plurality of third wires arranged in a direction crossing the first wire so as to pass through the remaining portion of the conductive pattern on the variable resistance layer.

The conductive pattern protrudes upward from the side surface of the first wiring, is formed higher than the height of the first wiring, and a plurality of conductive patterns are formed in an area of 4F ² .

The conductive pattern is formed to protrude from an upper portion of the first wiring.

The variable resistance layer is formed of at least one of a metal oxide, PCMO (Pr _{1 - X} Ca _X MnO ₃ , 0 <X <1), chalcogenide, perovskite, and a metal doped solid electrolyte. Is formed.

A tunneling barrier is further formed between the conductive pattern and the variable resistance layer.

The second wiring extends at an acute angle with the first wiring in a planar direction, and the third wiring extends at an acute angle with the first wiring in a plane direction and orthogonal to the second wiring.

The semiconductor device may further include an insulating layer provided between the second wiring and the third wiring.

The third wiring is formed in contact with the variable resistance layer on the conductive pattern through a hole or a trench formed in the insulating layer.

The second wiring is formed to pass through the conductive patterns formed on one side of the plurality of first wirings, and the third wiring is formed to pass through the conductive patterns formed on the other side of the plurality of first wirings. do.

The plurality of first wirings, conductive patterns, variable resistance layers, second wirings, and third wirings form one device layer, and the plurality of device layers are stacked to form a three-dimensional structure, between each of the plurality of device layers. It further comprises an interlayer insulating film formed on.

According to another aspect of the present invention, a variable resistance memory device includes a plurality of lower wires arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections crossing the plurality of lower interconnections and arranged in a direction orthogonal to the plurality of first upper interconnections; And a plurality of variable resistance elements formed between the lower interconnection and the first and second upper interconnections.

The variable resistance element has the first wiring comprises a conductive pattern formed on the variable resistance layer formed on the conductive pattern, the conductive pattern is formed in a plurality in the area of 4F ² programs of a plurality of bits per unit area of 4F ² This is possible.

According to still another aspect of the present invention, there is provided a method of driving a variable resistance memory device, including: a plurality of lower wires arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections crossing the plurality of lower interconnections and arranged in a direction orthogonal to the plurality of first upper interconnections; And a plurality of variable resistance elements formed between the lower interconnection and the first and second upper interconnections, applying a first program voltage to at least one of the lower interconnections, and selecting one of the first and second upper interconnections. A second programming voltage is applied to at least one of the at least one selected variable resistance element, a read voltage is applied to the lower line connected to the selected variable resistance element, and the first or second variable voltage is connected to the selected variable resistance element. The ground voltage is applied to the second upper wiring to read the program state of the variable resistance element.

The first program voltage is a positive voltage, the second program voltage is a negative voltage, and a ground voltage is applied to the unselected lower interconnections and the unselected first and second upper interconnections.

Reading a program state of the variable resistance element by sensing a potential change of the first upper line or the second upper line connected with the selected variable resistance element, and reading the program state of the variable resistance element and the lower line, first and second 2 Apply a voltage lower than the read voltage to the upper wiring.

Method of manufacturing a variable resistance memory device according to another embodiment of the present invention comprises the steps of forming a plurality of lower wiring extending in one direction on the substrate; Forming a plurality of conductive patterns using sidewall spacers to be connected to the lower wirings; Forming a variable resistance layer on the plurality of conductive patterns; And forming a plurality of upper interconnections on the variable resistance layer by using double patterning to pass over the plurality of conductive patterns.

Forming a plurality of first upper interconnections on the variable resistance layer using the double patterning to pass the upper interconnections to a part of the plurality of conductive patterns; And forming a plurality of second upper wires insulated from the first upper wires and extending in a direction orthogonal to pass through the remaining portions of the plurality of conductive patterns.

The forming of the plurality of conductive patterns may include forming conductive layer sidewall spacers on both sides of the lower wiring by a first sidewall spacer process; Forming an insulating layer sidewall spacer by a second sidewall spacer process crossing the conductive layer sidewall spacer; And removing the insulating layer sidewall spacer after removing the conductive layer sidewall spacer exposed by the insulating layer sidewall spacer.

The forming of the plurality of conductive patterns may include: stacking a plurality of first mask films on the plurality of lower interconnections and forming the conductive layer sidewall spacers on the side surfaces thereof; Forming a plurality of second mask films in a direction orthogonal to the lower wirings, and forming the insulating layer sidewall spacers on sidewalls of the plurality of second mask films; Removing the conductive layer sidewall spacers exposed by the insulating layer sidewall spacers; And removing the insulating layer sidewall spacers and the first and second mask layers.

The method may further include forming an insulating layer on the substrate to partially expose the conductive pattern.

The forming of the first upper interconnection may include forming a conductive layer and a photosensitive film on the variable resistance layer; First exposing the photosensitive film to form an exposure area of a first width and an unexposed area of a second width; Secondarily exposing the non-exposed areas of the photosensitive film to a first width; Developing the primary and secondary exposure regions to form a photoresist pattern; Etching the conductive layer using the photoresist pattern as an etching mask.

After forming an insulating layer on the first upper interconnection, forming a contact hole in the insulating layer to open another portion of the conductive pattern, wherein the second upper interconnection is formed so that the contact hole is buried. It forms on an insulating layer.

The forming of the contact hole may include forming a first contact hole larger than the contact hole by etching the insulating layer to expose the variable resistance layer on another portion of the conductive pattern; And forming a sidewall on a side surface of the first contact hole.

The forming of the second upper wiring may include forming a conductive layer and a photoresist film on the insulating layer to fill the contact hole; First exposing the photosensitive film to form an exposure area of a first width and an unexposed area of a second width; Secondarily exposing the non-exposed areas of the photosensitive film to a first width; Developing the primary and secondary exposure regions to form a photoresist pattern; Etching the conductive layer using the photoresist pattern as an etching mask.

The plurality of lower interconnections are formed using double patterning.

Forming an interlayer insulating film on the upper wiring; And forming a device layer by sequentially forming the lower wiring, the conductive pattern, the variable resistance layer, and the upper wiring, and manufacturing a three-dimensional structure by stacking a plurality of the interlayer insulating film and the device layer.

An electronic product according to another embodiment of the present invention is an electronic product including a resistance change memory device and a processor connected thereto, the resistance change memory device comprising: a plurality of lower wirings arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections arranged in a direction orthogonal to the plurality of first upper interconnections; And a plurality of variable resistance elements formed between the lower interconnection and the first and second upper interconnections.

Embodiments of the present invention form a plurality of conductive patterns on the first wiring after forming the first wiring extending in one direction, and after forming a plurality of second wirings to pass through a portion of the plurality of conductive patterns, A plurality of third wirings are formed to pass through the remaining part of the conductive pattern, thereby forming one element layer. In addition, a plurality of such device layers are stacked to fabricate a variable resistance memory device having a three-dimensional structure. Here, the second wiring and the third wiring, more preferably, the first wiring can also be formed with a width and an interval of 1F or less by using double patterning, and the conductive pattern is preferably fine with 0.1F using sidewall spacers. It can be formed in a pattern.

According to the exemplary embodiments of the present invention, a fine pattern of 1F or less, preferably 0.1F, may be formed using double patterning and sidewall spacers, and multiple bits of data may be stored in an area of 4F ² using the double patterning and sidewall spacers.

Therefore, the pattern of 1F or less can be formed by overcoming the limitation of the photolithography process, thereby improving the integration degree of the area-to-area device.

In addition, since the uniform pattern can be formed, the uniformity of the switching characteristics can be improved, thereby improving the operational reliability of the device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, if a part such as a layer, film, area, etc. is expressed as “upper” or “on” another part, each part is different from each part as well as being “right up” or “directly above” another part. This includes the case where there is another part between parts.

1 is a plan view of a resistance change memory device according to a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram.

Referring to FIG. 1, a resistance change memory device according to a first exemplary embodiment may include a plurality of first wires 100 extending in one direction and a plurality of conductive wires protruding in contact with side surfaces of the first wire 100. A plurality of acute angles extending from the pattern 200, the variable resistance layer 300 formed on the plurality of conductive patterns 200, and the first wiring 100 so as to pass through a portion of the plurality of conductive patterns 200. The second wiring 400 and the plurality of third wirings formed on the variable resistance layer 300 and extending in a direction orthogonal to the second wiring 400 so as to pass through the remaining portions of the plurality of conductive patterns 200. 500. Here, the first wiring 100 is a lower wiring formed under the variable resistance layer 300, and the second and third wirings 400 and 500 are upper wirings formed on the variable resistance layer 300.

The plurality of first wires 110, 120, and 130; 100 may extend in one direction, for example, in a horizontal direction. Each of the plurality of first wires 100 may be formed to have a predetermined width, spacing, and thickness. For example, the plurality of first wires 100 may be formed to have a width, spacing, and thickness of 1 F (feature size). 1F refers to a minimum size that can be formed by a lithography process, and may be 30 nm, 45 nm, or the like, depending on the device. In addition, the first wiring 100 may be formed using a conductive material. For example, aluminum (Al), iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), and titanium nitride It can be formed using at least one of (TiN) and polysilicon, it can be formed of a single layer or a plurality of layers.

The plurality of conductive patterns 210, 220, and 230; 200 protrude from the side surfaces of the first wiring 100 at predetermined widths and intervals. That is, the conductive pattern 200 protrudes from the upper side surface and the lower side surface of the first wiring 100 in the longitudinal direction of the first wiring 100. For example, a plurality of conductive patterns 211 and 212 are formed at upper and lower sides of the first first wiring 110, and a plurality of conductive patterns 221 are formed at upper and lower sides of the second first wiring 120. And 222 is formed, and a plurality of conductive patterns 231 and 232 are formed on the upper side surface and the lower side surface of the third first wiring 130. Meanwhile, each of the conductive patterns 200 is formed such that adjacent conductive patterns 200 are not shorted to each other in consideration of the width and the spacing of the first wiring 100. For this, for example, a width of 0.3F or less is preferable. Preferably it may be formed in a width of 0.2F or 0.1F. In addition, the interval between the conductive patterns 200 is equal to the width of the conductive pattern 200, or the width and the interval of the second wiring 400 and the third wiring 500 overlapping the conductive pattern 200. The gap between the conductive patterns 200 may be wider than the width of the conductive patterns 200 in consideration of the like. Therefore, at least four conductive patterns 200 may be formed in an area of 4F ² . In addition, each of the plurality of conductive patterns 200 may function as a unit device for storing respective data according to voltages applied to the first wiring 100, the second wiring 400, or the third wiring 500. have. Therefore, at least 4 bits of data can be stored in an area of 4F ² . In addition, the plurality of conductive patterns 200 may be formed thicker than the thickness of the first wiring 100. The conductive pattern 200 may be formed using a conductive material, for example, aluminum (Al), iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), and titanium nitride (TiN). And at least one of polysilicon. In addition, the conductive pattern 200 may be formed of the same material as the first wiring 100.

The variable resistance layer 300 is formed on the entire top including the plurality of first wires 100 and the plurality of conductive patterns 200. The variable resistance layer 300 may be formed using a material whose resistance changes according to a voltage applied between the first wiring 100 and the second and third wirings 400 and 500. The variable resistance layer 300 may use a metal oxide, PCMO (Pr _{1 - X} Ca _X MnO ₃ , 0 <X <1), chalcogenide, perovskite, or a metal doped solid electrolyte. Can be. The metal oxide may comprise SiO ₂ , Al ₂ O ₃ or a transition metal oxide, wherein the transition metal oxide is HfO ₂ , ZrO ₂ , Y ₂ O ₃ , TiO ₂ , NiO, Nb ₂ O ₅ , Ta ₂ O ₅ , CuO, Fe ₂ O ₃ or lanthanoids oxide (lanthanoids oxide) can be included, the lanthanoids are lanthanum (La), cerium (Ce), prasedium (Pr), neodymium (Nd), samarium (Sm), Gadolium (Gd) or dysprosium (Dy). In addition, the chalcogenide may comprise GeSbTe, perovskite teuneun SrTiO _3, Cr or Nb-doped may include SrZrO _3, metal doped solid electrolyte comprising a Ag is doped into GeSe, i.e. AgGeSe can do. Although not shown, a tunneling barrier (not shown) may be further formed below the variable resistance layer 300, that is, between the variable resistance layer 300, the first wiring 100, and the conductive pattern 200. The tunneling barrier is a film that can tunnel electrons by changing a potential barrier when the electric field applied to both ends is above a predetermined voltage. For example, SiO ₂ , Al ₂ O ₃ , HfO ₂ having a thickness of about ₂ to 5 nm. Or it may have a laminated structure such as SiO ₂ / HfO ₂ . When such a tunneling barrier is formed, a leakage current may be minimized by applying an electric field below a predetermined voltage to an unselected cell.

The plurality of second wires 410 to 470; 400 extend in an oblique direction forming an acute angle, for example, an angle of 45 ° with the first wire 100, for example, extending from a left upper side to a right downward side. . The plurality of second wirings 400 are formed to pass through the conductive pattern 210 formed on the first wiring 100. For example, the second second wiring 420 may have a conductive pattern 211a of the first first wiring 110, a conductive pattern 221b of the second first wiring 120, and a conductivity of the third first wiring line 130. It extends past the pattern 231c. That is, the second wiring 400 is the n + 1 th conductive on the n + 1 th first wiring 100, n + 1 from the n th conductive pattern 200, n on the n th first wiring 100, n. The patterns 200 and n + 1 extend to pass through the n + 2th conductive patterns 200 and n + 2 on the n + 2nd first wirings 100 and n + 2. The plurality of second wires 400 may be formed of a conductive material, and may be formed of the same material as the first wires 100 and the conductive pattern 200. In addition, the second wiring 400 may be formed to have a predetermined width in consideration of the width and spacing of the conductive pattern 200. For example, the second wiring 400 may be formed to have the same width as the conductive pattern 200.

The plurality of third wires 510 to 570; 500 form an acute angle, for example, 45 °, with the first wire 100 and extend in a direction perpendicular to the second wire 400. For example, it extends from the upper right to the lower left. In addition, the third wiring 500 passes over a portion of the conductive pattern 200 that is not connected to the second wiring 400, that is, over the conductive patterns 212, 222, and 232 formed under the first wiring 100. It is formed so as to extend. For example, the second third wiring 520 may include a conductive pattern 212c on the first first wiring 110, a conductive pattern 222b on the second first wiring 120, and a conductive pattern on the third first wiring 130. 232a extends past the phase. That is, the third wiring 500 is n on the n + 1th first wirings 100 and n + 1 from the n + 2th conductive patterns 200 and n + 2 on the nth first wirings 100 and n. The nth conductive patterns 200 and n + 1 are extended to pass through the nth conductive patterns 200 and n on the n + 2th first wirings 100 and n + 2. The plurality of third wires 500 may also be formed of a conductive material, and may be formed of the same material as the first wires 100, the conductive patterns 200, and the second wires 400. In addition, the third wiring 500 may be formed to have a predetermined width in consideration of the width and the gap of the conductive pattern 200 and the second wiring 400, for example, the conductive pattern 200 and the second wiring ( It may be formed to the same width as 400).

As described above, the resistance change memory device according to the first exemplary embodiment may include the first wiring 100 according to a voltage applied to the first wiring 100, the second wiring 400, or the third wiring 500. And a conductive path is formed (low resistance state) or formed in the variable resistance layer 300 between at least one of the conductive pattern 200 and at least one of the second wiring 400 and the third wiring 500. Is disconnected (high resistance state). For example, when a predetermined voltage is applied to the first wiring 100 and a predetermined voltage is applied to the selected one of the second wirings 400, the conductive pattern between the selected first wirings 100 and the second wirings 400 is applied. A conductive path is formed in the variable resistance layer 300 between the 200 and the second wiring 400 to store one bit of data. Thus, a conductive pattern 200 may store data of one bit, to form at least four conductive patterns 200 in the area of 4F ² it can store the data of at least 4 bits in the area of 4F ² .

FIG. 2 is an equivalent circuit diagram of a resistance memory device according to a first exemplary embodiment of the present invention, and a plurality of first wirings D11 to D15 and D10 arranged in one direction, for example, a horizontal direction, and a first wiring D10. A plurality of second wirings D21 to D24 arranged in an oblique direction spaced up and down and formed at an acute angle, and vertically spaced apart from the first wiring D10 and perpendicular to the second wiring D20 in a plane. A plurality of third wirings D31 to D34 (D30) arranged in a direction are provided, and the region A and the first wiring D10 formed by two adjacent second wirings D20 and D30 are respectively formed. Four unit elements R1, R2, R3 and R4 are provided in between. The resistive memory device according to the first exemplary embodiment may program data into at least one selected from the unit devices R1, R2, R3, and R4, and may read or erase the data. That is, the unit elements R1, R2, R3, and R4 can be driven independently or simultaneously.

 The driving method of the resistive memory device according to the first exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 5 as follows.

3 is an equivalent circuit diagram illustrating a method of programming a resistance change memory device according to a first exemplary embodiment of the present invention, and illustrates an example of storing one bit of data in a selected unit device.

Referring to FIG. 3, a predetermined voltage, for example, 1 / 2V _write is applied to the first wiring D12 connected to the selected unit device R1, and the other first wirings D11, D13, D14, and D15 are applied. Apply ground voltage (0V). Then, a predetermined voltage, for example, -1 / 2V _write is applied to the second wiring D22 connected to the selected unit device R1, and the remaining second wirings D21, D23, and D24 other than the second wiring D22 are applied. ) And the ground voltage (0V) is applied to the third wirings (D31, D32, D33, and D34). In this case, a program voltage, that is, a voltage of V _write is applied to the selected unit device R1. Therefore, data is programmed in one unit element R1 in a low resistance state or a high resistance state. At this time, an electric field of 1/2 V _write is applied to the unit elements between the selected first wiring D12 and the unselected second and third wirings D20 and D30, but the electric potential required for the data program does not become programmed. . In addition, no voltage is applied to the remaining unit elements between the unselected first wires D11, D13 and D14 and the unselected second and third wires D20 and D30, so that data is not programmed.

In addition, a predetermined voltage (1 / 2V _write ) is applied to the first wiring D12 connected to the unit device R2 in this manner, and the predetermined voltage (−1 / only) is applied only to the third wiring D31 connected to the unit device R2. When 2V _write is applied, data is programmed in the selected unit device R2. Applying a first wiring (D12) the predetermined voltage (1 / 2V _write) and the applied predetermined voltage (-1 / 2V _write) to the second wiring (D23) and a third wiring (D32) in the same way, when each unit element Data is programmed in each of R3 and the unit element R4.

As well as applying a first wiring (D12) the predetermined voltage (1 / 2V _write) the application and a second wiring (D22 and D23) and the third wiring predetermined voltage (-1 / 2V _write) to (D31 and D32) in Data can be programmed into the unit elements R1, R2, R3, and R4.

Accordingly, at least one unit device may be programmed according to voltages applied to the first wiring D10, the second wiring D20, and the third wiring D30.

4 is an equivalent circuit diagram illustrating an example of a read operation of a resistance change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a predetermined read voltage, for example, V _read is applied to the first wiring D12 to which the selected device R1 is connected, and the remaining first wiring D110, to which the selected device R1 is not connected, is applied. The ground voltage (0V) is applied to D13, D14, and D15. The ground voltage OV is applied to the second wiring D22 to which the selected element R1 is connected, and the read voltage V _read is applied to the remaining second wirings D21, D23, and D24 and the third wiring D30. Apply a voltage between ground and OV, for example 1 / 2V _read . In this case, a potential difference between the read voltage V _read exists between the first wire D12 and the second wire D22 with the selected element R1 interposed therebetween. At this time, when the selected element R1 is programmed to a low resistance state, a conductive path exists in the first wiring D12 and the second wiring D22, and accordingly, the second wiring D22 is read voltage V _read . You will have a level of. Thus, it is recognized that the selected element R1 is programmed to a low voltage state. In addition, when the selected element R1 is programmed to a high resistance state, conductive paths do not exist in the first wiring D12 and the second wiring D22, and accordingly, the second wiring D22 has a ground voltage (0V). ) Level.

Of course, the program states of the plurality of unit elements R1, R2, R3, and R4 formed on the selected first wiring D12 may be read at a time. In this case, the read voltage V _read is applied to the first wiring D12. The ground voltage (0V) is applied to all the second wirings D20 and the third wirings D30 connected to the unit device to be read. In addition, the unit devices R1, R2, R3, and R4 are sensed by sensing a voltage change of the second wiring D20 and the third wiring D30 according to the resistance state of the unit devices R1, R2, R3, and R4. Done. That is, when the second wiring D20 and the third wiring D30 maintain the high voltage state, that is, the level of the read voltage V _read , the unit elements R1, R2, R3, and R4 are programmed to a low resistance state. When the second wiring D20 and the third wiring D30 maintain the low voltage state, that is, the level of the ground voltage 0V, it is determined that the unit elements R1, R2, R3, and R4 are programmed to the low resistance state. .

FIG. 5 is an equivalent circuit diagram illustrating an example of an erase operation of a resistance change memory according to a first exemplary embodiment of the present invention.

Referring to FIG. 5, all unit elements are applied by applying a ground voltage (0V) to the first wiring D10 and an erase voltage, for example, V _erase , to the second wiring and the third wiring D20 and D30. _Applying an electric field of V _erase to erases data written to all unit elements.

As described above, the resistance change memory device according to the first exemplary embodiment may include a first wiring 100, a conductive pattern 200, a variable resistance layer 300, a second wiring 400, and a third wiring 500. ) May be stacked to form one device layer, and a plurality of such device layers may be stacked to manufacture a resistance change memory device having a three-dimensional structure. In this case, the conductive pattern 200, the second wiring 400, and the third wiring 500 may be selectively used in a manner of 1F or less, preferably 0.1F, using a double patterning process and a sidewall spacer process. It can be formed in a width of, the method of manufacturing a resistance change memory device according to a first embodiment of the present invention will be described in more detail with reference to the drawings.

FIG. 6 is a perspective view of a resistance change memory device according to a first embodiment of the present invention, and illustrates a resistance change memory device having a three-dimensional structure in which a plurality of device layers are stacked. Also, FIGS. 7A to 7N are cross-sectional views of a process sequence of a state cut along the lines A-A 'and B-B' of FIG. 6.

6 and 7A, a substrate 10 having a predetermined structure is provided. The substrate 11 can be applied to any conventional semiconductor memory device, and is not particularly limited in the present invention. For example, the substrate 11 may be a Si substrate, a SiO ₂ substrate, a Si / SiO ₂ multilayer substrate, a polysilicon substrate, or the like. It is available. In addition, a rectifying element (not shown) may be formed on the substrate 10. The rectifying element may comprise a diode or a transistor. The diode may be manufactured by forming p impurity regions (not shown) and n impurity regions (not shown) in the impurity ion implantation process in the substrate 10. The transistor is formed by stacking a gate insulating film (not shown) and a gate electrode (not shown) on the substrate 10, and source / drain regions (not shown) by an impurity ion implantation process in the substrate 10 on both sides of the gate electrode. It can manufacture by forming a. In addition, an insulating film (not shown) may be further formed on the substrate 10 to cover the rectifying device. The conductive layer 100a and the first mask film 20 are formed on the substrate 10. The conductive layer 100a may include a conductive layer including at least one of aluminum (Al), iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), titanium nitride (TiN), and polysilicon. It may be formed using a single layer or may be formed of a single layer or a plurality of layers. In addition, the first mask layer 20 may be formed of a material having a different etching rate from that of the conductive layer 100a and having a different etching rate from that of the second mask layer to be formed. For example, an insulating material such as a silicon oxide film or a silicon nitride film may be used. It is available. In addition, the thickness of the first mask layer 20 may be adjusted in consideration of the thickness of the conductive pattern to be formed.

6 and 7B, after forming a photoresist film (not shown) on the first mask film 20, the first mask film 20 and the conductive layer 100a are formed by a photolithography and an etching process using a predetermined mask. Pattern. As a result, the first wiring 100 is formed, and the first mask film 20 is patterned and remains thereon. The first wiring 100 and the first mask film 20 may extend in one direction, for example, in a horizontal direction, and may be formed in a plurality of widths and intervals, for example, 1F.

6 and 7C, a conductive layer (not shown) is formed over the entire surface including the patterned first mask layer 20. The conductive layer may be formed using a conductive material including the same material as the first wiring 100. The conductive layer is then etched back. Accordingly, the conductive layer remains on sidewalls of the stacked first wiring 100 and the first mask film 20 to form a first sidewall spacer 200a. In this case, the width of the first sidewall spacer 200a may vary depending on the thickness of the conductive layer, the stack height of the first wiring 100 and the first mask layer 150. For example, it is formed to a width of 0.3F, preferably 0.1F. This is to prevent the first sidewall spacers 200a formed between the first wires 100 maintaining the interval of 1F from being shorted to each other.

6 and 7D, the second mask layer 30 is formed over the entire surface including the first sidewall spacer 200a and the first mask layer 20. For example, the second mask layer 30 may be formed of a material having an etching rate different from that of the first mask layer 20. For example, when the first mask film 20 is formed of a silicon nitride film, the second mask film 30 may be formed of a silicon oxide film. In addition, the second mask layer 30 may be formed of not only a silicon oxide layer but also various materials that are easily etched. Subsequently, after forming a photoresist film (not shown) on the second mask film 30, the second mask film 30 is patterned by a photolithography and an etching process using a predetermined mask. At this time, the second mask film 30 remains in a direction orthogonal to the first mask film 20, and preferably has the same width and spacing as the first mask film 30, for example, the width and spacing of 1F. Is patterned.

6 and 7E, an insulating layer (not shown) is formed over the entire surface, and then the entire surface is etched to form second sidewall spacers 200b on sidewalls of the second mask layer 30. The insulating layer may be formed of a material having an etching rate different from that of the second mask layer 30. For example, the insulating layer may be formed of a silicon nitride film similarly to the first mask film 20.

6 and 7F, the second mask layer 30 is etched and removed using the second sidewall spacer 200b as an etch mask. Here, since the second sidewall spacer 200b and the first mask layer 20 are formed of a material having an etch selectivity different from that of the second mask layer 30, the second sidewall spacer 200b is removed when the second mask layer 30 is removed. The wall spacer 200b and the first mask layer 20 are not damaged by etching. Subsequently, a portion of the first sidewall spacer 200a exposed by removing the second mask layer 30 is etched to expose the substrate 10.

6 and 7G, the second sidewall spacer 200b and the first mask layer 20 are removed. Thus, the plurality of conductive patterns 200 are completed. The conductive pattern 200 is formed along the sidewall of the first wiring 100 from the substrate 10, for example, has a horizontal and vertical width of 0.1F, and is formed in a plurality at intervals of at least 0.1F.

6 and 7H, the variable resistance layer 300 is formed over the entire surface including the plurality of conductive patterns 200. The variable resistance layer 300 is formed thicker than the thickness of the conductive pattern 200. This is to allow a conductive path to be formed in the variable resistance layer 300 according to the voltage between the conductive pattern 200 and the second wiring 400 or the third wiring 500 thereon. If the variable resistance layer 300 is formed at the same height as the conductive pattern 200 or has a lower thickness than the conductive pattern 200, the conductive pattern 200, the second wiring 400, and the third wiring 500 are formed. ) May be shorted and cause a malfunction of the device. A film, a chalcogenide (chalcogenide) film, a perovskite (perovskite) film or a metal doping _- such a variable resistance layer 300 is a metal _{oxide, PCMO (X Ca X MnO 3} , 0 <X <1 Pr 1) A material containing a solid electrolyte membrane can be used. In addition, the variable resistance layer 300 may include a physical vapor deposition (PVD), molecular beam such as pulsed laser deposition (PLD), thermal evaporation, and electron-beam evaporation. It can be formed using a variety of deposition methods, such as epitaxial deposition (Molecular Beam Epitaxy (MBE)) or chemical vapor deposition (CVD).

6 and 7I, the conductive layer 400a is formed over the entire surface including the variable resistance layer 300. The conductive layer 400a may be formed using a conductive material including the same material as the first wiring 100 and the conductive pattern 200. Next, the photosensitive film 40 is formed on the conductive layer 400a.

6 and 7J, the photosensitive film 40 is patterned in two exposure and development processes. That is, the photosensitive film 40 first exposes the 2F unexposed area | region by the width | variety of 1F, for example after first exposure by the interval of 1F width | variety and 2F. In this way, there are regions exposed at a width of 1F and regions not exposed at a width of 0.5F. Similarly, for example, if a first exposure is performed at a width of 1F and a 1.2F interval, then an unexposed area of 1.2F is secondly exposed at a width of 1F, the area exposed at a width of 1F and a width of 0.1F are not exposed. There is an area that is not present. By such a double patterning method, the photoresist pattern 40a having a fine width may be formed. Subsequently, the first and second exposed regions are developed using a predetermined developer. Thus, a photosensitive film pattern 40a having a width of 0.5F, preferably 0.1F is formed. In this case, the photoresist pattern 40a is patterned to extend in an oblique direction from the upper left side to the lower right side, for example, at an angle of 45 ° with the first wiring 100. In addition, the photosensitive film pattern 40a is formed to pass through the conductive pattern 200 formed in contact with a portion of the plurality of conductive patterns 200, for example, one side of the wiring 100.

6 and 7K, the conductive layer 400a is patterned by an etching process using the photoresist pattern 40a as an etching mask. Therefore, a second wiring 400 formed in an oblique direction is formed to form an acute angle with the first wiring 100 while passing through a portion of the conductive pattern 200.

6 and 7L, an insulating film 50 is formed over the entirety of the second wiring 400. The insulating film 50 is preferably formed using a variable resistance layer 300 and a material having a high etching selectivity. For example, the insulating film 50 may be formed using an insulating material such as an amorphous carbon film, a silicon oxide film, or a silicon nitride film. Next, a predetermined region of the insulating layer 460 is etched to form a plurality of trenches 60. The plurality of trenches 60 extend in a direction orthogonal to the second wiring 400 and are formed to expose the variable resistance layer 300 on the conductive pattern 200 in which the second wiring 400 does not pass thereon. . In this case, the trench 60 may be formed by two exposure and development processes, that is, a double patterning process, after forming a photoresist film (not shown) on the insulating film 50. That is, for example, if the first exposure at the interval of 1F width and 1.2F is followed by the second exposure of the unexposed area of 1.2F to the width of 1F, the area exposed to the width of 1F and the width of 0.1F are not exposed. There is an area that is not present. Subsequently, the exposed region of the photoresist film is removed to form a photoresist pattern, and the insulating film 50 is etched using the photoresist pattern as an etch mask to form a plurality of trenches 60. Meanwhile, an etch stop layer (not shown) may be further formed between the insulating layer 50 and the variable resistance layer 300 to prevent the lower portion of the variable resistance layer 300 from being damaged by etching when the insulating layer 50 is etched. have. In this case, the etch stop layer may be formed of a material having a large etching selectivity with the insulating layer 50. For example, when the insulating layer 50 is formed of a silicon oxide layer, the etch stop layer may be formed of a silicon nitride layer.

6 and 7M, a conductive layer (not shown) is formed to fill the plurality of trenches 60 on the insulating film 50. After the photoresist layer (not shown) is formed on the conductive layer, the photoresist layer is patterned by the same double patterning process as the process for forming the plurality of trenches 60. As a result, a plurality of third wires 500 extending in a direction orthogonal to the second wires 400 are formed. That is, the third wiring 500 is formed to extend from the upper right side to the lower left side at an acute angle of, for example, 45 ° with the first wiring 100. In addition, the third wiring 500 may be formed to have the same resistance as the second wiring 400 in consideration of a portion embedded in the trench 60. This is to maintain the same signal transmission speed by making the resistances of the second wire 400 and the third wire 500 the same.

Thus, the plurality of first wirings 100 extending in the horizontal direction, the plurality of conductive patterns 200 formed from the side surfaces of the first wirings 100, the variable resistance layer 300 formed on the conductive pattern 200, and The second wiring 400 is formed on the variable resistance layer 300 and extends to form an acute angle with the first wiring 100 so as to pass through a portion of the conductive pattern 200. The second wiring 400 and the insulating film ( A single layer device layer 1000 may be formed of the third wiring 500 that is insulated with the 50 interposed therebetween and formed to extend in a direction orthogonal to the second wiring 400.

6 and 7N, an interlayer insulating film 600 is formed on the device layer 1000, and the first wiring 100, the conductive pattern 200, and the variable resistance layer 300 are formed on the interlayer insulating film 600. ), The second wiring 400 and the third wiring 500 are stacked to form a plurality of device layers 2000 and 3000. In this way, a variable resistance memory device in which a plurality of device layers 1000, 2000, and 3000 are stacked is manufactured.

As described above, in the first embodiment of the present invention, the plurality of conductive patterns 200 are formed using sidewall spacers, and the second wiring 400 and the third wiring 500 are formed using double patterning. A variable resistance element having a three-dimensional structure in which these were stacked was manufactured. However, by using sidewall spacers and double patterning, not only the structure of the first embodiment of the present invention but also a variable resistance memory device having various structures capable of reducing the size of the device can be manufactured.

Hereinafter, other embodiments of the present invention that can reduce the size of the wiring by using sidewall spacers and double patterning will be described.

FIG. 8 is a plan view of a variable resistance memory device according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along the line A-A 'and line B-B' of FIG. 8. Here, only a plan view and a cross-sectional view of one device layer are illustrated, but a plurality of device layers may be stacked to form a variable resistance memory device.

8 and 9, the variable resistance memory device according to the second exemplary embodiment may include a plurality of first wires 100 extending in one direction and a plurality of first wires 100 formed in a predetermined region on the first wire 100. Of the conductive pattern 200, the insulating layer 250 formed between the plurality of conductive patterns 200, and the plurality of conductive patterns 200 are partially exposed, the insulating layer 450, and the plurality of conductive patterns 200. ) And a plurality of second wirings 400 formed in a direction orthogonal to the first wiring 100 and passing through the plurality of conductive patterns 200. Here, the first wiring 100 and the second wiring 400 are formed to have a width of 1F or less, for example, 0.5F, by using double patterning, and the conductive pattern 200 is formed by using sidewall spacers. can do.

The manufacturing method of the variable resistance memory device according to the second exemplary embodiment of the present invention will be described below.

10A to 10I are cross-sectional views of devices sequentially illustrating a method of manufacturing a variable resistance memory device according to a second exemplary embodiment of the present invention, and are taken along lines AA ′ and BB ′ of FIG. 9. It is sectional drawing of the element shown in the order of process.

Referring to FIG. 10A, a first conductive layer 100a is formed on a substrate 10 on which a predetermined structure is formed. The substrate 10 may be a Si substrate, a SiO ₂ substrate, a multilayer substrate of Si / SiO ₂ , a polysilicon substrate, or the like. In addition, a rectifying device (not shown) such as a diode or a transistor may be formed on the substrate 10, and an insulating film (not shown) may be further formed on the substrate 10 to cover the rectifying device. The rectifying element may comprise a diode or a transistor. The first conductive layer 100a may be formed of at least one of, for example, aluminum (Al), iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), titanium nitride (TiN), and polysilicon. It may be formed using one conductive material and may be formed of a single layer or a plurality of layers. Subsequently, a first photosensitive film 40 is formed on the first conductive layer 100a.

Referring to FIG. 10B, the first photosensitive film 40 is patterned by two exposure and development processes, that is, a double patterning process. Here, the first photosensitive film 40 is first exposed at, for example, a width of 1F and an interval of 2F, and then secondly exposed unexposed 2F regions at a width of 1F. In this way, there are regions exposed at a width of 1F and regions not exposed at a width of 0.5F. Subsequently, the first and second exposed regions are developed using a predetermined developer. Thus, the first photosensitive film pattern 40a having a width of 0.5F is formed. In this case, the first photoresist pattern 40a is patterned in a shape extending in one direction, for example, a horizontal direction, and maintains a width of 1F between the first photoresist pattern 40a.

 Referring to FIG. 10C, the lower first conductive layer 100a is etched using the first photoresist pattern 40a as an etch mask. Thus, a plurality of first wirings 100 having a width of 0.5F and spaced at intervals of 1F are formed. After removing the first photoresist pattern 40a, the first mask layer 20 is formed on the substrate 10 on which the plurality of first interconnections 100 are formed. The first mask layer 20 may be formed of a material having a different etching rate from that of the first wiring 100. For example, an insulating material such as a silicon oxide film or a silicon nitride film may be used. In addition, the thickness of the first mask layer 20 may be adjusted in consideration of the thickness of the conductive pattern to be formed. Subsequently, the first mask film 20 is patterned by a photolithography and an etching process. In this case, the first mask film 20 extends in a direction perpendicular to the first wiring 100, that is, in a vertical direction, and is patterned to maintain, for example, a width and a spacing of 1F.

Referring to FIG. 10D, a conductive layer (not shown) is formed over the entire surface including the patterned first mask layer 20. The conductive layer may be formed using a conductive material including the same material as the first wiring 100. The conductive layer is then etched back. Therefore, the conductive layer remains on the sidewall of the first mask film 20 to form the first sidewall spacer 200a. In this case, the width of the first sidewall spacer 200a may vary depending on the thickness of the conductive layer, the stacking height of the first wiring 100 and the first mask layer 20, and the like, for example, 0.3F. It will remain in the width of 0.1F.

Referring to FIG. 10E, after removing the first mask layer 20, the second photoresist layer pattern 45 is formed on the first wiring 100. That is, after forming the second photoresist film (not shown) on the entire upper portion, the second photoresist film is patterned by using the double patterning process used when forming the first wiring 100. Therefore, the second photosensitive film pattern 45 is formed on the first wiring 100 in the same shape as the first wiring 100. Subsequently, the first sidewall spacers 200a exposing the second photoresist pattern 45 as an etching mask are etched. In other words, the sidewall spacer 200a remaining on the substrate 10 is removed.

Referring to FIG. 10F, after removing the second photoresist pattern 250, the first mask layer 20 is removed. As a result, a conductive pattern 200 having a width of 0.3 F or less while maintaining a predetermined interval, for example, 1 F, is formed on the first wiring 100.

Referring to FIG. 10G, an insulating layer 450 is formed on a region between the conductive patterns 200, that is, the substrate 10 and the first wiring 100 between the conductive patterns 200. In this case, the insulating layer 450 may be formed to expose a portion of the upper portion of the conductive pattern 200, and an insulating material such as a silicon oxide film or a silicon nitride film may be used. Subsequently, the variable resistance layer 300 is formed on the whole. Resistance variable layer 300 is a metal _{oxide, PCMO (Pr 1 - X Ca} X MnO 3, 0 <X <1) film, a chalcogenide (chalcogenide) film, a perovskite (perovskite) film or a metal-doped solid It may include an electrolyte membrane. In addition, the variable resistance layer 300 may include a physical vapor deposition (PVD), molecular beam such as pulsed laser deposition (PLD), thermal evaporation, and electron-beam evaporation. It may be formed using a epitaxy deposition method (Molecular Beam Epitaxy; MBE) or chemical vapor deposition (CVD).

Referring to FIG. 10H, the second mask layer 25 is formed over the entire surface. Subsequently, the second mask film 25 is patterned into the same shape as the shape of the patterned first mask film 20 by double patterning. That is, it extends in a direction orthogonal to the first wiring 100 using double patterning, and is patterned so that a portion where the conductive pattern 200 is formed is exposed. At this time, the interval between the second mask layer 25 may be patterned wider than the width of the conductive pattern 200, preferably equal to the width of the first wiring 100, for example, to a width of 0.5F Can be patterned. Therefore, the second mask layer 25 extends in the direction orthogonal to the first wiring 100 and is formed in a shape in which the lower conductive pattern 200 is exposed. A second conductive layer (not shown) is formed over the entire surface including the second mask layer 25. Subsequently, the second conductive layer is entirely etched to form second sidewall spacers 400a on sidewalls of the second mask layer.

Referring to 10i, when the second mask layer 25 is removed, a plurality of second wires 400 may be formed to overlap the lower conductive pattern 200 and extend in a direction orthogonal to the first wires 100. . After forming one device layer as described above, an interlayer insulating film 600 may be formed, and a plurality of device layers may be stacked to manufacture a variable resistance memory device having a three-dimensional structure.

FIG. 11 is a plan view of a variable resistance memory device according to a third exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the variable resistance memory device taken along line AA ′ of FIG. 11. It is a top view and sectional drawing of one element layer.

11 and 12, the variable resistance memory device according to the third exemplary embodiment may include a plurality of first wires 100 extending in one direction and a plurality of conductive wires formed in the first wire 100. A pattern 200, an insulating layer 250 formed over the entire surface including the conductive pattern, a contact hole 260 formed in a predetermined region of the insulating layer 250 to expose the conductive pattern 200, and a contact hole ( The variable resistance layer 300 formed on the conductive pattern 200 in the 260 and the plurality of second wirings 400 formed to fill the contact hole 260 and orthogonal to the first wiring 100 may be formed. Include. In addition, in the variable resistance memory device according to the second exemplary embodiment, the first wiring 100 and the second wiring 400 may be formed to have a width of 1F or less, preferably 0.5F, by using double patterning. Can be.

The manufacturing method of the variable resistance memory device according to the third exemplary embodiment of the present invention will be described below.

13A to 13D are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a variable resistance memory device according to a third embodiment of the present invention.

Referring to FIG. 13A, a plurality of first wires 100 extending in one direction are formed on the substrate 10 having a predetermined structure by using double patterning. That is, a conductive layer (not shown) and a photoresist film (not shown) are formed on the substrate 10, the photoresist is patterned by two exposure and development processes, and then the conductive layer is etched using the patterned photoresist as an etch mask to form a first wiring. Form 100. Here, the photoresist film is first exposed at an interval of 1F width and 2F, and then secondly exposed unexposed 2F area at a width of 1F, and thus is not exposed at a width of 1F and a width of 0.5F. After allowing the region to exist, it is patterned to have a width of 0.5 F by developing the first and second exposed regions using a predetermined developer. Thus, for example, the first wiring 100 has a width of 0.5F and is spaced apart at intervals of 1F.

FIG. 13B forms a plurality of conductive patterns 200 on the first wiring 100. The conductive pattern 200 may be formed using sidewall spacers, which will be described in more detail as follows. A plurality of first mask films (not shown) are formed on the substrate 10 including the first wiring 100 in a direction orthogonal to the first wiring 100, and conductive layers (not shown) are formed over the entirety. Afterwards, the conductive layer is etched entirely to form sidewall spacers (not shown) on the sidewalls of the first mask layer. Subsequently, a second mask film (not shown) is formed on the first wiring 100 in the same shape as the first wiring 100 and the sidewall spacers exposed by the second mask film are etched. Subsequently, when the first and second mask layers are removed, a plurality of conductive patterns 200 are formed on the first wiring 100.

Referring to FIG. 13C, after forming the insulating layer 250 over the entire surface, a first contact hole 260a is formed to expose the conductive pattern 200 by etching a predetermined region of the insulating layer 250. Here, the first contact hole 260a is formed to have a diameter larger than the width of the conductive pattern 200. This is because the conductive pattern 200 is formed by using the sidewall spacer, the width is smaller than 1F, for example less than 0.3F, the first contact hole 260a is due to the limitation of the photo process, for example This is because it is formed with a diameter of 1F. Therefore, the adjacent first contact holes 260a may be partially overlapped with each other.

Referring to FIG. 13D, a second insulating layer (not shown) having a predetermined thickness is formed on the entire upper portion including the first contact hole 260a such that the first contact hole 260a is not completely filled. Subsequently, the entire surface of the second insulating layer is etched to form sidewalls 260b on the sidewalls of the first contact holes 260a. Accordingly, a side wall 260b is formed in the first contact hole 260a to form a contact hole 260 that becomes narrower downward. In addition, adjacent contact holes 260 are not in contact.

Referring to FIG. 13E, after the variable resistance layer 300 is formed in the contact hole 260, a conductive layer is formed to fill the contact hole 260, and the conductive layer is patterned to be perpendicular to the first wiring 100. A second wiring 400 extending to the trench is formed. Here, the second wiring 400 may also be formed using double patterning.

In the method of manufacturing the resistive memory device according to the third exemplary embodiment, the first contact hole 260a having a larger diameter than the conductive pattern 200 may be formed to overlap the adjacent first contact hole 260a. Since the sidewall 260b is formed in the first contact hole 260a to form a contact hole 260 that becomes narrower toward the bottom, the adjacent contact hole 260 is not shorted.

Meanwhile, other embodiments of the present invention can be implemented using some of the features of the above-described embodiments of the present invention. For example, in the first embodiment of the present invention, the first wiring 100 may be formed to have a width of 0.5F or less by using double patterning. In the first embodiment, the first wiring 100 may be formed to have a width of 0.5F or less. Before the variable resistance layer 300 is formed, an insulating layer may be formed to expose a portion of the conductive pattern 200 as in the second embodiment of the present invention, and then a variable resistance layer may be formed thereon. In addition, in the first embodiment, the contact hole forming method of the third embodiment without forming the trench 60, that is, forming a contact hole and then forming a sidewall on the sidewalls of the contact hole may reduce the size of the contact hole. .

FIG. 14 is a schematic block diagram of an electronic product using a resistance change memory device as a data storage medium according to embodiments of the present disclosure.

Referring to FIG. 14, the electronic product 700 includes at least one resistance change memory device 710, a data storage medium, a processor 720 connected to the resistance change memory device 710, and an input connected to the processor 720. / Output device 730. Here, the resistance change memory device 710 may include any one of the resistance change memory devices according to the embodiments of the present invention described above.

The processor 720 may perform a function of controlling the resistance change memory device 710. In addition, the electronic product 700 may exchange data with another electronic product through the input / output device 730. In addition to data communication between the processor 720 and the resistance change memory device 710, data communication between the processor 720 and the input / output device 730 may be performed using data bus lines.

The electronic product 710 may be a data storage device such as a memory card, an information processing device such as a computer, a digital camera, or a cellular phone.

Although the technical spirit of the present invention has been described in detail according to the above embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a plan view of a variable resistance memory device according to a first exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a variable resistance memory device according to a first exemplary embodiment of the present invention.

3 to 5 are equivalent circuit diagrams for describing a method of driving a variable resistance memory device according to a first embodiment of the present invention.

6 (a) and 6 (b) are perspective views of a variable resistance memory device according to a first embodiment of the present invention.

7 (a) to 7 (m) are cut along the AA 'and BB' lines of FIG. 6 (a) to explain a method of manufacturing a variable resistance memory device according to a first exemplary embodiment of the present invention. Sectional view in order of process.

8 is a plan view of a variable resistance memory device according to a second exemplary embodiment of the present invention.

9 (a) and 9 (b) are cross-sectional views taken along the lines A-A 'and B-B' of the variable resistance memory device according to the second embodiment of the present invention.

10 (a) to 10 (i) illustrate a process sequence of cutting along the AA ′ and BB ′ lines of FIG. 8 to explain a method of manufacturing a variable resistance memory device according to a second exemplary embodiment of the present invention. Shown as a cross-section.

11 is a plan view of a variable resistance memory device according to a third embodiment of the present invention.

12 is a cross-sectional view taken along the line A-A 'of the variable resistance memory device according to the third embodiment of the present invention.

13 (a) to 13 (d) are cross-sectional views in the order of steps taken along line AA ′ of FIG. 11 to explain a method of manufacturing a variable resistance memory device according to a third exemplary embodiment of the present invention. .

<Explanation of symbols for the main parts of the drawings>

100: first wiring 200: conductive pattern

300: variable resistance layer 400: second wiring

500: third wiring

Claims (34)

A plurality of first wirings arranged in one direction; A plurality of conductive patterns connected to the first wirings; A variable resistance layer formed on the conductive pattern; A plurality of second wirings arranged in a direction crossing the first wiring so as to pass a portion of the conductive pattern on the variable resistance layer; And And a plurality of third wires arranged in a direction crossing the first wire so as to pass through the remaining portion of the conductive pattern on the variable resistance layer. The variable resistance memory device of claim 1, wherein the conductive pattern protrudes upward from a side surface of the first wiring and is higher than a height of the first wiring. The variable resistance memory device of claim 2, wherein a plurality of conductive patterns are formed in an area of 4F ² . The variable resistance memory device of claim 1, wherein the conductive pattern protrudes from an upper portion of the first wire. The method of claim 1, wherein the variable resistance layer is metal oxide, PCMO (Pr _{1 - X} Ca _X MnO ₃ , 0 <X <1), chalcogenide, perovskite and metal doped A variable resistance memory device formed of at least one of a solid electrolyte. The variable resistance memory device of claim 5, further comprising a tunneling barrier formed between the conductive pattern and the variable resistance layer. The variable resistance memory device of claim 1, wherein the second wiring extends at an acute angle with the first wiring in a planar direction. The variable resistance memory device of claim 7, wherein the third wiring forms an acute angle with the first wiring in a planar direction and extends in a direction orthogonal to the second wiring. The variable resistance memory device of claim 8, further comprising an insulating layer provided between the second wiring and the third wiring. The variable resistance memory device of claim 9, wherein the third wiring is formed on and in contact with the variable resistance layer on the conductive pattern through a hole or a trench formed in the insulating layer. The variable resistance memory device of claim 10, wherein the second wiring passes through the conductive pattern formed on one side of the plurality of first wirings. The variable resistance memory device of claim 11, wherein the third wiring is formed to pass over the conductive pattern formed on the other side surface of the plurality of first wirings. The variable resistance memory device of claim 1, wherein the plurality of first wirings, conductive patterns, variable resistance layers, second wirings, and third wirings form one device layer, and the plurality of device layers are stacked. The variable resistance memory device of claim 13, further comprising an interlayer insulating layer formed between each of the plurality of device layers. A plurality of lower wires arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections crossing the plurality of lower interconnections and arranged in a direction orthogonal to the plurality of first upper interconnections; And And a plurality of variable resistance elements formed between the lower interconnections and the first and second upper interconnections. The variable resistance memory device of claim 15, wherein the variable resistance element comprises a conductive pattern formed on the first wiring and a variable resistance layer formed on the conductive pattern. 17. The method of claim 16 wherein the conductive pattern is formed of a plurality in the area of 4F ² resistance variable memory element which can be a plurality of bit program area of 4F ^2. A plurality of lower wires arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections crossing the plurality of lower interconnections and arranged in a direction orthogonal to the plurality of first upper interconnections; And A plurality of variable resistance elements formed between the lower interconnections and the first and second upper interconnections, Program the at least one variable resistance element by applying a first program voltage to at least one selected from among the lower interconnections, and applying a second program voltage to at least one selected from among the first and second upper interconnections, A variable resistance memory reading a program state of the variable resistance element by applying a read voltage to the lower line connected to the selected variable resistance element and applying a ground voltage to the first or second upper line connected to the selected variable resistance element Method of driving the device. 19. The method of claim 18, wherein the first program voltage is a positive voltage and the second program voltage is a negative voltage. 20. The method of claim 19, wherein a ground voltage is applied to the unselected lower interconnections and the unselected first and second upper interconnections when programming the selected variable resistive element. 19. The method of claim 18, wherein the program state of the variable resistance element is read by sensing a change in potential of the first upper line or the second upper line connected to the selected variable resistance element. 20. The variable resistance memory of claim 19, wherein a lower voltage than the read voltage is applied to the lower wirings, the first and the second upper wirings connected to the non-selected variable resistance elements when the program state of the selected variable resistance element is read. Method of driving the device. Forming a plurality of lower wires extending in one direction on the substrate; Forming a plurality of conductive patterns using sidewall spacers to be connected to the lower wirings; Forming a variable resistance layer on the plurality of conductive patterns; And Forming a plurality of upper interconnections on the variable resistance layer by double patterning so as to pass over the plurality of conductive patterns. 24. The method of claim 23, wherein the upper interconnection comprises: forming a plurality of first upper interconnections on the variable resistance layer using the double patterning to pass a portion of the plurality of conductive patterns; And And forming a plurality of second upper wires insulated from the first upper wires and extending in a direction orthogonal to pass through the remaining portions of the plurality of conductive patterns. The method of claim 24, wherein the forming of the plurality of conductive patterns comprises: Stacking a plurality of first mask films on the plurality of lower wirings and forming conductive layer sidewall spacers on the side surfaces thereof; Forming a plurality of second mask films in a direction orthogonal to the lower wirings, and forming insulating layer sidewall spacers on the sidewalls; Removing the second mask layer using the insulating layer sidewall spacer as an etch mask; Selectively removing the conductive layer sidewall spacers exposing the insulating layer sidewall spacers and the first mask layer as an etch mask; And And removing the insulating layer sidewall spacers and the first mask layer. 26. The method of claim 25, wherein the second mask layer is formed of a material having an etch rate different from that of the first mask layer and the insulating layer sidewall spacer. 25. The method of claim 24, further comprising forming an insulating layer on the substrate to partially expose the conductive pattern. The method of claim 24, wherein the forming of the first upper wiring comprises: Forming a conductive layer and a photosensitive film on the variable resistance layer; First exposing the photosensitive film to form an exposure area of a first width and an unexposed area of a second width; Secondarily exposing the non-exposed areas of the photosensitive film to a first width; Developing the primary and secondary exposure regions to form a photoresist pattern; And etching the conductive layer using the photoresist pattern as an etch mask. 25. The method of claim 24, further comprising: forming a contact hole in the insulating layer to open another portion of the conductive pattern after forming the insulating layer on the first upper wiring; And forming a contact hole on the insulating layer to fill the contact hole. The method of claim 29, wherein forming the contact hole comprises: Etching the insulating layer to expose the variable resistance layer on another portion of the conductive pattern to form a first contact hole larger than the contact hole; And And forming a sidewall on a side surface of the first contact hole. The method of claim 30, wherein the forming of the second upper interconnection comprises: Forming a conductive layer and a photosensitive film on the insulating layer to fill the contact hole; First exposing the photosensitive film to form an exposure area of a first width and an unexposed area of a second width; Secondarily exposing the non-exposed areas of the photosensitive film to a first width; Developing the primary and secondary exposure regions to form a photoresist pattern; And etching the conductive layer using the photoresist pattern as an etch mask. 24. The method of claim 23, wherein the plurality of lower interconnections are formed using double patterning. 24. The method of claim 23, further comprising: forming an interlayer insulating film on the upper wiring; And The method may further include forming a device layer by sequentially forming the lower wiring, the conductive pattern, the variable resistance layer, and the upper wiring, And manufacturing a three-dimensional structure by laminating a plurality of the interlayer insulating films and the device layers. An electronic product having a resistance change memory device and a processor connected thereto. The resistance change memory device, A plurality of lower wires arranged in one direction; A plurality of first upper wires arranged in a direction crossing the plurality of lower wires; A plurality of second upper interconnections crossing the plurality of lower interconnections and arranged in a direction orthogonal to the plurality of first upper interconnections; And An electronic product comprising a plurality of variable resistance elements formed between the lower wiring and the first and second upper wiring.

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