KR100436138B1 - Device and Method for Transferring and Receiving IPC Basing on ATM Cell Between Processor - Google Patents

Abstract

The present invention relates to an inter-processor inter-processor AMT cell-based IP transceiver device and method, and in particular, to prevent abnormal reassembly when receiving a cell generated during inter-processor communication and during the processor's own lookback test. The present invention relates to an inter-processor ATM cell-based IP transceiver device and method.

An interprocessor ATM cell-based IPC transmission / reception apparatus according to an embodiment of the present invention includes a cell multiplexing / demultiplexing unit for replicating ATM cells received from an upper block in a group on an active and standby side; Characterized in that it comprises a processor for transmitting a message to the VPI / VCI channel of the active side of the other processor.

Description

Device and method for transfer between ATM cells based on PC between processors {Device and Method for Transferring and Receiving IPC Basing on ATM Cell Between Processor}

The present invention relates to an inter-processor inter-processor AMT cell-based IP transceiver device and method, and more particularly, to prevent abnormal reassembly when receiving a cell generated during inter-processor communication and the processor's own lookback test. The present invention relates to an ATM cell based IPC transceiver and method.

In general, an ATM switch is connected to a Pseudo Universal Test Operations PHY Interface for ATM (ATM) bus, as shown in FIG. 1, to perform routing of communication messages with the processor. Cell Mux Demux Assembly (hereinafter referred to as "CMDA") for converting serial data between the unit 10 and the AMC and the processor into UTOPIA data. The 20, the processor 30, and the ATM switch unit 40 is largely divided, the processor unit 30 and the CMDA unit 20 is matched with a cross-redundant hot link (hot link) The CMDA unit 20 and the AMC unit 10 are connected by a similar utopia bus, and the AMC unit 10 and the ATM switch unit 40 are connected by a 622 Mbps Low Voltage Differential Signal (LVDS) link.

The CMDA unit 20 may operate by matching M processor units at the same time, and the first processor unit 30 is a processor unit (SMP: System Management Processor) in charge of operating and maintaining the system. In charge of. All processors download and operate a program from the SMP. When the non-active processor, that is, a standby processor downloads a program from the SMP, is called standby loading.

In the conventional ATM switch, a plurality of processor units are sequentially matched to the CMDA unit 20, and the CMDA unit 20 hot links the IPC (Inter Processor Communication) based on the matched processor unit 30 and the ATM cell. Link). The transmitting cell of the processor unit 30 is transmitted to each port of the CMDA unit 20, and the CMDA unit 20 converts the ATM cell received at each port into a 56-byte pseudo utopia ATM cell and converts it into an AMC unit. When writing to FIFO (First-in-First-out) so that it can be transmitted to (10), AMC unit 10, which is a similar utopia master unit, is connected so that this ATM cell can be routed from the switch. Connection) is transmitted to the ATM switch unit 40 in units of cells in which an information field is inserted. At this time, the message transmitted to the ATM switch unit 40 is routed to the location where the corresponding processor unit exists by looking at the connection information, and is received by the AMC unit 10 again. The AMC unit 10 analyzes the received cell again, finds the port information of the processor, inserts the information into the 56-byte cell, and transmits the information to the FIFO of the CMDA unit 20 through the pseudo-utopia bus. The CMDA unit 20 analyzes the cell to find the corresponding port and transmits it to the hot link. Each processor has a VPI / VCI (Virtual Path Identifier / Virtual Channel Identifier), respectively. The transmitting processor transmits to the VPI / VCI of the receiving processor. The AMC unit 10 has the VPI / VCI and port information. Attach the connection information to transmit the cell to the ATM switch unit 40, the reverse cell is transferred to the processor by changing the VPI / VCI information of the processor transmitted from the AMC unit 10 to the cell. The receiving processor must prepare a corresponding VPI / VCI channel in advance, and a message received with the same VPI / VCI receives an IPC message through reassembly.

Conventionally, the hot link has a fixed port. When the active and standby of the processor unit are switched, the hot link port is not changed, and the CMDA unit 20 converts the port information into a 56 byte cell along with the VPI / VCI. 10), the AMC unit 10 could not distinguish between active and standby positions of the processor unit 30 through this message.

In addition, the processor unit 30 has a structure in which the VPI / VCI on the active side is always fixed so that the same information is always maintained even when the A side and the B side exchange information. The cell destined for the ATM switch unit 40 is called an ingress cell, and the cell exiting from the ATM switch unit 40 is called an egress cell. The AMC unit 10 is 56 bytes long. Based on the port / VPI / VCI information included in the ingress cell, the connection information is pasted and transmitted to the ATM switch unit 40, and the AMC unit 10 receiving the egress cell analyzes the cell again and analyzes the corresponding VPI / VCI. It changes the port / VPI / VCI information of the processor to find the transmission in the table, and transmits to the CMDA unit 20, CMDA unit 20 transmits to the corresponding port.

The changed information cannot be determined by the information contained in the cell in the AMC unit 10, so the A side (0, 2, 4, 6 ... port) is always active regardless of whether the processor unit 30 is switched. Since the cell is determined to be sent by the processor, and the cell change is made based on this, even when the lookback test is performed, the message sent by the B side in the active state is similar to the message received from the A side by the AMC unit 10. It is determined and transmitted to the CMDA unit 20 as port information connected to the A side, and the CMDA unit 20 is transmitted to the A side (0, 2, 4, 6 ... port). In this case, the processor on the B side has a structure that cannot receive its own messages forever. That is, when the B side is active, the lookback cell is sent to the A side while passing through the CMDA unit 20, the AMC unit 10, and the ATM switch unit 40. Similarly, messages received from other processors have the same effect. In order to prevent this, the CMDA unit 20 has a function of copying a cell by forming a group such as (0, 1), (2, 3) ... received by the AMC unit 10. When copying like this, when the lookback message is an SMP processor, when a standby loading is performed, the cells are mixed and reassembled while receiving a program from the active processor through IPC. As a result, the received message is broken. This happens. ATM cells have different transmission times for each channel and channel, so even if cells are transmitted on different channels, the receivers will reassemble on the same channel if they have the same VPI / VCI. In the case of standby loading to the B side, there is a problem that the transmitted message is reassembled in a channel such as the A side itself lookback test message and B side, resulting in a broken result. In addition, another processor performing standby loading from the SMP may also perform a wrong reassembly while the A side and the B side receive a message transmitted from the SMP on the same channel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned general problems, and an object thereof is to prevent abnormal reassembly upon reception of a cell generated during inter-processor communication and a processor self-lookback test.

1 is a diagram showing an interprocessor ATM cell-based IPC transmission and reception apparatus according to the present invention.

Fig. 2 shows a case where an ATM cell is mixed with an SMP processor during standby loading and lookback test.

* Description of the symbols for the main parts of the drawings *

10: AMC part

20: CMDA Department

30: processor unit

40: ATM switch unit

In accordance with an aspect of the present invention, there is provided an interprocessor ATM cell-based IPC transmission / reception apparatus including: a cell multiplexing / demultiplexing unit for replicating ATM cells received from an upper block in a group on an active and standby side; Characterized in that it comprises a processor for transmitting a message to the VPI / VCI channel of the active side of the other processor.

In accordance with an aspect of the present invention, there is provided a method of transmitting and receiving an ATM cell-based IPC transmission / reception method for an ATM cell transmitted from an upper block so as to find a corresponding port and copy the same message to a paired port; The processor-to-processor lookback channel may include transmitting a standby side to an active side channel and a standby side to an active side channel when the standby side of the SMP is in a standby loading state from the active side.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The ATM switch according to the embodiment of the present invention is similar to FIG. Every cell receiving from the AMC unit 10 finds a corresponding port so that the same message can be duplicated in a port paired with the port. In other words, (0, 1), (2, 3) ... grouped so that messages can be simultaneously delivered to the A side and B side of the same hot link group. In addition, the processor that transmits a message to another processor transmits through a channel corresponding to the active VPI / VCI, and uses the VPI / VCI transmitted to the opposite processor only during the lookback test.

The transmitting side must have all channels corresponding to the VPI / VCI of the receiving processor, and the receiving side processor must have the channels corresponding to the VPI / VCI of the transmitting side. This channel refers to an ATM virtual channel, which is an asynchronous transmission method. In addition, each processor has a different VPI / VCI and communication based on it.

The transmitting processor transmits to the receiving VPI / VCI, but the VPI / VCI field corresponding to the ATM header is changed during delivery to the receiving side, and the VPI / VCI of the ATM cell header received by the receiving side is replaced with the VPI / VCI of the sending side. It is structured to be delivered.

Referring to the processor-to-processor ATM cell-based IPC transmission and reception method according to an embodiment of the present invention as follows.

First, all processors perform a lookback test to monitor the normality of the hot link, and need to send and receive messages with other processors. At this time, messages are exchanged through the active side channel. By transmitting and receiving, cell mixing does not occur, thereby enabling all desired communication.

First, when the CMDA unit 20 receives all the cells from the AMC unit 10, the cell is analyzed so that the cells can be copied to the paired group by analyzing the group of ports so that the cells are transferred regardless of the switching of the processor unit 30. Based on this structure, the SMP transmits messages sent to the standby side using the active channel when a standby loading request is made. The messages transmitted on the same channel do not change the order of the cells. Since reassembly is performed while maintaining the order from the CMDA unit 20, abnormal reception of the cell does not occur.

When transmitting a message to a redundant processor using the copy function of the CMDA unit 20, the message is transmitted using an active side channel, and the receiving side may select whether to process the message using only actual processor information included therein.

For example, suppose SMP and another processor have four channels as follows.

channel VPI / VCI Processor 2 1/24 SMP Active Side 3 1/25 SMP standby side 4 1/36 M processor active side

5 1/37 M processor standby side

Each processor has four channels of VPI / VCI information, that is, 1/24 (channel 2), 1/25 (channel 3), 1/36 (channel 4), and 1/37 (channel 5). If you look at the path of the message sent to the M processor, the M processor receives 1/24 (channel 2) of the message sent to the active side during standby loading, and in SMP, the channel sent to the M processor is 1/36 ( There is only channel 4) and the redundant M processor receives this message on 1/24 (channel 2).

Therefore, it is changed into 1/34 to 1/24 in the final receiver and reception is normally performed.

However, if the M processor transmits the active side and the standby side to different channels 1/36 (channel 3) and 1/37 (channel 4), the receiving side receives 1/24 (channel 2). This results in reception on 1/24 (channel 2) resulting in abnormal reception of messages.

I.e. 1/36 (cell giving SMP to active processor)-> 1/24 (when receiving) and 1/37 (cell giving SMP to standby processor)-> 1/24 (when receiving) Is received on the same channel, resulting in abnormal reassembly.However, if both active and standby side transmissions use VPI / VCI on the active side, only one channel is 1: 1. Transmission and reception are possible. When transmitting to the M processor, the standby transmits to channel 4 with active channel 5 only, which prevents abnormal reassembly of the cell when receiving, and communicates with active and standby using only one channel. The structure is small.

When the standby side of the SMP has a structure in which the standby side of the SMP is standbyly loaded from the active side, as shown in FIG. 2, the lookback channel between the processors is mixed with the lookback test cell and the standby loading cell. In the case of the lookback test message, the active is active, the standby is transmitted to standby, and the standby is transmitted to the standby channel and the standby is transmitted to the active side channel. Can be prevented. That is, if the SMP transmits to the active side at 1/25 (channel 3) and the standby is transmitted to 1/24 (channel 2), and the lookback test is performed, a normal message can be received even during standby loading.

Although the preferred embodiments of the present invention have been described in detail above, it will be understood by those skilled in the art that the present invention may be modified or modified in various ways. Therefore, changes of the embodiments of the present invention will not be able to escape the technical scope of the present invention.

As described above, the present invention has an effect of preventing abnormal reassembly when receiving a cell generated during inter-processor communication and during a processor self-lookback test.

Claims (5)

A cell multiplexing / demultiplexing unit for replicating the ATM cells received from the upper block in groups on the active and standby sides; The inter-processor ATM cell-based PC transceiver device comprising: a processor unit configured to transmit a message to a VPI / VCI channel of an active side of another processor. The method of claim 1, The processor unit, the AT-MS cell-based PC transceiver between the processor, characterized in that for transmitting the message transmitted to the standby side on the standby side request SMP. The method of claim 1, The cell multiplexer / demultiplexer, when receiving an ATM cell from an upper block, analyzes the group of ports, copies the cell to a paired group, and transfers the cell to an ATM cell-based PC transceiver device, characterized in that . Replicating the ATM cell transmitted from the upper block by searching for the corresponding port to generate the same message at the paired port; The processor-to-processor lookback channel includes the process of transmitting the standby side of the SMP from the active side to the standby side, the active side to the standby side channel, and the standby side to the active side channel. Seed transmission and reception method. The method of claim 4, wherein The process of replicating an ATM cell transmitted from the upper block to find a corresponding port so that the same message is generated in a paired port may include transmitting a message transmitted to a standby side by using an active channel when a standby loading request of the SMP is performed. APM cell-based PCC transmission and reception method between the processor, characterized in that made.