KR100428725B1 - Two-step self loopback test system and method in the recorded announcement equipment of a digital mobile switching center, especially concerned with conveniently executing the testing and maintenance of a circuit pack by configuring a self loopback test circuit in two steps - Google Patents
Two-step self loopback test system and method in the recorded announcement equipment of a digital mobile switching center, especially concerned with conveniently executing the testing and maintenance of a circuit pack by configuring a self loopback test circuit in two steps Download PDFInfo
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- KR100428725B1 KR100428725B1 KR1019960009524A KR19960009524A KR100428725B1 KR 100428725 B1 KR100428725 B1 KR 100428725B1 KR 1019960009524 A KR1019960009524 A KR 1019960009524A KR 19960009524 A KR19960009524 A KR 19960009524A KR 100428725 B1 KR100428725 B1 KR 100428725B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/20—Testing circuits or apparatus; Circuits or apparatus for detecting, indicating, or signalling faults or troubles
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M2203/00—Aspects of automatic or semi-automatic exchanges
- H04M2203/05—Aspects of automatic or semi-automatic exchanges related to OAM&P
- H04M2203/055—Aspects of automatic or semi-automatic exchanges related to OAM&P loopback testing
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- Computer Networks & Wireless Communication (AREA)
- Dc Digital Transmission (AREA)
- Mobile Radio Communication Systems (AREA)
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Abstract
Description
본 발명은 디지탈 이동통신 교환기 녹음 안내장치의 2단계 자체 루프백 시험 장치 및 방법에 관한 것으로, 특히 디지탈 이동통신 교환기 녹음 안내장치의 자체 루프백 시험 장치를 2단계로 구성하여 회로팩의 시험 및 유지보수를 간편하게 할 수 있도록 설계한 디지탈 이동통신 교환기 녹음 안내장치의 2단계 자체 루프백 시험 장치에 관한 것이다.The present invention relates to a two-stage self-loopback test apparatus and method of a digital mobile communication switch recording guide device, and in particular, a self-loopback test device of a digital mobile communication switch recording guide device is configured in two stages to test and maintain a circuit pack. The present invention relates to a two-stage self-loopback test apparatus for digital mobile communication switch recording guides designed for simplicity.
일반적으로 기존의 녹음 안내장치의 자체 루프백 시험 회로는 회로팩 내의 모든 펄스부호변조방식서브 하이웨이 경로를 포함하지 않으므로 자체 루프백 시험이 양호하더라도 회로팩의 펄스부호변조방식(PCM)서브 하이웨이 경로의 시험을 완전하게 실행하였다고 할 수 없었다.In general, the self-loopback test circuit of a conventional recording guide does not include all pulse-coded modulated sub-highway paths in the circuit pack, so even if the loopback test is satisfactory, the circuit-packed pulsed modulated (PCM) sub-highway path is tested. It could not be done completely.
이를 도면을 참조로 하여 설명하면 제 1 도에 도시한 바와 같이, 회로팩 내의 펄스 변조방식 서브하이웨이의 경로 중 SHWO 경로인 A/D 펄스부호 변조방식 디코더(11)와: 상기 A/D 펄스부호 변조방식 디코더(11)에서 받은 신호의 완충기적인 역할을 하는 버퍼(12,15)와; 상기 완충적 역할을 하는 버퍼(12,15)에서 들어온 신호를 트리거시켜 출력하는 디플립플롭(13,16,17)과: 상기 입력단의 신호에 의해 우 또는 좌로 자리보내기를 하는 쉬프트레지스터(18) 및 상기의 모든 신호선을 두개로 나눠 주는 대퍼런셜드라이브,리시브(14,20)로 구성된다.Referring to the drawings, as shown in FIG. 1, the A / D pulse code modulation scheme decoder 11 which is a SHWO path among the paths of the pulse modulation subhighway in the circuit pack and the A / D pulse code Buffers 12 and 15 serving as buffers of the signal received from the modulation scheme decoder 11; De-flip flops 13, 16, and 17 for triggering and outputting signals from the buffers 12 and 15 serving as buffers; and shift registers 18 for shifting right or left by signals from the input terminal. And a differential drive, receiving 14 and 20, which divides all the signal lines in two.
상기와 같이 구성되는 본 발명을 제 1 도를 참조하여 설명하면When explaining the present invention configured as described above with reference to FIG.
송신시 서브하이웨이 0의 A/D 펄스부호 변조방식 데이타는 A/D펄스 부호 변조방식 디코더(11)와 버퍼(12), 디플립플롭(13)을 거쳐 디퍼런셜드라이브(14)의 서브하이웨이 0채널로 출력되고, 서브하이웨이 1의 A/D펄스부호 변조방식 데이타는 버퍼(15), 디플립플롭(16)을 거쳐 디퍼런셜드라이브(14)의 서브하이웨이 1채널로 출력된다. 수신시 서브하이웨이 0의 펄스부호 변조방식 데이타는 디퍼런셜리시브(20)의 0채널을 통하여 버퍼(19), 쉬프트레지스터(18)를 통해 입력되며, 서브하이웨이 1의 펄스부호 변조방식 데이타는 디퍼런셜리시브(20)의 버퍼(19), 쉬프트레지스터(18)를 통해 입력된다.A / D pulse code modulation data of subhighway 0 is transmitted to the subhighway 0 channel of the differential drive 14 through the A / D pulse code modulation method decoder 11, the buffer 12, and the flip-flop 13. The A / D pulse code modulation system data of subhighway 1 is output to the subhighway 1 channel of the differential drive 14 through the buffer 15 and the flip-flop 16. Upon reception, the pulse code modulation method data of subhighway 0 is input through the buffer 19 and the shift register 18 through the 0 channel of the differential receive 20, and the pulse code modulation method data of the subhighway 1 is differential receive ( 20 is input via the buffer 19, the shift register 18.
1단계의 자체 루프백 시험 회로는 서브하이웨이 0의 경우 A/D 펄스부호 변조방식 디코더(11), 버퍼(12)에서 쉬프트레지스터(18)를 거쳐 디플립플롭(17)을 통하여 루프백 된다.The first loopback test circuit of the first stage is looped back through the deflip-flop 17 through the shift register 18 in the A / D pulse code modulation scheme decoder 11 and the buffer 12 in the case of the subhighway 0.
이렇게 기존의 녹음 안내장치의 루프백 장치는 회로팩 내의 모든 펄스부호변조방식 서브하이웨이 경로를 포함하지 않으므로 자체 루프백 시험이 양호하더라도 회로팩의 펄스부호변조방식 서브하이웨이 경로의 시험을 완전하게 실행 하였다고 할 수 없었고, 버퍼의 용량에 한계가 있으므로 모든 데이타가 돌아왔는지 확인하기 어려운 문제점이 있었다.Thus, the loopback device of the conventional recording guide device does not include all the pulse-coded modulation subhighway paths in the circuit pack, so even if the loopback test is satisfactory, the test of the pulse-code modulation subhighway path of the circuit pack is completely executed. There was a problem that it was difficult to check whether all the data was returned because there was a limit on the capacity of the buffer.
본 발명은 이러한 문제점을 해결하기 위한 것으로, 기존의 녹음 안내장치의 자체 루프백 시험 회로로 하고 타임 스위치와 인터페이스하는 드라이브부와 리시브부에서 입출력, 인에이블신호에 의해 동작하는 3상태버퍼(32,37)와; 상기 3상태 버퍼(32,37)에서 자체 시험이 필요할 경우 루프 인에이블 테스트를 열어주는 루프버퍼(35,40,44,46)에 2단계 자체 루프 백 시험 회로를 구성하여 2단계에 걸친 자체 루프백 시험을 통한 회로팩의 시험 및 유지보수에 신뢰성 부여를 특징으로 한다.The present invention has been made to solve this problem, and is a tri-state buffer (32, 37) operated by input / output and enable signals in a drive unit and a receiving unit which are self loopback test circuits of a conventional recording guide apparatus and interface with a time switch. )Wow; When the self test is required in the tri-state buffers 32 and 37, a 2-step self loopback test circuit is formed in the loop buffers 35, 40, 44, and 46 that open the loop enable test. Reliability is characterized by the testing and maintenance of circuit packs through testing.
제 2도의 구성 설명은 제 1도와 같으므로 생략한다.Since the configuration of FIG. 2 is the same as that of FIG. 1, it is omitted.
본 발명 녹음 안내 장치의 자체 루프 백 시험 회로를 제 2도에 도시한 바와 같이 동작을 설명하면 다음과 같다.Referring to FIG. 2, the loopback test circuit of the recording guide apparatus of the present invention is described as follows.
송신시 서브하이웨이 0의 A/D 펄스 변조방식 데이타는 A/D 펄스 변조방식 디코더(31)와 3상태버퍼(32), 버퍼(33), 디플립플롭(34)를 거쳐 디퍼런셜 드라이브의 0번 채널로 출력되고, 서브하이웨이 1의 A/D 펄스변조방식 데이타는3상태버퍼(37),버퍼(38),디플립플롭(39)을 거쳐 디퍼런셜 드라이브(45)의 1번 채널로 출력된다. 수신시 서브하이웨이 0의 펄스 변조방식 데이타는 디피런셜 리시브(45)의 0번 채널을 통하여 버퍼(44,43), 쉬프트레지스터(42)를 거쳐 입력되며, 서브하이웨이 1의 펄스변조방식 데이타는 디퍼런셜 리시브(45), 버퍼(46)를 거쳐 쉬프트레지스터(42)를 통하여 입력된다. 1단계의 자체 루프백 시험 회로는 서브하이웨이 0의 경우 A/D 펄스 변조방식 디코더(31), 3상태버퍼(32), 버퍼(33,43), 쉬프트레지스터(42)를 거쳐 디플립플롭(41)을 통해서 루프 백되며, 서브하이웨이 1의 경우는 3상태버퍼(37), 버퍼(38,43),쉬프트레지스터(42)를 거쳐 디플립플롭(41)으로 루프 백 된다.During transmission, A / D pulse modulation data of subhighway 0 is passed through the A / D pulse modulation decoder 31, the tri-state buffer 32, the buffer 33, and the flip-flop 34. The A / D pulse modulation method data of the subhighway 1 is outputted to the channel 1 of the differential drive 45 through the three-state buffer 37, the buffer 38, and the flip-flop 39. Upon reception, pulse modulation method data of subhighway 0 is input through buffers 44 and 43 and shift register 42 through channel 0 of differential receive 45, and pulse modulation method data of subhighway 1 is differential. It is input via the shift register 42 via the receive 45 and the buffer 46. The self-loopback test circuit of the first stage is a deflip-flop (41) through the A / D pulse modulation decoder 31, the tri-state buffer 32, the buffers 33 and 43, and the shift register 42 for the subhighway 0. In the case of subhighway 1, the loopback is performed through the tri-state buffer 37, the buffers 38 and 43, and the shift register 42 to the flip-flop 41.
그리고, 2단계의 자체 루프백 시험 회로는 서브하이웨이 0의경우 A/D 펄스 변조방식 디코더(31), 3상태버퍼(32), 버퍼(33), 디플립플롭(34), 버퍼(35)를 거쳐 디퍼런셜 드라이브(36)의 2번 채널을 통하여 디퍼런셜 리시브(45)의 0번 채널로 입력되어 버퍼(43,44), 쉬프트레지스터(42), 디플립플롭(41)으로 루프 백 되며 서브하이웨이 1의 경우 3상태버퍼(37), 버퍼(38), 디플립플롭(39), 버퍼(40)을 거쳐 디퍼런셜 드라이브(36)의 3번 채널을 통하여 디퍼런셜 리시브(45)의 1번 채널로 입력되어 버퍼(46),쉬프트레지스터(42),디플립플롭(41)으로 루프 백 된다.In addition, the self-loopback test circuit of the second stage uses the A / D pulse modulation decoder 31, the tri-state buffer 32, the buffer 33, the flip-flop 34, and the buffer 35 in the case of the subhighway 0. Through channel 2 of the differential drive 36, the channel is input to channel 0 of the differential receive 45 and looped back to the buffers 43 and 44, the shift register 42, and the flip-flop 41. In the case of the third state buffer 37, the buffer 38, the flip-flop 39, the buffer 40 through the channel 3 of the differential drive 36 is input to the channel 1 of the differential receive 45 Loop back to buffer 46, shift register 42, and flip-flop 41.
따라서, 종래의 녹음 안내장치의 자체 루프 백 시험회로는 회로팩내의 A/D 펄스 변조방식 서브하이웨이의 모든 경로를 시험하지 못하였으나 회로팩의 A/D 펄스 변조방식 서브하이웨이 경로의 최종단에서도 자체 루프 백 시험 회로를 구성함으로써, 회로팩의 A/D 펄스 변조방식 서브하이웨이 경로를 2단계에 걸쳐 루프 백시험을 통해 시험 및 유지보수를 간편하계 함으로써 생산성 및 신뢰성을 향상시키는 효과가 있다.Therefore, the loopback test circuit of the conventional recording guide apparatus does not test all the paths of the A / D pulse modulation subhighway in the circuit pack, but it can be used at the end of the A / D pulse modulation subhighway path of the circuit pack. By constructing the loop back test circuit, the A / D pulse modulation subhighway path of the circuit pack can be easily tested and maintained through the loop back test in two steps, thereby improving productivity and reliability.
제 1 도는 기존 녹음 안내장치의 자체 루프백 시험 장치의 회로도,1 is a circuit diagram of a self loopback test apparatus of an existing recording guide apparatus,
제 2 도는 본 발명의 회로도이다.2 is a circuit diagram of the present invention.
* 도면 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawing
11,31 : A/D 필스부호변조방식디코더 12,15,19,33,38,43 : 버퍼11,31: A / D Field Coded Modulation Decoder 12,15,19,33,38,43: Buffer
13,16,17,34,39,41 : 디플립플롭 18,42 : 쉬프터레지스터13,16,17,34,39,41: deflip-flop 18,42: shifter register
35,40,44,46 : 루프버퍼 14,36 : 디퍼런셜드라이브35,40,44,46: Loop buffer 14,36: Differential drive
20,45 : 디퍼런셜리시브 32,37 : 3상태 버퍼20,45: Differential 32,37: 3 state buffer
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KR1019960009524A KR100428725B1 (en) | 1996-03-30 | 1996-03-30 | Two-step self loopback test system and method in the recorded announcement equipment of a digital mobile switching center, especially concerned with conveniently executing the testing and maintenance of a circuit pack by configuring a self loopback test circuit in two steps |
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KR1019960009524A KR100428725B1 (en) | 1996-03-30 | 1996-03-30 | Two-step self loopback test system and method in the recorded announcement equipment of a digital mobile switching center, especially concerned with conveniently executing the testing and maintenance of a circuit pack by configuring a self loopback test circuit in two steps |
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KR100428725B1 true KR100428725B1 (en) | 2004-07-07 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR920002786A (en) * | 1990-07-06 | 1992-02-28 | 다움·콜프 | Cloned N-methylhydantoinase |
KR920011074A (en) * | 1990-11-30 | 1992-06-27 | 정몽헌 | Limit detector |
KR940000455A (en) * | 1992-06-02 | 1994-01-03 | 가와무라 요시부미 | Angiotensin II antagonistic imidazole, preparation method thereof and therapeutic use thereof |
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1996
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR920002786A (en) * | 1990-07-06 | 1992-02-28 | 다움·콜프 | Cloned N-methylhydantoinase |
KR920011074A (en) * | 1990-11-30 | 1992-06-27 | 정몽헌 | Limit detector |
KR940000455A (en) * | 1992-06-02 | 1994-01-03 | 가와무라 요시부미 | Angiotensin II antagonistic imidazole, preparation method thereof and therapeutic use thereof |
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