KR100392260B1 - Three Step Cell Searcher Using Partial Matched Filter for Asynchronous IMT 2000 DS-CDMA - Google Patents

Abstract

The present invention relates to a system for performing three-step cell searching according to the "3GPP" standard, which is an IMT2000 asynchronous DS-CDMA standard. In particular, the present invention relates to an input transmission signal that can be used for IMT2000 asynchronous DS-CDMA three-step synchronization acquisition. A signal aligner for time aligning with; A complex early and rate matched filter for obtaining a correlation value between an early signal output from the signal aligner multiplexed and a spread signal generated from a code generator; Squares and adders for obtaining complex energy from the correlation value delivered from the method filter and summing I / Q therefrom; A code generator for generating a spreading code necessary in three steps; A correlation energy comparator for comparing the correlation energy between the transmission signal and the spreading code and the threshold energy of each step; A classifier for extracting and sorting only a few correlation energies in order of magnitude; A synchronization point buffer which stores the correlation energy value and the position index obtained from the classifier; A searcher buffer for storing the correlation energy and the position index for the multipath having high verified correlation energy having passed through three steps, and transmitting the position to the lake receiver; And a two-stage synchronization for asynchronous IMT2000 using a partial correlator, wherein the code index of each slot is stored for each slot to obtain a code group, and a searcher controller for controlling all blocks of the synchronous obtainer. An acquisition device.

Description

Three-Step Cell Searcher Using Partial Matched Filter for Asynchronous IMT 2000 DS-CDMA}

The present invention relates to a system for effectively performing cell search in accordance with the "3GPP" standard, which is an IMT2000 asynchronous DS-CDMA standard. Specifically, the present invention relates to a cell search used for synchronization acquisition for IMT2000 asynchronous DS-CDMA. The present invention relates to a structure for supporting space time block coding based transmit antenna diversity (STTD) and time switched transmit diversity for SCH (TSTD) mode, and to an apparatus for synchronizing asynchronous IMT2000 using a partial correlator commonly used in a synchronization acquisition step.

In addition, the proposed correlator consists of a small matched filter, which enables the inverse spreading period by operating the adder tree and the integrator in multiples of the chip. It can be easily adjusted with an enable signal and occupies a small area.

In general, in the IMT2000 system, which is referred to as a next generation wireless communication means, the international communication organization "ITU" can transmit audio, video, and data signals anywhere in the world to one terminal through a wireless channel. Standards are being formulated, and the lower standardization body "3GPP TSG RAN WG1" is in the final stages of standards for physical channels.

In this case, the cell searcher (synchronous acquirer) used in the existing CDMA demodulator acquires synchronization using only a long spreading code, but in the case of IMT2000 asynchronous DS-CDMA, an additional "SCH" code is added for fast synchronization acquisition. As the overall structure required for motivation acquisition is different, the existing method cannot be applied as it is, so a new alternative should be proposed.

In addition, the matched filter used as a conventional correlator implements the adder tree as large as the integral interval to obtain correlation, and the despreading interval at each chip position is determined by the size of the matched filter. There is also a problem that it is difficult to apply them in common while changing the integration period in synchronizing acquisition of DS-CDMA.

That is, according to the asynchronous standard, the base station spreads the signal using a pseudo random number (PN) code, and thus the terminal acquires the synchronization of the code used for signal spreading at the base station to which the terminal belongs before solving the signal transmitted from the base station. The process must be preceded. In this case, the synchronous acquisition in the IMT2000 asynchronous scheme is different from the conventional schemes used in the IS-95A and B, and thus the conventional scheme cannot be applied to the aforementioned IMT2000 asynchronous scheme.

An object of the present invention for solving the above problems is to support the space-time block coding based transmit antenna diversity (STTD) and time switched transmit diversity for SCH (TSTD) mode of cell search used for synchronization acquisition for IMT2000 asynchronous DS-CDMA To provide a three-stage synchronization acquisition device for asynchronous IMT2000 using a partial correlator that can be jointly used in three stages.

In addition, in the present invention, as a condition for achieving the above object, a correlator is configured as a small matched filter, wherein the matched filter operates an adder tree and an integrator by multiples of chips. An additional purpose is to reduce the area occupied while allowing easy adjustment of the inverse spreading interval with an enable signal.

That is, as the necessity of designing a terminal in accordance with the "3GPP" standard has emerged, the present invention provides an effective design of a synchronization acquirer that is significantly different from the existing IS-A, B operation of a demodulator part of a wireless terminal of IMT2000 asynchronous DS-CDMA. Its purpose is to design its structure and optimal correlator.

1 is a diagram illustrating a main structure of a synchronization acquirer of a demodulator for an IMT2000 asynchronous DS-CDMA terminal according to the present invention;

2 is a diagram illustrating a structure of a synchronization obtainer internal correlator of a demodulator for an IMT2000 asynchronous DS-CDMA terminal according to the present invention;

3A to 3D are diagrams illustrating the structure of a synchronization acquirer internal code generator of a demodulator for an IMT2000 asynchronous DS-CDMA terminal according to the present invention;

4 is a diagram illustrating a correlator signal timing when the structure of FIGS.

FIG. 5 is a timing diagram of a correlator initial state signal when the structure of FIGS. 2 and 3 acquire a second stage synchronization; FIG.

6 is a timing diagram of a correlator execution state signal when the structure of FIGS. 2 and 3 acquires second stage synchronization;

7 is a diagram illustrating a correlator signal timing when the structure of FIGS. 2 and 3 acquires third-phase synchronization;

A feature of the present invention for achieving the above object is, in the system for performing three-step cell search according to the "3GPP" standard, which is an IMT2000 asynchronous DS-CDMA standard, which can be used for IMT2000 asynchronous DS-CDMA three-step synchronization acquisition A signal aligner for time-aligning the input transmission signal at an early, rate; A complex early and rate matched filter for obtaining a correlation value between an early signal output from the signal aligner multiplexed and a spread signal generated from a code generator; A square and adder that calculates complex energy from the correlation value delivered from the method filter and adds I / Q therefrom; A code generator for generating a spreading code necessary in three steps; A correlation energy comparator for comparing the correlation energy between the transmission signal and the spreading code and the threshold energy of each step; A classifier for extracting and sorting only a few correlation energies in order of magnitude; A synchronization point buffer which stores the correlation energy value and the position index obtained from the classifier; A searcher buffer for storing the correlation energy and the position index for the multipath having high verified correlation energy having passed through three steps, and transmitting the position to the lake receiver; And in the second step, a code index of each slot is stored for each slot to configure a SSCH buffer for obtaining a code group, and a searcher controller for controlling all blocks of the sync obtainer.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Looking briefly at the technical idea to be applied in the present invention, if you first look at the IMT2000 asynchronous method, when the base station spreads the signal using a pseudo random number (PN) code according to the asynchronous standard, the terminal decompresses the signal transmitted from the base station Prior to this, a process of acquiring synchronization of a code used for signal spreading is performed in a base station to which a terminal belongs. At this time, a process for acquiring synchronization is performed through three steps.

Accordingly, in the present invention, synchronization acquisition is performed using a common channel transmitted throughout the cell, such as a synchronization channel (SCH) and a common pilot channel (CPICH). Step Cell search is performed by dividing step by step.

The steps are outlined as follows.

The first step is to correlate the Rx stream transmitted from the base station with the primary SCH (PSCH) code generated by the terminal on a per chip basis (correlation detection). The process of detecting and hypothesizing the point as a boundary point of a slot of a signal having a transmission delay from the base station to the terminal is performed.

In the second step, the slot boundary point obtained in the first step is assumed as the slot boundary of the transmission signal, and the secondary SCH (SSCH) codes are synchronized based on this time boundary to obtain correlation for each code. The index of the SSCH code being transmitted is obtained. Using this, the boundary of the code group and the frame of the transmission signal is obtained.

Lastly, in the third step, the spreading code (PN) belonging to the code group obtained in the second step is synchronized with the frame boundary to obtain a correlation with the CPICH channel of the input transmission signal, and the spreading code of the current spreading code having the largest correlation code is obtained. Decide on

Hereinafter, each step will be described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a functional structure of a synchronization obtainer according to the 3GPP standard. In the third step, a signal aligner 6 aligns an input transmission signal at an early stage and a late stage. A code generator 9 for generating a necessary spreading code and a signal time-aligned and output from the signal aligner 6 are inputted through the multiplexing 7, 8 to generate a spreading signal generated by the code generator 9. The complex energy is calculated from the complex early and late matched filter (10, 11) for obtaining the correlation value and the correlation value transmitted from the matched filter (10, 11), and I / Q summed therefrom. A squarer and an adder (13), a correlation energy comparator (14) for comparing the correlation energy between the transmission signal and the spreading code and the threshold energy of each step, and sorting only a predetermined number of correlation energy in order of magnitude. Classifier (1 5), synchronization point buffers 16 and 17 storing correlation energy values and position indexes obtained from the classifier, and correlation energy and position indexes for multipaths having high verified correlation energy passing through the third step. Searcher buffers 18 and 19 for transmitting the position to the rake, and in the second step, the code index of each slot is stored for each slot to control the SSCH buffer 20 for obtaining the code group and all the blocks of the synchronous acquirer. It can be divided by the controller (23).

Looking at the operation according to the steps of each block of the synchronization obtainer as described above, as a first step, the input transport signal (RX stream) is the signal aligner 6 according to the Nyquist sampling theory The squarer and the adder which are divided into the early matched filter 10 and the rate matched filter 11 so as to perform searching in units of 1/2 chips, and obtain correlation energy for each chip of a transmission signal. (13) is designed such that the early, rate matched filters (10, 11) can be shared using a multiplexer (12), and the correlation energy comparator (14) has a first step threshold at each position ( threshold) and classify several chip positions through the classifier 15 in order of high energy values, and classify the correlation energy values and position indices into ibn, ad slots respectively to support the STTD and TSTD modes. According to the stores in each of the synchronization point buffer (16, 17).

In addition, as a second step, the hypothesis position point of the multi-pass slot to be verified stored in the sync point buffers 16 and 17 is determined by the early and rate matched filters 10 and 7 by the even and ad sync point buffers 16 and 17. 11) by synchronizing the SSCH codes at slot boundary points of the channel transmitted to the TSTD, and obtaining the correlation energy for each SSCH code for each slot through the squarer and the adder 13, and the correlation energy comparator ( 14) obtains the index of the SSCH code having the highest correlation energy by comparing with the second-stage threshold energy at each position, and stores the index in the SSCH buffer 20 in the order of ibn and ad slots, and then alternately stores the code group comparator. After performing comparison with each code group in step 22, the code group to which the current terminal belongs is determined, and the frame boundary is obtained and transmitted to the search controller 23. The second step For example, the slot position point of the expected sync point to be verified stored in the sync point buffers 16 and 17 is determined by the early and rate matched filters by the even and ad sync point buffers 16 and 17. Set to (10, 11), the CLK_buff1 control signal is used to store the received signal as BUFF_sig by SSCH code length only once every slot from the expected synchronization point. The received signal stored in the BUFF_sig is fixed for one slot. Simultaneously updating all SSCH codes that can be set for one slot to BUFF_code, the correlation energy for the received signal stored in BUFF_sig and each SSCH code is calculated for each slot through the squarer and adder 13, and the correlation energy comparator 14 ) Is compared with the delivered correlation energy and the second stage threshold energy for each SSCH code, and Find the index. The SSCH buffer 20 is filled by the number of slots K_SS allowed by the SSCH buffer 20 in slot units. (In the present embodiment, the SSCH buffer 20 of FIG. If the K_SS = 15 slots, the efficiency becomes better.) The representative SSCH code indexes in each of the slots thus obtained are in the order of even and child slots during TSTD transmission, and are alternately arranged in the SSCH buffer 20 in units of slots. SSCH code indices as many as K_SS stored in the SSCH buffer 20 and all slots of all code groups specified in the standard "3G TS 25.213 Table 4: Allocation of SSCs for secondary SCH" Compare all indexes sequentially. In this case, the code group comparator 22 multiplies the number of slots (K_SL) and the number of groups (K_GR) by the number of slots (K_SL) and group (K_GR) of the SSCH code indexes stored in the SSCH buffer 20 in K_SS units according to the slot order (K_SL * K_GR) Comparing as many times as possible, and calculates the largest code group and the slot position among the comparison result (number of slots with the same index <= K_SS), and determines the code group to which the current terminal belongs, based on the frame Finally, in the third step, the frame boundary of the hypothetical expected synchronization point obtained in the second step is set in the early or rate matched filter 10, 11. And spread the signals allocated to the code group to which the current code group belongs and the CPICH channel code by synchronizing with the frame boundary through the matched filters 10 and 11 for each spreading code. Find the correlation energy.

In this case, the means for obtaining the correlation energy is used as the square adder 13, the third stage threshold energy is compared with the correlation energy comparator 14, and then the index of the spreading code having the highest correlation energy is determined. After this, the spreading code index is transmitted to the searcher controller 23, and the comparison result of the correlation energy and the threshold energy transferred from the correlation energy comparator 14 in the second and third steps is compared with the searcher controller ( 23 determines whether to store hypothetical frame boundary positions and correlation energy values in the searcher buffers 18 and 19, and the results of the searcher buffers 18 and 19 are passed to the rake receiver.

FIG. 2 is an internal configuration diagram of complex early or rate matched filters 10 and 11 designed to be shared by the correlator according to the present invention in three stages for synchronization acquisition, and to obtain a BPSK and QPSK correlation energy. And the adder 36 is an externally located block and corresponds to the square and adder 13 shown in FIG. 1.

The adder of the square and adder 36 has an integrator structure and can support both BPSK and QPSK schemes as signal timing.

3A to 3D are internal configuration diagrams of the code generator 9 designed to share the correlator in three stages, and may be designed to be shared in the early and rate matched filters 10 and 11 individually or as one.

The following operation is based on the early matched filter 10, and similarly to the rate matched filter 11, the operation time for sharing the squarer and the adder 13 is different.

The early matched filter 10 integrates the AN (AN: 3, 7, 15, 31, 63, 127) adders 33 and the partially added result to obtain an integrator 34 to obtain a correlation value in the entire integration period. ) And BUFF_sig (30,31) for storing the input signal. In FIG. 2, AN = 7 is assumed for convenience of the example.

The matched filter (10,11) used is a small number (AN =) without using the same number of adders as the size of the integral section (W: 8, 16, 32, 64, 128, 256). By using the adder of (W / MC) -1), the addition is performed several times per chip (MC), and then the MC is controlled by varying the size of the integral (34). AN * MC) is a structure that can be performed.

At this time, the transmission signal stored in the BUFF_sig (30, 31) and the code stored in the BUFF_code (41, 42) is designed to be selectively output by AN + 1 by the multiplex (32, 43).

This structure requires clocking that is drained to the chip, and uses only the multirate clock that is available and adjusts the signal to the enable signal so that only the MC * chip rate clock is required.

The seven adders 33, which add correlations for eight code positions, have a tree structure like [{(A0 + A1) + (A2 + A3)} + {(A4 + 5) + (A6 + A7)}]. It is designed to have low output latency and uniform propagation delay, so it has low power consumption.

The multiplex 35 selects and outputs I, Q passes to share the squarer and adder 36 and the squarer and adder 36 is not in the early, rate-matched filters 10 and 11, respectively. Similar to the squarer and adder 13 of 1, there is only one outside the matched filter, which is also shared by the multiplexed 12 by the early, rate-matched filters 10 and 11.

The multiplex 40, 44 of FIG. 3B selectively outputs PSCH, SSCH, and spreading codes, and its operation is different according to three stages. In particular, the multiplex 44 has BPSK (first stage, second stage), and QPSK ( Third Step) Support Demodulation

4 to 7 summarize the signal control of the correlator according to the three stages according to the operation modes and stages. FIG. 4 shows the timing of each correlator signal when performing the first stage using the PSCH channel transmitted through the BPSK. Giving.

At the initial search time, BUFF_code (41,42) is initialized to PSCH code, and accordingly, input signals are input to BUFF_sig (30,31) one by one, and BUFF_code (41,42) and BUFF_sig (30,31) of FIFO are input. The difference is as follows. In the non-initial correlation detection state, BUFF_code (41,42) holds the PSCH code, but BUFF_sig (30,31) accepts the input signal one by one for each chip and has the PSCH code and transmission delay at that chip location. It serves as a typical matched filter that detects the correlation between transmitted signals and obtains a multipath position index.

At this time, multi-clocking (CLK_sum) is used for each chip and mux1_con is used to divide and add the transmission signals and codes stored in BUFF_sig (30,31) and BUFF_code (41,42) by the size of the adder tree 33. Integral 34 is used to set the correlation integral section. In FIG. 4, W = 64 and MC = 8 are illustrated.

In addition, since the early and rate matched filters 10 and 11 share the square and adder 13 as shown in FIG. 1, CLK_add is applied to each of the early and rate matched filters 10 and 11. It works. The mux2_con signal is plotted against the early matched filters 10 and 11.

5 shows signal timing in an initial state when acquiring the second stage synchronization, and FIG. 6 shows signal timing of the execution state when acquiring the second stage synchronization. Unlike FIG. 1, in FIG. It is not necessary to obtain a value, and only a SSCH code index of a corresponding slot having the largest correlation energy is obtained by obtaining a correlation value for each transmission signal and the number of SSCH codes in each slot.

5 is a diagram illustrating a process of initializing a transmission signal in BUFF_sig (30,31) and initializing the SSCH code to be verified first in BUFF_code (41,42) in a slot initial state of the second step, and adjusting to CLK_buff1. The BUFF_sig (30,31) is initialized and maintained in synchronization with the boundary of the hypothesis location point of the multipath slot to be verified stored in the sync point buffers 16 and 17 in the second step only once every slot, and controlled by CLK_buff. The BUFF_codes 41 and 42 obtain a correlation value between the transmission signal and the SSCH codes while updating the number of SSCHs to be verified for each slot. Multiclocking can be used to shorten the renewal time.

In addition, FIG. 6 shows an operation of a correlation state for every slot. In FIG. 6, a transmission signal stored in BUFF_sig (30, 31) and a code stored in BUFF_code (41, 42) are displayed when a specific SSCH code to be searched is renewed. The mux1_con is changed using the multiplexes 32 and 43, and the adder tree 33 is operated by selectively outputting AN + 1 once per clock, and the result is CLK_sum enabled using the integrator 34. In this way, correlation values are collected by the integral period.

In this process, the multiplex 32 and 43 scan the integral section set in each step, in whole or in part, of the signals stored in the BUFF_sig (30,31) and BUFF_code (41,42), and the integral section is maximum W. It is possible to set = <256 (SCH code length).

Finally, Figure 7 is a diagram illustrating the signal timing of the correlator in the third stage synchronization acquisition using the CPICH code.

In the third step, the operation of the correlator is similar to that in the second step, and the transmission signal is initialized to BUFF_sig (30,31) in synchronization with the frame boundary obtained in the second step, and the spreading code belonging to the code group is BUFF_code (41,42). ) And obtain the correlation energy for each spreading code.

When the spread code (PN) is initialized, it should be initialized with the P & P code belonging to the code group, and the multi-clock faster than the clock or the reference clock is applied to the P / N generator to move from the source position to the P & P location belonging to the code group. When the location is reached, the BUFF_code buffer is initialized with the P & P code generated from then on.

At this time, the initial condition of the PEN resist used at the start of the code is stored in the buffer, and using this initial value, it moves to the next PEN code position to be verified in the code group by clocking or multi-clock and then resets the BUFF_code buffer. Update

In the third step, as in the second step, the integration section is set by the method of addition after integration while scanning the multiplex, and in the third step, the CPICH channel is solved. Perform QPSK demodulation using CLK_sum.

While the invention has been shown and described in connection with specific embodiments thereof, it will be appreciated that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

As described above, according to the present invention, the IMT2000 asynchronous DS-CDMA synchronous obtainer has a structure suitable for supporting STTD and TSTD modes, and adds the matched filter 10, 11 to the adder tree 33 and the integrator 34. Its small size allows the despreading section to be controlled by the enable signal, which is advantageous for reducing power consumption and controlling the control signals of the matched filter (10, 11), the code generator (9), the squarer and the adder (13). Therefore, it can be commonly used in the three-step synchronization process, so the hardware complexity is low.

Claims (15)

In the asynchronous IMT2000 synchronization acquisition device using a partial correlator, A code generator for generating a spreading code; A signal aligner for time-aligning the input transmission signal RX stream used for IMT2000 asynchronous DS-CDMA synchronous acquisition by Early and Rate; A complex early and rate matched filter for obtaining a correlation value between a signal transmitted by multiplexing the early and rate signals output from the signal aligner and a spread signal generated by the code generator; A squared and adder for calculating complex energy from the correlation value delivered from the matched filter and then I / Q summing; A correlation energy comparator that compares correlation energy between spread codes generated by the code generator and threshold energy of each step to obtain an index of an SSCH code having the highest correlation energy; A classifier for selecting and sorting the correlation energy in order of magnitude; A sync point buffer that stores a correlation energy value and a position index obtained from the classifier; A searcher buffer for storing the correlation energy and the position index for the multipath having high verified correlation energy and transmitting the position to the rake receiver; An SSCH buffer receiving a code index of each slot from the correlation energy comparator and temporarily storing a code group for each slot; And A code group comparator for comparing the code groups stored in the SSCH buffer to determine a code group to which the current terminal belongs and to obtain a frame boundary; Asynchronous IMT2000 synchronization acquisition device using a partial correlator comprising a. The method of claim 1, And the matched filter is divided into a partial adder and an integrator, or a partial adder is configured as an adder array having a tree structure. The method of claim 2, The matched filter uses a small number (AN = (W / MC) -1) adder without using the same number of adders as the integral section size (W), and transfers the code stored in the buffer and the code stored in the buffer. Asynchronously using a partial correlator, which selectively outputs AN + 1 by multiplex and divides the addition of several times (MC), and then adjusts the number of additions according to the method of integrating to vary the integral section. IMT2000 Sync Acquisition Device. The method of claim 1, The signal aligner is a partial correlator for dividing and aligning the input transmission signal according to the Nyquist sampling theory so that the early, rate matched filter can perform searching in units of 1/2 chip. Asynchronous IMT2000 Synchronous Acquisition Device. delete The method of claim 1, In order to perform searching in 1/2 chip unit in the first step of the three-step synchronization acquisition process, the input signal is divided into early and rate matched filters, and a square and adder for obtaining the correlation energy for each chip of the transmission signal ( 36) uses multiplexes to allow early, rate matched filters to be shared, and a correlation energy comparator compares the first-stage threshold energy at each location, and classifies several chip locations in order of higher energy values. Asynchronous IMT2000 synchronization acquisition device using partial correlator which stores energy value and position index in sync point buffer according to even and ad slot, respectively to support STTD and TSTD modes. The method of claim 6, In the correlation detection state, the code buffer maintains the PSCH code, and the signal buffer receives the input signal one chip for each chip, and detects the correlation between the PSCH code and the transmission signal having the transmission delay at the chip position. Asynchronous IMT2000 synchronization acquisition device using a partial correlator characterized in that the multiplexer divides the transmission signals and codes stored in the signal buffer and the code buffer by the size of the adder tree, adds them, integrates them, and obtains a correlation value. The method of claim 1, In the second step of the three-step synchronization acquisition process, the hypothesis location points of the multipath slots to be verified stored in the synchronization point buffer are set to early and rate matched filters for each even and ad synchronization point buffer, and the SSCH codes are synchronized to synchronize each slot. For each SSCH code, obtain the correlation energy for each SSCH code, compare it with the second-stage threshold energy, obtain the index of the SSCH code with the highest correlation energy, and store it in the SSCH buffer in the order of ibn, ad slot, alternately. Asynchronous IMT2000 synchronization acquisition apparatus using a partial correlator characterized in that after performing a comparison with the group determines the code group to which the current terminal belongs, obtains the frame boundary and delivers to the searcher controller. The method of claim 8, Transmit signals and codes stored in the signal buffer and the code buffer selectively by scanning the integral section by multiplexing the stored codes and signals while resetting the number of code buffers to initialize and verify the signal buffers in each slot. Asynchronous IMT2000 synchronization acquisition device using a partial correlator, characterized in that by adding by dividing by the size of the adder tree, integrating the result and setting the integration section in an enable manner. The method of claim 1, The frame boundary of the hypothetical multipath is set in an early or rate matched filter, and the spreading codes and CPICH channel codes assigned to the code group belonging to the same are synchronized with the transmission signal to correlate with the transmission signal to correlate energy for each spreading code. After comparing the 3rd stage threshold energy with the 3rd stage threshold energy, obtain the index of the spreading code with the highest correlation energy, and transfer this spreading code index to the searcher controller and the correlation energy and the threshold transmitted from the correlation energy comparator in the 2nd and 3rd stages. The asynchronous IMT2000 synchronization acquisition device using the partial correlator characterized in that the searcher controller stores the home frame boundary position and the correlation energy value in the searcher buffer based on the comparison result of the energy and transmits the result of the searcher buffer to the lake receiver. The method of claim 10, Initializes signal buffer and code buffer and updates spreading codes belonging to the code group to code buffer, scans integral code by using multiplex and selectively transmits signals stored in signal buffer and code buffer And adding and dividing the code by the size of the adder tree and integrating the result to set the integration section in an enable manner. The method of claim 8 or 10, Asynchronous IMT2000 using a partial correlator characterized by controlling the squarer and adder 36 using the adder with an integrator structure as an enable signal and sharing the BPSK and QPSK schemes as a structure using the multiplex 44. Sync Acquisition Device. The method according to claim 10 or 11, wherein When the PN is initialized to the PEN code belonging to the code group at the time of PN initialization, it moves from the original position to the PEN code position belonging to the code group by applying a multi-clock which is several times faster than the clock or reference clock. Asynchronous IMT2000 synchronization acquisition device using a partial correlator. The method according to claim 10 or 11, wherein The initial condition of the PEN resist used at the start of the code is stored in the buffer, and using this initial value, the clock buffer or multi-clock is moved to the next PEN code position to be verified in the code group, and the code buffer is updated again. Asynchronous IMT2000 synchronization acquisition device using a partial correlator, characterized in that. delete