KR970072746A - The initial synchronization establishing circuit of the matched filter having the memory element - Google Patents

The initial synchronization establishing circuit of the matched filter having the memory element Download PDF

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Publication number
KR970072746A
KR970072746A KR1019960014062A KR19960014062A KR970072746A KR 970072746 A KR970072746 A KR 970072746A KR 1019960014062 A KR1019960014062 A KR 1019960014062A KR 19960014062 A KR19960014062 A KR 19960014062A KR 970072746 A KR970072746 A KR 970072746A
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South Korea
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sequence
matched filter
initial synchronization
circuit
length
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KR1019960014062A
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Korean (ko)
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KR0176105B1 (en
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임명섭
박형숙
손경열
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양숭택
한국전자통신연구원
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H04B1/7093—Matched filter type

Abstract

본 발명은 CDMA 이동통신의 수신부에서 기억소자를 갖는 정합필터의 초기동기확립회로에 관한 것이다.The present invention relates to an initial synchronization establishing circuit of a matched filter having a memory element in a receiver of a CDMA mobile communication.

종래 기술은 초기동기시간이 많이 소요되고, 그에 따른 하드웨어의 양이 많이 필요했던 문제점이 있었다.The prior art requires a large initial synchronization time and requires a large amount of hardware.

이를 해결하기 위해 본 발명은 수신된 의사잡음(PN) 시퀀스의 한 주기(L)를 임의의 부분적인 상관 구간(n)으로 나눈(L/n) 길이의 제1PN 시퀀스와 제1PN 스퀀스의 길이와 동일하게 CDMA 이동통신의 수신부에서 발생된 제2PN 시퀀스를 PN 시퀀스의 한 주기(L)가 될 때까지 논리 연산하는 정합필터와, 정합필터에서 논리 연산된 각 결과의 값이 프로세서의 제어에 의해 L/n시간마다 일시 기억되는 제1기억수단과, 제1기억수단에 기억된 각 결과값과 자체에 기억된 소정의 임계값을 비교 제어하기 위한 프로그램이 기억된 제2기억수단과, 제1기억수단에 기억된 각 결과값의 총합값을 구하고, 그 총합값을 상기 제2기억수단에 기억된 임계값과의 비교에 따라 초기 동기를 확립하는 프로세서로 구성된 것이다.In order to solve the above problem, the present invention provides a method for decoding a PN sequence of a length of a first PN sequence having a length of (L / n) length obtained by dividing one period (L) of a received pseudo noise (PN) sequence by an arbitrary partial correlation period (n) (L) of the PN sequence until the value of the second PN sequence generated in the receiving part of the CDMA mobile communication becomes equal to one period (L) of the PN sequence, and a value of each result logically calculated in the matched filter Second storing means for storing a program for comparing and controlling each result value stored in the first storing means with a predetermined threshold value stored in the first storing means; And a processor for obtaining a total value of the respective result values stored in the storage means and establishing initial synchronization by comparing the total value with the threshold value stored in the second storage means.

Description

기억소자를 갖는 정합필터의 초기동기확립회로The initial synchronization establishing circuit of the matched filter having the memory element

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따른 초기동기확립회로의 블록 구성도.FIG. 3 is a block diagram of an initial synchronization establishing circuit according to the present invention; FIG.

Claims (7)

직접 시퀀스 확산 스펙트럼 통신을 이용한 CDMA 이동통신에서 초기동기를 확립하기 위한 회로에 있어서, 수신된 의사잡음(PN) 시퀀스의 한 주기(L)를 임의의 부분적인 상관구간(n)으로 나눈(L/n) 길이의 제1PN 시퀀스와 상기 제1PN 시퀀스의 길이와 동일하게 상기 CDMA 이동통신의 수신부에서 발생된 제2PN 시퀀스를 상기 PN 시퀀스의 한 주기(L)가 될 때까지 논리 연산하는 정합필터와, 상기 정합필터에서 논리 연산된 각 결과의 값이 프로세서의 제어에 의해 L/n시간마다 일시 기억되는 제1기억수단과, 상기 제1기억수단에 기억된 각 결과값과 자체에 기억된 소정의 임계값을 비교 제어하기 위한 프로그램이 기억된 제2기억수단과, 상기 제1기억수단에 기억된 각 결과값의 총합값을 구하고, 그 총합값을 상기 제2기억수단에 기억된 임계값과의 비교에 따라 초기 동기를 확립하는 프로세서로 구성된 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.A circuit for establishing initial synchronization in a CDMA mobile communication using direct sequence spread spectrum communication, the circuit comprising: means for dividing one period (L) of a received pseudo noise (PN) sequence by an arbitrary partial correlation interval (n) a first PN sequence having a length equal to the length of the first PN sequence and a second PN sequence generated at a receiver of the CDMA mobile communication with a length equal to the length of the first PN sequence until a period (L) A first memory means for temporarily storing the values of the results logically computed in the matched filter by L / n times under the control of the processor, and a second memory means for storing each result value stored in the first memory means, Calculating a sum value of each result value stored in the first storage means and comparing the sum value with a threshold value stored in the second storage means; According to the initial motivation And a processor for establishing an initial synchronization of the matched filter. 제1항에 있어서, 상기 정합필터는 상기 제1PN 시퀀스를 입력받는 입력 데이타용 쉬프트 레지스터와, 상기 입력 데이타용 쉬프트 레지스터에 입력된 제1PN 시퀀스의 순서와 맞추기 위해 상기 수신부에서 조정되는 클럭에 따라 발생된 상기 제2PN 시퀀스가 입력되는 수신용 쉬프트 레지스터와, 상기 입력 데이타용 쉬프트 레지스터에 입력된 제1PN 시퀀스와 상기 수신용 쉬프트 레지스터에서 발생된 제2PN 스퀀스가 동일한지를 판단하기 위해 논리 연산하는 논리 연산부로 구성된 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.2. The apparatus of claim 1, wherein the matched filter comprises: a shift register for input data to which the first PN sequence is input; and a second PN sequence generated according to a clock adjusted by the receiving unit to match the order of the first PN sequence input to the shift register for input data And a logic operation unit for performing logic operation to determine whether the first PN sequence input to the shift register for input data and the second PN sequence generated in the reception shift register are identical to each other And the initial synchronization establishing circuit of the matched filter having the memory element. 제2항에 있어서, 상기 논리 연산부는 상기 제1PN 시퀀스가 상기 제2PN 시퀀스를 배타적 논리합하는 다수개의 상관기와, 상기 다수개의 상관기에 의해 각각 배타적 논리합된 결과를 논리 반전시키는 인버터로 구성되어, 상기 제1PN 시퀀스와 상기 제2PN 시퀀스가 동일한지를 판단하는 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.3. The apparatus of claim 2, wherein the logic operation unit comprises: a plurality of correlators for the first PN sequence for exclusive-ORing the second PN sequence; and an inverter for logically inverting the result of the exclusive OR operation performed by the plurality of correlators, And determines whether or not the 1PN sequence and the second PN sequence are identical to each other. 제1항 또는 제3항에 있어서, 상기 다수개의 상관기는 상기 제1PN 시퀀스의 부분적인 상판구간(n)에 상응한 수인 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.The initial synchronization establishing circuit of a matched filter according to any one of claims 1 to 3, wherein the plurality of correlators is a number corresponding to a partial top plate section (n) of the first PN sequence. 제1항에 있어서, 상기 제1기억수단은 램(RAM)으로 구성된 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.2. The initial synchronization establishing circuit of a matched filter according to claim 1, wherein the first storage means comprises a RAM. 제1항에 있어서, 상기 제2기억수단은 램(RO)으로 구성된 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.2. The initial synchronization establishing circuit of a matched filter as claimed in claim 1, wherein the second memory means comprises a ram (RO). 제1항에 있어서, 상기 프로세서는 상기 L/n 시간마다 제2PN 시퀀스를 발생하는 것을 특징으로 하는 기억소자를 갖는 정합필터의 초기동기확립회로.2. The initial synchronization establishing circuit of a matched filter according to claim 1, wherein the processor generates a second PN sequence every L / n time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960014062A 1996-04-30 1996-04-30 Initial synchronizing circuits of matched filter with memory equipment KR0176105B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361794B1 (en) * 1999-03-03 2002-11-22 가부시키가이샤 히타치세이사쿠쇼 Mobile station, base station and synchronizing control method thereof
KR100386575B1 (en) * 2000-03-09 2003-06-02 엘지전자 주식회사 PN code correlator and Method for acquisition received signal's synchronization using the same
KR100392260B1 (en) * 2000-01-27 2003-07-22 한국전자통신연구원 Three Step Cell Searcher Using Partial Matched Filter for Asynchronous IMT 2000 DS-CDMA
KR100434471B1 (en) * 1999-05-15 2004-06-05 삼성전자주식회사 Appatatus and method for generating frame sync word and verifying the frame sync word in w-cdma communication system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361794B1 (en) * 1999-03-03 2002-11-22 가부시키가이샤 히타치세이사쿠쇼 Mobile station, base station and synchronizing control method thereof
KR100434471B1 (en) * 1999-05-15 2004-06-05 삼성전자주식회사 Appatatus and method for generating frame sync word and verifying the frame sync word in w-cdma communication system
KR100392260B1 (en) * 2000-01-27 2003-07-22 한국전자통신연구원 Three Step Cell Searcher Using Partial Matched Filter for Asynchronous IMT 2000 DS-CDMA
KR100386575B1 (en) * 2000-03-09 2003-06-02 엘지전자 주식회사 PN code correlator and Method for acquisition received signal's synchronization using the same

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