KR100388470B1 - Method for etching semiconductor device using anti-reflective coating - Google Patents
Method for etching semiconductor device using anti-reflective coating Download PDFInfo
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- KR100388470B1 KR100388470B1 KR10-2000-0077842A KR20000077842A KR100388470B1 KR 100388470 B1 KR100388470 B1 KR 100388470B1 KR 20000077842 A KR20000077842 A KR 20000077842A KR 100388470 B1 KR100388470 B1 KR 100388470B1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/31127—Etching organic layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
본 발명은 고온 식각 공정에 의한 패턴의 휘어짐을 방지하도록 한 반사방지막을 이용한 반도체소자의 식각 방법에 관한 것으로, 반도체기판상에 피식각층을 형성하는 단계, 상기 피식각층상에 반사방지 목적의 두께보다 두꺼운 1000Å∼5000Å의 두께를 갖는 반사방지막을 형성하는 단계, 상기 반사방지막상에 감광막을 도포하고 노광 및 현상으로 상기 감광막을 패터닝하는 단계, 상기 패터닝된 감광막을 이용하여 상기 반사방지막을 식각하는 단계, 및 상기 패터닝된 감광막과 상기 패터닝된 반사방지막을 이용하여 상기 피식각층을 식각하는 단계를 포함하여 이루어진다.The present invention relates to an etching method of a semiconductor device using an anti-reflection film to prevent the bending of the pattern by a high temperature etching process, the method comprising: forming an etched layer on the semiconductor substrate, the thickness of the anti-reflective object on the etched layer Forming an antireflection film having a thickness of 1000 Å to 5000, thick, applying a photoresist film on the antireflection film and patterning the photoresist film by exposure and development, etching the antireflection film using the patterned photoresist film, And etching the etched layer by using the patterned photoresist and the patterned antireflection film.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 반사방지막(Anti Reflective Coating; ARC)을 이용한 반도체소자의 식각 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an etching method of a semiconductor device using an anti-reflective coating (ARC).
최근에 소자의 집적도가 증가함 따라 CD(Critical Demension)도 비례하여 작아지는 추세에 있다.Recently, as the degree of integration of devices increases, the critical dimension (CD) also decreases in proportion.
통상적으로 1M(Megabit)급 소자에서는 0.81㎛, 64M급 소자에서는 0.351㎛, 256M급 소자에서는 0.251㎛ 그리고 1G급 소자에서는 0.181㎛로 작아지고 있다. 따라서 패터닝을 위한 노광방법도 종래 i- 라인에서 DUV(Deep UV) 노광 방법으로 전환되고 있다.In general, the size of the 1M (Megabit) device is 0.81㎛, 0.351㎛ for 64M devices, 0.251㎛ for 256M devices and 0.181㎛ for 1G devices. Therefore, the exposure method for patterning has also been converted from the i-line to the DUV (Deep UV) exposure method.
반사방지막(ARC)은 아로메틱 폴리설폰(Aromatic polysulfone) 구조를 가지며, 즉, 반사방지막을 구성하는 구성물이 아르메틱 폴리셜폰 구조를 가질 경우에 DUV(Deep Ultraviolet) 마이크로 리소그래피(Micro lithography)에 대해 유용한 반사방지막으로 사용된다.The anti-reflection film (ARC) has an aromatic polysulfone structure, that is, useful for deep ultraviolet micro lithography (DUV) when the constituents of the anti-reflection film have an armetic polyphone structure. Used as an antireflection film.
일반적으로 반사방지막(ARC)의 일부인 하부반사방지막(Bottom ARC; BARC)은 유기(Organic) 성분과 무기(Inorganic) 성분으로 구분되며 유기성분의 반사방지막은 포토레지스트(Photoresist)와 같은 C, H, O 등의 성분을 가지며 점도가 높은 특성이 있다.In general, the bottom anti-reflective coating (Bottom ARC; BARC), which is a part of the anti-reflective coating (ARC), is classified into an organic component and an inorganic component. The anti-reflective coating of the organic component is C, H, or the like as the photoresist. It has a component such as O and has high viscosity.
그리고, 무기성분의 반사방지막은 SiO2계열 또는 카본(C) 계열이 주성분이다.In addition, the inorganic antireflection film is mainly composed of SiO 2 series or carbon (C) series.
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 식각 방법을 도시한 단면도이고, 도 2a 내지 도 2b는 감광막의 휘어짐을 이용한 피식각층의 식각방법을 도시한 평면도이다.1A to 1D are cross-sectional views illustrating an etching method of a semiconductor device according to the related art, and FIGS. 2A to 2B are plan views illustrating an etching method of an etching target layer using bending of a photosensitive film.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 선택적으로 식각되고자 하는 피식각층(12)을 형성한 후, 피식각층(12)상에 반사방지막(13)을 형성한다. 반사방지막(13)상에 감광막(14)을 도포하고 노광 및 현상으로 감광막(14)을 패터닝한다.As shown in FIG. 1A, after forming an etched layer 12 to be selectively etched on the semiconductor substrate 11, an anti-reflection film 13 is formed on the etched layer 12. The photosensitive film 14 is coated on the antireflection film 13 and the photosensitive film 14 is patterned by exposure and development.
여기서, 통상적으로 반사방지의 목적으로 사용되는 반사방지막(13)은 1000Å 이하의 두께로 형성된다.Here, the anti-reflection film 13 which is usually used for the purpose of anti-reflection is formed to a thickness of 1000 Å or less.
도 1b에 도시된 바와 같이, 패터닝된 감광막(14)을 이용하여 반사방지막(13)을 식각한다. 이 때, 반사방지막(13a) 형성시, 감광막(14)은 소정 두께만큼 손실된다. 도면부호 14a는 손실된 감광막을 나타낸다.As shown in FIG. 1B, the anti-reflection film 13 is etched using the patterned photoresist 14. At this time, when the antireflection film 13a is formed, the photosensitive film 14 is lost by a predetermined thickness. Reference numeral 14a denotes a lost photoresist film.
도 1c에 도시된 바와 같이, 감광막(14a)을 이용하여 피식각층(12)을 식각한다. 이 때, 감광막(14a)은 식각량이 더욱 증가되어 등방성 프로파일을 가진다(14b).As shown in FIG. 1C, the etched layer 12 is etched using the photosensitive film 14a. At this time, the photoresist 14a has an increased amount of etching, thereby having an isotropic profile (14b).
일반적으로 감광막은 열에 약해서 온도가 보통 130℃∼150℃ 이상 상승하면 연화되어 플로잉(Flowing) 현상이 발생되며, 두께가 소정량 손실된 감광막(14a)을 이용하여 피식각층(12)을 식각할 때, 챔버내 온도가 200℃∼250℃까지 상승하므로 반도체기판(11)의 뒷면에서 열을 식히도록 하지만, 식각량이 지나치게 많은 경우, 표면의 열로 인한 감광막(14a)의 플로잉 현상이 발생하여 감광막(14b)이 휘어진다(도 2a 참조).In general, the photoresist film is weak to heat and is softened when the temperature rises above 130 ° C. to 150 ° C., thereby causing a flow phenomenon, and the etching target layer 12 may be etched using the photoresist film 14a having a predetermined thickness loss. At this time, since the temperature in the chamber rises from 200 ° C to 250 ° C, the heat is cooled on the back side of the semiconductor substrate 11, but if the etching amount is too large, the flow phenomenon of the photosensitive film 14a due to the surface heat occurs and the photosensitive film 14b is bent (see FIG. 2A).
도 1d에 도시된 바와같이, 휘어진 감광막(14b)과 반사방지막(13a)을 이용하여 피식각층(12)을 식각한다.As shown in FIG. 1D, the etched layer 12 is etched using the curved photosensitive film 14b and the anti-reflection film 13a.
그러나, 도 2b에 도시된 것처럼, 휘어진 감광막(14b)을 이용하여 피식각층(12)을 식각하게 되면 식각된 피식각층(12a)도 휘어진 형태로 형성된다.However, as shown in FIG. 2B, when the etched layer 12 is etched using the curved photosensitive film 14b, the etched layer 12a is also formed in a curved shape.
상술한 바와 같이, 종래기술은 식각량이 많은 공정에서 감광막이 고열을 견디지 못해 패턴이 휘어지는 문제점이 있다.As described above, the prior art has a problem in that the photoresist film does not endure high heat in the etching process and the pattern is bent.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 식각량이 많은 공정에서 감광막의 휘어짐에 따른 피식각층의 휘어짐을 방지하는데 적합한 반사방지막을 이용한 반도체소자의 식각 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide an etching method of a semiconductor device using an anti-reflection film suitable for preventing the bending of the etched layer due to the bending of the photosensitive film in the process having a large amount of etching. .
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 식각 방법을 도시한 단면도,1A to 1D are cross-sectional views illustrating an etching method of a semiconductor device according to the prior art;
도 2a 내지 도 2b는 감광막의 휘어짐을 이용한 피식각층의 식각방법을 도시한 평면도,2A to 2B are plan views illustrating an etching method of an etching target layer using the bending of the photosensitive film;
도 3a 내지 도 3c는 본 발명의 실시예에 따른 반사방지막을 이용한 반도체소자의 식각 방법을 도시한 도면.3A to 3C illustrate an etching method of a semiconductor device using an anti-reflection film according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 피식각층21 semiconductor substrate 22 etched layer
23 : 반사방지막 24 : 감광막23: antireflection film 24: photosensitive film
상기 목적을 달성하기 위한 본 발명의 반사방지막을 이용한 반도체소자의 식각 방법은 반도체기판상에 피식각층을 형성하는 단계, 상기 피식각층상에 반사방지 목적의 두께보다 두꺼운 1000Å∼5000Å의 두께를 갖는 반사방지막을 형성하는 단계, 상기 반사방지막상에 감광막을 도포하고 노광 및 현상으로 상기 감광막을 패터닝하는 단계, 상기 패터닝된 감광막을 이용하여 상기 반사방지막을 식각하는 단계, 및 상기 패터닝된 감광막과 상기 패터닝된 반사방지막을 이용하여 상기 피식각층을 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.In the etching method of the semiconductor device using the anti-reflection film of the present invention for achieving the above object, forming an etching target layer on the semiconductor substrate, the reflection having a thickness of 1000 ~ 5000Å thicker than the thickness of the anti-reflection purpose on the etching target layer Forming a protective film, applying a photoresist film on the antireflection film, patterning the photoresist film by exposure and development, etching the antireflection film using the patterned photoresist film, and etching the patterned photoresist film and the patterned photoresist film. And etching the etched layer by using an anti-reflection film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3c는 본 발명의 실시예에 따른 반사방지막을 이용한 반도체소자의 식각 방법을 도시한 도면이다.3A to 3C illustrate an etching method of a semiconductor device using an anti-reflection film according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체기판(21)상에 선택적으로 식각되고자 하는 피식각층(22)을 형성한 후, 피식각층(22)상에 반사방지막(23)을 형성한다. 반사방지막(23)상에 감광막(24)을 도포하고 노광 및 현상으로 감광막(24)을 패터닝한다.As shown in FIG. 3A, after the etching target layer 22 to be selectively etched is formed on the semiconductor substrate 21, an anti-reflection film 23 is formed on the etching target layer 22. The photoresist film 24 is coated on the antireflection film 23 and the photoresist film 24 is patterned by exposure and development.
여기서, 반사방지막(23)은 유기반사방지막 또는 무기반사방지막 중 어느 하나를 이용해도 무방하며, 1000Å∼5000Å의 두께(d)로 형성된다.Here, the antireflection film 23 may use either an organic antireflection film or an inorganic antireflection film, and is formed to have a thickness d of 1000 kPa to 5000 kPa.
도 3b에 도시된 바와 같이, 패터닝된 감광막(24)을 이용하여 반사방지막(23)을 식각한다. 이 때, 반사방지막(23a) 형성시, 감광막(24)은 소정 두께만큼 손실되어 등방성 프로파일을 갖는 감광막(24a)이 형성되는데, 그 이유는 두께가 증가한 반사방지막(23)을 식각할 때 많은 양의 감광막이 손실되기 때문이다.As shown in FIG. 3B, the anti-reflection film 23 is etched using the patterned photoresist 24. At this time, when the anti-reflection film 23a is formed, the photoresist film 24 is lost by a predetermined thickness to form a photoresist film 24a having an isotropic profile, because a large amount is used when etching the anti-reflection film 23 having an increased thickness. This is because the photosensitive film of is lost.
도 3c에 도시된 바와 같이, 감광막(24a)외에 반사방지막(23a)을 이용하여 피식각층(22)을 식각한다. 이 때, 감광막(24a)은 식각량이 더욱 증가되어 완전히 손실되며, 반사방지막(23b)은 피식각층(22)을 식각할 때 소량 손실되어 상측 부분이 등방성 프로파일을 갖는다.As shown in FIG. 3C, the etching target layer 22 is etched using the anti-reflection film 23a in addition to the photosensitive film 24a. At this time, the photoresist film 24a is completely lost because the etching amount is further increased, and the anti-reflection film 23b is slightly lost when the etching layer 22 is etched so that the upper portion has an isotropic profile.
여기서, 통상의 기술처럼 피식각층(22)을 식각할 때 고온(200℃ 이상)에서 이루어지나, 반사방지막(23b)은 열에 매우 강한 특성이 있어 고온에서도 연화가 발생되지 않는다. 따라서, 피식각층(22)의 두께가 두꺼워 식각량이 많을 경우에도 휘어지지 않는다.In this case, the etching layer 22 is formed at a high temperature (200 ° C. or more) as in the conventional art, but the anti-reflection film 23b is very resistant to heat, and thus softening does not occur even at a high temperature. Therefore, the thickness of the etched layer 22 is so thick that it does not bend even when the etching amount is large.
상술한 바와 같이, 동일한 두께의 피식각층을 식각할 때, 식각량이 많은 경우 반사방지막의 두께를 증가시키고, 반사방지막을 이용하여 피식각층을 식각하면 패턴이 휘어지지 않는다.As described above, when the etching layer having the same thickness is etched, when the etching amount is large, the thickness of the anti-reflection film is increased, and when the etching layer is etched using the anti-reflection film, the pattern is not bent.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반사방지막을 이용한 반도체소자의 식각 방법은 고온에서 우수한 내열성을 가지는 반사방지막을 이용하여 피식각층을 식각하므로써, 식각량이 과도한 경우에도 패턴의 휘어짐을 방지할 수 있는 효과가 있다.The etching method of the semiconductor device using the anti-reflection film of the present invention as described above by using the anti-reflection film having excellent heat resistance at high temperature to etch the layer to be etched, there is an effect that can prevent the bending of the pattern even if the etching amount is excessive. .
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